Power supply circuit
阅读说明：本技术 电源电路 (Power supply circuit ) 是由 吉冈透 笛木洋一 于 2020-03-19 设计创作，主要内容包括：本发明提供一种能够抑制泄漏电流增大的电源电路。在主低压差部(1)于通常动作时输出第一内部电压(Vin1)且副低压差部(2)在睡眠动作时输出睡眠电压(Vsp)的电源电路(PS)中,对晶体管(TR1)的漏极施加睡眠电压(Vsp),对栅极及背栅极施加比睡眠电压高的外部电压(Vex)。(The invention provides a power supply circuit capable of suppressing increase of leakage current. In a power supply circuit (PS) in which a main low-voltage difference part (1) outputs a first internal voltage (Vin1) during a normal operation and a sub low-voltage difference part (2) outputs a sleep voltage (Vsp) during a sleep operation, the sleep voltage (Vsp) is applied to the drain of a transistor (TR1), and an external voltage (Vex) higher than the sleep voltage is applied to the gate and the back gate.)
1. A power supply circuit that switches to a sleep operation following a normal operation, comprising:
a sub-low voltage difference unit that generates a sleep voltage, which is a voltage used for the sleep operation, and outputs the sleep voltage to an output terminal during the sleep operation;
a P-channel metal oxide semiconductor transistor in which a source is connected to a first internal voltage corresponding to a magnitude of a voltage applied to a gate and a voltage of the drain defined by a magnitude control of a current flowing between the source and the drain is output to the output terminal during the normal operation; and
and a main low dropout portion which applies another voltage higher than the sleep voltage to the gate and the back gate of the PMOS transistor during the sleep operation.
2. The power supply circuit of claim 1, further comprising:
a second P-channel metal oxide semiconductor transistor having a source connected to the other voltage and a drain connected to the gate of the P-channel metal oxide semiconductor transistor;
a third P-channel metal oxide semiconductor transistor having a source connected to the first internal voltage and a drain connected to the back gate of the P-channel metal oxide semiconductor transistor; and
a fourth PMOS transistor having a source connected to the other voltage and a drain connected to the back gate of the PMOS transistor,
in the normal operation, the third PMOS transistor is in an ON state, and the second PMOS transistor and the fourth PMOS transistor are in an OFF state,
during the sleep mode, the third P-channel mos transistor is in a blocking state, and the second P-channel mos transistor and the fourth P-channel mos transistor are in a conducting state.
Technical Field
The present invention relates to a power supply circuit.
Background
The power supply circuit disclosed in patent document 1 suppresses current consumption due to leakage (leak) by a switch (switch).
[ Prior art documents ]
[ patent document ]
Patent document 1: japanese patent laid-open No. 2001-147746
Disclosure of Invention
[ problems to be solved by the invention ]
In association with the suppression of the current consumption, for example, in a power supply circuit used in a wireless system, a normal operation and a sleep (sleep) operation in which only a minimum operation is required are alternately switched in time series. In a power supply circuit, basically, an operation of outputting a voltage to an output terminal of the power supply circuit is performed by a main Low Dropout (LDO) unit in a normal operation, and is performed by a sub LDO unit in a sleep operation. In the former case, as shown in fig. 3, the
In order to stabilize the level of the second internal voltage Vin2 to be output during the normal operation, the main LDO10 has a feedback (feedback) system. The feedback system includes an amplifier a10, a transistor (resistor) TR10 (e.g., a P-channel Metal-Oxide-Semiconductor Field-effect transistor (PMOSFET)), a switch SW10, and resistors R10 and R20. The amplifier a10 differentially amplifies a reference voltage Vref (e.g., 1.2V) output from a bias unit (not shown) and a divided voltage Vdiv (e.g., about 1.2V) defined by dividing the second internal voltage Vin2 by the resistor R1 and the resistor R2, and outputs a voltage Vg (gate voltage Vg) obtained by the differential amplification to the gate of the
On the other hand, when switching from the normal operation to the sleep operation in response to the control signal CT, the DC/DC converter unit stops operating in comparison with the normal operation. However, in the normal operation before the sleep state, the first internal voltage Vin1 which is output from the DC/DC converter section and applied to the source and the back gate of the transistor TR10 gradually decreases due to an influence of an element (for example, a smoothing capacitor) connected between the output terminal of the DC/DC converter section and the ground. As a result, the first internal voltage Vin1 is lower than an output voltage (sleep voltage) from a sub LDO unit (not shown) applied to the output terminal TM. That is, in the transistor TR10, the first internal voltage Vin1 applied to the source and the back gate becomes lower than the sleep voltage applied to the drain. Thus, a forward voltage is applied to a body diode (not shown) of the transistor TR10, which results in an increase in leakage current in the
The invention provides a power supply circuit capable of suppressing increase of leakage current.
[ means for solving problems ]
In order to solve the above problem, a power supply circuit according to the present invention is a power supply circuit that switches to a sleep operation after a normal operation, the power supply circuit including:
a sub LDO unit that generates a sleep voltage, which is a voltage used for the sleep operation, during the sleep operation, and outputs the sleep voltage to an output terminal;
a PMOS transistor having a source connected to a first internal voltage during the normal operation, and outputting a second internal voltage to the output terminal, the second internal voltage being a voltage of the drain defined by controlling a magnitude of a current flowing between the source and the drain; and
and a main LDO unit that applies another voltage higher than the sleep voltage to the gate and the back gate of the PMOS transistor during the sleep operation.
[ Effect of the invention ]
In the power supply circuit according to the present invention, in the main LDO unit, the PMOS transistor applies the sleep voltage from the sub LDO unit to the drain via the output terminal during the sleep operation, but applies a voltage higher than the sleep voltage to the gate and the back gate of the PMOS transistor. Thereby, a reverse bias voltage is applied to the body diode of the PMOS transistor, and therefore an increase in leakage current in the PMOS transistor can be avoided.
Drawings
Fig. 1 shows a configuration of a power supply circuit according to an embodiment.
Fig. 2 shows a structure of the main LDO unit according to the embodiment.
Fig. 3 shows a structure of a conventional main LDO unit.
Description of the symbols
PS: power supply circuit
1: main LDO part
TR 1-TR 4: transistor with a metal gate electrode
A1: amplifier with a high-frequency amplifier
SW1, SW 2: switch with a switch body
R1, R2: resistor with a resistor element
Detailed Description
Description of the preferred embodiments
Hereinafter, a power supply circuit according to an embodiment of the present invention will be described.
Structure of the embodiment
Fig. 1 shows a configuration of a power supply circuit according to an embodiment. Hereinafter, a power supply circuit according to an embodiment will be described with reference to fig. 1.
As shown in fig. 1, the power supply circuit PS of the embodiment inputs an external voltage Vex (e.g., 3.3V), and outputs a first internal voltage Vin1 (e.g., 1.7V), a second internal voltage Vin2 (e.g., 1.4V), and a sleep voltage Vsp (e.g., 1.4V). The power supply circuit PS includes a main LDO unit 1, a sub LDO unit 2, a DC/DC converter unit 3, a bias unit 4, and a control unit 5 to output the three voltages. In the power supply circuit PS, the normal operation and the sleep operation are alternately switched in time series in order to reduce power consumption. During the normal operation of the power supply circuit PS, the first internal voltage Vin1 and the second internal voltage Vin2 are output so that the power supply circuit PS and an external circuit (a circuit other than the power supply circuit PS) perform the normal operation. On the other hand, the power supply circuit PS outputs only the sleep voltage Vsp in order to reduce power consumption during the sleep operation.
The main LDO unit 1 has a function of an LDO (low dropout), that is, a function of a linear regulator (linear regulator) that generates an output voltage lower than the input voltage (for example, 1V or less) from the input voltage.
In the normal operation of the main LDO unit 1, in order to function as the LDO, the second internal voltage Vin2 is generated from the first internal voltage Vin1 output from the DC/DC converter unit 3. The main LDO unit 1 outputs the generated second internal voltage Vin2 to the output terminal TM. The main LDO unit 1 generates the second internal voltage Vin2 based on the reference voltage Vref output from the bias unit 4.
On the other hand, during the sleep operation, the main LDO unit 1 does not generate the second internal voltage Vin2, and therefore does not output any voltage to the output terminal TM, as compared with the normal operation.
The main LDO unit 1 is to operate in either a normal operation or a sleep operation, and is determined by a control signal CT output from the control unit 5.
The sub LDO unit 2 has a function of an LDO, that is, a function of a linear regulator that generates an output voltage lower than the input voltage (for example, 1V or less) from the input voltage, as in the main LDO unit 1. The sub LDO unit 2 performs an operation comparable to that of the main LDO unit 1.
The sub LDO unit 2 generates the sleep voltage Vsp from the external voltage Vex during a sleep operation in order to function as the LDO. The sub LDO unit 2 outputs the generated sleep voltage Vsp to the output terminal TM.
On the other hand, the sub LDO unit 2 does not substantially perform any operation during normal operation, that is, it is a hot standby (warmstandby), in other words, it does not output any voltage to the output terminal TM.
The sub LDO unit 2 is to operate in either a normal operation or a sleep operation, and is determined based on a control signal CT output from the control unit 5, as in the main LDO unit 1.
The DC/DC converter section 3 has a function of converting (stepping down) a direct-current voltage into another direct-current voltage. Specifically, the DC/DC converter section 3 generates the first internal voltage Vin1 from the external voltage Vex. The DC/DC converter unit 3 outputs the generated first internal voltage Vin1 to an external circuit (corresponding to a load LD), and also inputs the first internal voltage Vin1 to the main LDO unit 1 via the output to the external circuit.
The bias unit 4 outputs the reference voltage Vref to the main LDO unit 1, so that the main LDO unit 1 can generate the second internal voltage Vin2 from the first internal voltage Vin 1.
The control unit 5 outputs a control signal CT indicating which of the normal operation and the sleep operation should be operated to the main LDO unit 1, the sub LDO unit 2, the DC/DC converter unit 3, and the bias unit 4. Here, the "control signal" does not simply mean a specific signal (for example, a digital signal) such as 1 or 0, high voltage, or low voltage, but means an abstract signal (conceptual signal) indicating which of a normal operation and a sleep voltage should be operated. When the control unit 5 outputs a control signal CT indicating that the operation should be performed in the normal operation, the main LDO unit 1, the DC/DC converter unit 3, and the bias unit 4 operate (the sub LDO unit 2 does not substantially operate). On the other hand, when the control unit 5 outputs the control signal CT indicating that the operation should be performed in the sleep operation, only the sub LDO unit 2 operates.
One or more external circuits (loads LD) are connected to the first internal voltage Vin1 output from the power supply circuit PS having the above-described configuration. In order to stabilize the first internal voltage Vin1, a smoothing capacitor C1 is provided between the input terminal of the first internal voltage Vin1 and the ground in the power supply circuit PS. Further, there may be a capacitance (not shown) generated by a wiring for routing the first internal voltage Vin1 between the external circuit (load LD).
As described above, the output terminal TM of the slave power supply circuit PS outputs the second internal voltage Vin2 output from the master LDO unit 1 during the normal operation, and outputs the sleep voltage Vsp output from the slave LDO unit 2 during the sleep operation. The second internal voltage Vin2 or the sleep voltage Vsp output from the output terminal TM is applied to an external circuit (whether the same as or different from the external circuit). In the output terminal TM, similarly to the function of the smoothing capacitor C1, a smoothing capacitor C2 is provided between the output terminal and the ground in order to stabilize the second internal voltage Vin2 and the sleep voltage Vsp.
Fig. 2 shows a structure of the main LDO according to the embodiment. Hereinafter, the main LDO of the embodiment will be described with reference to fig. 2.
As shown in fig. 2, the main LDO unit 1 includes an amplifier a1, a Transistor TR1 which is a P-channel Metal-Oxide-Semiconductor Field-Effect Transistor (PMOSFET), a Transistor TR2, a Transistor TR3, a Transistor TR4, a switch SW1, a switch SW2, a resistor R1, and a resistor R2.
The amplifier a1 operates with the first internal voltage Vin1 and performs differential amplification. The amplifier a1 includes two input terminals and one output terminal. The reference voltage Vref output from the bias unit 4 is input to one of the input terminals of the amplifier a 1. The other input terminal of the amplifier a1 is inputted (fed back) with a divided voltage Vdiv to be described later in order to ensure a feedback function. The amplifier a1 amplifies a voltage difference between the reference voltage Vref and the divided voltage Ddiv to generate an amplified voltage Vamp, and outputs the amplified voltage Vamp from an output terminal.
The switch SW1 is provided at the rear stage of the amplifier a 1. The switch SW1 has one end connected to the output terminal of the amplifier a1 and the other end connected to the gate of the transistor TR1 and the drain of the transistor TR 2.
The transistor TR1 is provided at the rear stage of the switch SW 1. The transistor TR1 has a source connected to the first internal voltage Vin1, a drain connected to the output terminal TM and one end of the switch SW2, and a back gate connected to the drain of the transistor TR3 and the drain of the transistor TR 4.
The other end of the switch SW2 is connected to one end of the resistor R1.
The resistors R1 and R2 are connected in series to divide the second internal voltage Vin2 output to the output terminal TM. The other end of the resistor R1 is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to the ground potential. The second internal voltage Vin2 is divided by the resistors R1 and R2 connected in series, and the divided voltage Vdiv is defined at the connection point between the resistors R1 and R2.
The transistor TR2 has a gate to which the control signal CT is input and a source connected to the external voltage Vex.
The transistor TR3 has a gate to which the control signal CT is input and a source connected to the first internal voltage Vin 1.
The transistor TR4 has a gate to which the control signal CT is input and a source connected to the external voltage Vex.
Actions of embodiment
The operation of the main LDO according to the embodiment will be described.
Table 1 shows the states of the respective parts of the main LDO according to the embodiment. Hereinafter, the operation of the main LDO according to the embodiment will be described with reference to fig. 2 and table 1.
SW1
SW2
TR3
TR2
TR4
General movement
Is connected to
Is connected to
Is connected to
Disconnect
Disconnect
Sleep movement
Disconnect
Disconnect
Disconnect
Is connected to
Is connected to
TABLE 1
At the time of normal operation
The main LDO unit 1 receives a control signal CT (shown in fig. 1 and 2) from the control unit 5, which indicates that the main LDO unit should operate in a normal operation. In response to the control signal CT, in the main LDO section 1, the transistor TR2 and the transistor TR4 are turned off (blocking state), and on the other hand, the transistor TR3 and the switches SW1 and SW2 are turned on (conducting state).
The transistor TR2 becomes the blocking state, so that the gate of the transistor TR1 is separated from the external voltage Vex, that is, the external voltage Vex is not applied to the gate of the transistor TR 1. On the other hand, the switch SW1 is turned to the on state, so that the gate of the transistor TR1 is connected to the output terminal of the amplifier a1, that is, the amplified voltage Vamp output from the amplifier a1 is applied to the gate of the transistor TR 1.
The pass transistor TR4 becomes the blocking state so that the back gate of the transistor TR1 is separated from the external voltage Vex, i.e., the external voltage Vex is not applied to the back gate of the transistor TR 1. On the other hand, the transistor TR3 becomes the on state, so that the back gate of the transistor TR1 is connected to the first internal voltage Vin1, that is, the first internal voltage Vin1 is applied to the back gate of the transistor TR 1.
When the switch SW2 is turned on, the voltage at the drain of the transistor TR1 is divided by the resistor R1 and the resistor R2, and thus the divided voltage Vdiv is defined at the connection point between the resistor R1 and the resistor R2. The amplifier a1 has a reference voltage Vref input to one input terminal thereof and a divided voltage Vdiv input to the other input terminal thereof. The amplifier a1 amplifies a voltage difference between the reference voltage Vref and the divided voltage Vdiv, thereby outputting an amplified voltage Vamp.
As described above, when the amplified voltage Vamp output from the amplifier a1 is applied to the gate of the transistor TR1, a source/drain current having a magnitude corresponding to the magnitude of the amplified voltage Vamp flows, in other words, the source/drain current increases or decreases according to the fluctuation (magnitude) of the amplified voltage Vamp. By the increase and decrease of the source/drain current, the voltage at the drain of the transistor TR1, that is, the variation of the second internal voltage Vin2 is suppressed. Thus, the second internal voltage Vin2, whose fluctuation is suppressed, i.e., stabilized, is output to the output terminal TM.
During sleep movement
The main LDO unit 1 receives a control signal CT (shown in fig. 1 and 2) from the control unit 5, which indicates that the operation should be performed in the sleep state. In response to the control signal CT, in the main LDO unit 1, the transistor TR2 and the transistor TR4 are turned on (on state), and the transistor TR3 and the switch SW1 and the switch SW2 are turned off (off state), contrary to the sleep operation.
The transistor TR2 becomes the on state, so that the gate of the transistor TR1 is connected to the external voltage Vex, that is, the external voltage Vex is applied to the gate of the transistor TR 1. On the other hand, the switch SW1 is turned to the blocking state, so that the gate of the transistor TR1 is separated from the output terminal of the amplifier a1, that is, the amplified voltage Vamp output from the amplifier a1 is not applied to the gate of the transistor TR 1.
The back gate of the transistor TR1 is connected to the external voltage Vex by the transistor TR4 becoming on, that is, the external voltage Vex is applied to the back gate of the transistor TR 1. On the other hand, the back gate of the transistor TR1 is separated from the first internal voltage Vin1 by the transistor TR3 becoming the blocking state, that is, the first internal voltage Vin1 is not applied to the back gate of the transistor TR 1.
The switch SW2 is turned to the blocking state, so that the voltage at the drain of the transistor TR1 is not divided by the resistors R1 and R2. As a result, the divided voltage Vdiv, which is the ground potential (the potential of the ground connected to the other end of the resistor R2), is input to the other input terminal of the amplifier a 1. Here, as described above, since the switch SW1 is in the blocking state, the magnitude of the divided voltage Vdiv input to the other input terminal does not have any influence on the operation of the transistor TR 1.
Here, referring to the relationship between the output terminal TM and the sub LDO unit 2, as described above, the sub LDO unit 2 outputs the sleep voltage Vsp to the output terminal TM during the sleep operation. Thus, the sleep voltage Vsp is applied to the output terminal TM, in other words, the sleep voltage Vsp is applied to the drain of the transistor TR 1.
The voltage applied to the transistor TR1 in the sleep action is summarized as follows. (1) The first internal voltage Vin1 is applied to the source, (2) the external voltage Vex is applied to the gate and the back gate, and (3) the sleep voltage Vsp is applied to the drain.
Since the external voltage Vex higher than the first internal voltage Vin1 applied to the source is applied to the gate, in other words, a reverse bias for turning off the transistor TR1 (blocking state) is applied between the gate and the source. Thereby, the transistor TR1 becomes a blocking state, that is, the drain becomes open (open) in relation to the source (open end).
Further, the external voltage Vex greater than the sleep voltage Vsp applied to the drain and greater than the first internal voltage Vin1 applied to the source is applied to the back gate, so that the body diode (not shown) of the transistor TR1 becomes an off state (blocking state).
Effects of the embodiment
As described above, in the main LDO according to the embodiment, during the sleep operation, the external voltage Vex larger than the first internal voltage Vin1 and the sleep voltage Vsp is applied to the gate and the back gate of the transistor TR1 having the first internal voltage Vin1 applied to the source and the sleep voltage Vsp applied to the drain. Thereby, the transistor TR1 becomes a blocking state, and the body diode of the transistor TR1 becomes a blocking state. By the body diode in the latter being in the blocking state, unlike the illustration in fig. 3, it is possible to avoid a situation in which the body diode is turned on due to the gradual decrease in the first internal voltage Vin1, thereby causing a leakage current to flow through the transistor TR 1.
(modification)
Instead of using PMOSFETs, the transistors TR1 to TR4 in the main LDO unit 1 of the above embodiment may use N-channel Metal-Oxide-Semiconductor Field-Effect transistors (NMOSFETs). In the case of NMOSFETs, the on state and off state in the normal operation and sleep operation of the transistors TR2 to TR4, the switch SW1, and the switch SW2 are the same as those in the case of PMOSFETs shown in table 1.
On the other hand, in the case of using an NMOSFET, the voltage applied during the sleep operation is different from that of the above embodiment with respect to the transistor TR 1. Specifically, it is necessary to apply a voltage (first voltage) smaller than the sleep voltage Vsp applied to the source to the drain of the transistor TR1 and apply a voltage (second voltage) smaller than the sleep voltage Vsp applied to the source and smaller than the first voltage applied to the drain to the gate and the back gate, on the premise that the high side (high side) drive using the PMOSFET is different from the low side (low side) drive using the NMOSFET in the above embodiment. Thus, as in the case of using a PMOSFET, both the transistor TR1 and the body diode can be turned off.
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