阅读说明：本技术 一种等离激元波导的制备方法 (Preparation method of plasmon waveguide ) 是由 陶金 邱英 刘子晨 肖希 余少华 于 2020-06-28 设计创作，主要内容包括：本申请涉及一种等离激元波导的制备方法,该制备方法包括步骤：在衬底上刻蚀一保护层；在所述保护层上形成刻蚀窗口；在所述刻蚀窗口内采用干法刻蚀工艺刻蚀所述衬底,使所述衬底上形成一沟道；去除所述保护层；在形成有沟道的衬底上镀一层金属基材。本申请提供的等离激元波导的制备方法,不仅使得刻蚀难度较小,而且材质价格不高,成本更低。(The application relates to a preparation method of a plasmon waveguide, which comprises the following steps: etching a protective layer on the substrate; forming an etching window on the protective layer; etching the substrate in the etching window by adopting a dry etching process to form a channel on the substrate; removing the protective layer; and plating a layer of metal base material on the substrate with the channel. The preparation method of the plasmon waveguide not only enables the etching difficulty to be small, but also is low in material price and low in cost.)

1. A method for preparing a plasmonic waveguide, comprising the steps of:

etching a protective layer (2) on the substrate (1);

forming an etching window (3) on the protective layer (2);

etching the substrate (1) in the etching window (3) by adopting a dry etching process to form a channel (4) on the substrate (1);

removing the protective layer (2);

a metal base material (5) is plated on a substrate (1) on which a trench (4) is formed.

2. The method of fabricating a plasmonic waveguide of claim 1, wherein: the substrate (1) sequentially comprises a silicon dioxide layer (12) and a silicon layer (11) from bottom to top.

3. The method of fabricating a plasmonic waveguide of claim 1, wherein: the protective layer (2) is photoresist.

4. The method of fabricating a plasmonic waveguide of claim 3, wherein: the specific step of etching a protective layer (2) on the substrate (1) comprises:

and spin-coating photoresist on the substrate (1) by adopting a semiconductor photoetching process.

5. The method of fabricating a plasmonic waveguide of claim 3, wherein: the specific steps of forming the etching window (3) on the protective layer (2) comprise:

and exposing the protective layer (2), developing by using a developing solution, covering the part, which does not need to be etched, of the substrate (1) by using a photoresist, and dissolving the photoresist in the part, which needs to be etched, of the substrate (1) to form an etching window (3).

6. The method for preparing a plasmonic waveguide of claim 3, wherein the specific step of removing the protective layer (2) comprises:

and removing the protective layer (2) by adopting a wet etching process.

7. The method of fabricating a plasmonic waveguide of claim 1, wherein the width of the channel (4) is 10nm to 500 nm.

8. The method for preparing a plasmonic waveguide according to claim 1, wherein the step of plating a metal base material on the substrate (1) on which the channel is formed comprises:

and placing the substrate (1) with the channel (4) in an electron beam evaporation furnace or an electromagnetic sputtering furnace to plate metal base materials.

9. The method of manufacturing a plasmonic waveguide according to claim 8, wherein after the substrate (1) formed with the channel (4) is placed in an electron beam evaporation furnace or an electromagnetic sputtering furnace, further comprising the steps of:

and controlling the conditions of an electron beam evaporation furnace or an electromagnetic sputtering furnace, and plating a metal substrate on the bottom surface of the channel (4).

10. The method of manufacturing a plasmonic waveguide according to claim 8, wherein after the substrate (1) formed with the channel (4) is placed in an electron beam evaporation furnace or an electromagnetic sputtering furnace, further comprising the steps of:

and controlling the conditions of an electron beam evaporation furnace or an electromagnetic sputtering furnace, and plating metal base materials on the bottom surface and the side wall of the channel (4).

Technical Field

The application relates to the technical field of integrated optical waveguides, in particular to a preparation method of a plasmon waveguide.

Background

Semiconductor electronic devices currently enable nanoelectronic components for information storage and computation, but are limited in speed to around 10GHz due to thermal effects and inline time delays. Dielectric photonics, such as silicon-based waveguides, optical fibers, etc., can provide extremely large bandwidths, limited by diffraction limits so that their dimensions are on the order of a wavelength.

The surface plasmon waves are surface waves formed by collective oscillation formed by photons and electrons in the metal material, and can control the optical waves in a sub-wavelength scale. The plasmon is adopted as an information carrier, so that the limit of diffraction limit can be broken through, the sizes of an optical loop and an element are reduced to the nanometer level, and the perfect combination of photons and electrons on the nanometer level can be realized. The generation of plasmon waves and the realization of the low-loss negative dielectric constant of the plasmon optical device generally adopt noble metals such as gold, silver and the like, and the imaginary part of the refractive index of the noble metals is smaller than the absolute value of the real part.

In practical applications, the plasmonic optical device needs to be compatible with industry standard manufacturing processes, such as CMOS (complementary metal-oxide-semiconductor) process, which is suitable for mass production of low-cost plasmonic devices and electronic components integrated therewith. Copper is the most widely used metal in modern microelectronics, and the plasma oscillation frequency of the copper is very close to that of gold, so that the copper can be used as a material for preparing a plasmon device on a large scale.

Disclosure of Invention

The embodiment of the application provides a preparation method of a plasmon waveguide, and aims to solve the technical problems of high etching difficulty and high cost in the related technology.

The application provides a preparation method of a plasmon waveguide, which comprises the following steps:

etching a protective layer on the substrate;

forming an etching window on the protective layer;

etching the substrate in the etching window by adopting a dry etching process to form a channel on the substrate;

removing the protective layer;

and plating a layer of metal base material on the substrate with the channel.

In some embodiments, the substrate comprises, in order from bottom to top, a silicon dioxide layer and a silicon layer.

In some embodiments, the protective layer is a photoresist.

In some embodiments, the step of etching a protective layer on the substrate comprises:

and spin-coating a photoresist on the substrate by adopting a semiconductor photoetching process.

In some embodiments, the step of forming the etching window on the protection layer includes:

and exposing the protective layer, developing by using a developing solution, covering the part which does not need to be etched on the substrate by using a photoresist, and dissolving the photoresist on the part which needs to be etched on the substrate to form an etching window.

In some embodiments, the specific step of removing the protective layer comprises:

and removing the protective layer by adopting a wet etching process.

In some embodiments, the width of the channel is 10nm to 500 nm.

In some embodiments, the step of plating a metal base material on the substrate with the channel comprises:

and placing the substrate with the channel in an electron beam evaporation furnace or an electromagnetic sputtering furnace to plate metal base materials.

In some embodiments, after the substrate with the trench is placed in an electron beam evaporation furnace or an electromagnetic sputtering furnace, the method further comprises the steps of:

and controlling the conditions of an electron beam evaporation furnace or an electromagnetic sputtering furnace, and plating a metal substrate on the bottom surface of the channel.

In some embodiments, after the substrate with the trench is placed in an electron beam evaporation furnace or an electromagnetic sputtering furnace, the method further comprises the steps of:

and controlling the conditions of an electron beam evaporation furnace or an electromagnetic sputtering furnace, and plating metal base materials on the bottom surface and the side wall of the channel.

The beneficial effect that technical scheme that this application provided brought includes: not only the etching difficulty is small, but also the material price is not high, and the cost is lower.

The embodiment of the application provides a preparation method of a plasmon waveguide, in order to form the plasmon waveguide, a layer of channel is etched in a dry method firstly, and then a metal substrate is plated on the channel, so that the thickness of a required metal layer is smaller, for example, if the channel is etched after the metal substrate is plated, the thickness of the required channel is N, the thickness of the required metal layer is at least N, in the preparation method of the plasmon waveguide, the channel with the thickness of N is formed on a substrate, then the metal substrate is plated, only a very thin layer of copper needs to be arranged to meet the requirement, the etching difficulty is smaller, the material price is not high, and the cost is lower.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a flowchart of a method for manufacturing a plasmonic waveguide according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of step S1 in the embodiment of the present application;

FIG. 3 is a schematic diagram of step S2 in the embodiment of the present application;

FIG. 4 is a schematic diagram of step S3 in the embodiment of the present application;

FIG. 5 is a schematic diagram of step S4 in the embodiment of the present application;

FIG. 6 is a schematic diagram of a channel plasmon waveguide in step S5 according to an embodiment of the present application;

FIG. 7 is a schematic view of a strip plasmon waveguide in an embodiment of the present application;

fig. 8 is a detailed flowchart of a method for manufacturing a plasmonic waveguide according to an embodiment of the present application.

In the figure: 1. a substrate; 11. a silicon layer; 12. a silicon dioxide layer; 2. a protective layer; 3. etching a window; 4. a channel; 5. a metal substrate.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Referring to fig. 1, an embodiment of the present application provides a method for manufacturing a plasmonic waveguide, which includes the steps of:

s1: etching a protective layer 2 on the substrate 1, as shown in fig. 2;

s2: forming an etching window 3 on the protective layer 2, as shown in fig. 3;

s3: etching the substrate 1 in the etching window 3 by adopting a dry etching process to form a channel 4 on the substrate 1, as shown in fig. 4;

s4: removing the protective layer 2, as shown in fig. 5;

s5: a metal base material 5 is plated on the substrate 1 where the trenches 4 are formed, as shown in fig. 6.

In the preparation method of the plasmon waveguide, in order to form the plasmon waveguide, a layer of channel is etched by a dry method, and then the metal substrate is plated on the channel, so that the thickness of a required metal layer is smaller, for example, if the channel is etched after the metal substrate is plated, and the thickness of the required channel is N, the thickness of the required metal layer is at least N.

Preferably, in the embodiment of the present application, the metal substrate is copper, which is not expensive, and is compatible with CMOS process, which can reduce the cost.

Further, in the present embodiment, the substrate 1 includes a silicon dioxide layer 12 and a silicon layer 11 in this order from bottom to top. And, the thickness of the silicon dioxide layer 12 is 2 microns, the thickness of the silicon layer 11 is 220nm, and the silicon on insulator SOI which is mature in industry and used in large quantity is adopted as a substrate, so that the cost is lower.

In other embodiments, the substrate may be other media, and may be selected according to actual requirements.

Specifically, in the embodiment of the present application, the protective layer 2 is a photoresist. When the method is used, different photoresists and photolithographic processes are selected according to different resolution and material etching requirements.

Further, in the embodiment of the present application, the specific step of etching a protection layer 2 on a substrate 1 includes:

and spin-coating a photoresist on the substrate 1 by adopting a semiconductor photoetching process.

Further, in the embodiment of the present application, the specific step of forming the etching window 3 on the protection layer 2 includes:

and exposing the protective layer 2, developing by using a developing solution, covering the part which does not need to be etched on the substrate 1 by using a photoresist, and dissolving the photoresist on the part which needs to be etched on the substrate 1 to form an etching window 3.

Further, in the embodiment of the present application, the specific step of removing the protective layer 2 includes:

and removing the protective layer 2 by adopting a wet etching process.

The specific process of the wet etching process used in the present application is: the protective layer 3 was removed clean with acetone and the surface was allowed to dry completely.

Referring to fig. 6, preferably, in the embodiment of the present application, the width of the channel 4 is denoted as w, and the width of the channel 4 is 100nm to 300nm, that is, the value of w ranges from 100nm to 300 nm.

Further, in the embodiment of the present application, the step of plating a metal base material on the substrate 1 formed with the trench includes:

the substrate 1 formed with the trenches 4 is placed in an electron beam evaporation furnace or an electromagnetic sputtering furnace to be metallized with a base material.

Further, in one embodiment, after the substrate 1 formed with the trench 4 is placed in an electron beam evaporation furnace or an electromagnetic sputtering furnace, the method further includes the steps of:

and controlling the conditions of an electron beam evaporation furnace or an electromagnetic sputtering furnace, plating a metal substrate on the bottom surface of the channel 4, and forming a channel plasma waveguide as shown in figure 6.

Further, in another embodiment, after the substrate 1 formed with the trench 4 is placed in an electron beam evaporation furnace or an electromagnetic sputtering furnace, the method further includes the steps of:

controlling the conditions of an electron beam evaporation furnace or an electromagnetic sputtering furnace, plating a metal substrate on the bottom surface and the side wall of the channel 4, and forming the strip-shaped plasma waveguide, as shown in figure 7.

In practical applications, if a trench plasmon waveguide is required, a metal substrate is plated on the bottom surface of the trench 4, and if a strip plasmon waveguide is required, a metal substrate is plated on the bottom surface and the side wall of the trench 4.

Referring to fig. 8, an embodiment of the present application further provides a detailed flowchart of a method for manufacturing a plasmonic waveguide, which is based on a copper substrate and includes the steps of:

a1: taking an SOI wafer as a substrate 1, wherein the substrate 1 sequentially comprises a silicon dioxide layer 12 and a silicon layer 11 from bottom to top;

a2: spin-coating a photoresist on the substrate 1 by adopting a semiconductor photoetching process, wherein the photoresist is a protective layer 2;

a3: exposing the photoresist, developing by using a developing solution, covering the part which does not need to be etched on the substrate 1 by using the photoresist, and dissolving the photoresist on the part which needs to be etched on the substrate 1 to form an etching window 3;

a4: etching the substrate 1 in the etching window 3 by adopting a dry etching process to form a channel 4 on the substrate 1, wherein the etching depth and time are determined according to the designed depth of the copper-based plasmon waveguide;

a5: removing the residual photoresist cleanly by using acetone, and completely drying the surface of the photoresist;

a6: a substrate 1 with a channel 4 is plated with a layer of metal base material 5, wherein the metal base material 5 is copper, and further a copper-based surface plasmon waveguide is formed.

The copper-based surface plasmon waveguide formed in the embodiment of the application is based on the copper-based surface plasmon waveguide, the one-layer channel is etched by a dry method firstly, and then copper is plated on the channel, so that the thickness of a required metal layer is smaller, for example, if the channel is etched by copper plating firstly and then the thickness of the required channel is N, the thickness of the required metal layer is at least N, the copper-based surface plasmon waveguide formed in the embodiment of the application is based on the copper-based surface plasmon waveguide, the channel with the thickness of N is formed on the substrate, copper plating is performed again, the requirement can be met only by setting a very thin layer of copper, the etching difficulty is smaller, the price of the copper material.

In the description of the present application, it should be noted that the terms "upper", "lower", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, which are only for convenience in describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and operate, and thus, should not be construed as limiting the present application. Unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are intended to be inclusive and mean, for example, that they may be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

It is noted that, in the present application, relational terms such as "first" and "second", and the like, are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The above description is merely exemplary of the present application and is presented to enable those skilled in the art to understand and practice the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.