阅读说明：本技术 逆变器及电子设备 (Inverter and electronic device ) 是由 李迎 李勇 于 2020-05-29 设计创作，主要内容包括：本申请提供一种逆变器及电子设备,涉及逆变器领域,能够解决并联的IGBT的动态均流不平衡的问题。该逆变器包括母线电容,母线电容包括电容芯包以及位于电容芯包侧面并列设置的至少一相正极输出母排和负极输出母排；在至少一相输出母排的正极输出母排和负极输出母排之间并联设置有至少两个IGBT,至少两个IGBT中包括第一IGBT、第二IGBT；第一IGBT与正极输出母排、负极输出母排的连接位置分别比第二IGBT与正极输出母排、负极输出母排的连接位置更接近电容芯包；第一IGBT与输出母排的连接方式与第二IGBT与输出母排的连接方式存在不同；第一IGBT与输出母排的连接阻抗(R1、R2)之和大于第二IGBT与输出母排的连接阻抗(R3、R4)之和,即R1+R2＞R3+R4。(The application provides an inverter and electronic equipment, relates to the inverter field, can solve the unbalanced problem of parallelly connected IGBT's dynamic current sharing. The inverter comprises a bus capacitor, wherein the bus capacitor comprises a capacitor core package and at least one phase of positive output busbar and negative output busbar which are arranged on the side surface of the capacitor core package in parallel; at least two IGBTs are arranged in parallel between the positive output busbar and the negative output busbar of at least one phase of output busbar, and the at least two IGBTs comprise a first IGBT and a second IGBT; the connection positions of the first IGBT and the positive output busbar and the negative output busbar are respectively closer to the capacitor core package than the connection positions of the second IGBT and the positive output busbar and the negative output busbar; the connection mode of the first IGBT and the output bus bar is different from that of the second IGBT and the output bus bar; the sum of the connecting impedances (R1 and R2) of the first IGBT and the output bus bar is larger than the sum of the connecting impedances (R3 and R4) of the second IGBT and the output bus bar, namely R1+ R2 > R3+ R4.)

1. The inverter is characterized by comprising a bus capacitor, wherein the bus capacitor comprises a capacitor core package and at least one phase output bus bar which is positioned on the side surface of the capacitor core package and arranged in parallel;

each phase of the output bus bar comprises a positive output bus bar and a negative output bus bar;

at least two IGBTs are arranged in parallel between the positive output busbar and the negative output busbar of at least one phase of the output busbar, and the at least two IGBTs comprise a first IGBT and a second IGBT;

the connecting position of the first IGBT and the positive output bus bar is closer to the capacitor core package than the connecting position of the second IGBT and the positive output bus bar;

the connecting position of the first IGBT and the negative output bus bar is closer to the capacitor core package than the connecting position of the second IGBT and the negative output bus bar;

the connection mode of the first IGBT and the positive output busbar and the connection mode of the negative output busbar are different from the connection mode of the second IGBT and the positive output busbar and the connection mode of the second IGBT and the negative output busbar;

the connection impedance between the first IGBT and the positive electrode output busbar is R1, the connection impedance between the first IGBT and the negative electrode output busbar is R2, the connection impedance between the second IGBT and the positive electrode output busbar is R3, the connection impedance between the second IGBT and the negative electrode output busbar is R4, and the requirements that R1+ R2 is more than R3+ R4 are met.

2. The inverter of claim 1,

the distances from the connecting positions of the first IGBT and the positive output busbar and the negative output busbar to the capacitor core package are equal, and the first IGBT and the positive output busbar and the negative output busbar are connected in a first connecting mode;

the distances from the connecting positions of the second IGBT and the positive output busbar and the negative output busbar to the capacitor core package are equal, and the second IGBT and the positive output busbar and the negative output busbar are connected in a second connecting mode;

the first connection mode is different from the second connection mode, and the connection impedance of the first connection mode is larger than that of the second connection mode.

3. The inverter according to claim 2, wherein the first connection means is a bolt connection and the second connection means is a welding connection.

4. The inverter according to claim 2, wherein the first connection method is non-full-welding, and the second connection method is full-welding.

5. The inverter according to claim 3 or 4, wherein the welding is laser welding.

6. The inverter according to claim 2, wherein the first connection means is a first bolt connection, and the second connection means is a second bolt connection;

at least one of the connection contact area, the screw diameter and the screw length of the first bolt connection and the second bolt connection are different.

7. The inverter according to any one of claims 1 to 6, wherein two IGBTs are arranged in parallel between a positive output busbar and a negative output busbar of each phase of the output busbar.

8. The inverter according to any one of claims 1 to 7, wherein the inverter comprises a three-phase output busbar.

9. The inverter according to claim 8, wherein the plurality of IGBTs connected in parallel between the positive output busbar and the negative output busbar in each phase output busbar are arranged in the same manner.

10. An electronic device, characterized by comprising an inverter according to any one of claims 1 to 9.

Technical Field

The present application relates to the field of inverters, and in particular, to an inverter and an electronic device.

Background

An inverter is a converter that converts direct current electric energy into constant frequency, constant voltage or frequency and voltage regulation alternating current, and is widely applied to equipment in various fields (such as vehicles, mobile phones and the like). Among them, an Insulated Gate Bipolar Transistor (IGBT) is a mainstream switching device used in an inverter, and also plays a core role in the inverter.

The inverter adopted by the high-power equipment needs to achieve a specific current value through the parallel IGBT so as to enable the inverter to complete high-power output; however, the parallel IGBTs have different routing distances from the capacitor core package of the bus capacitor in the inverter, which results in different equivalent inductances from the parallel IGBTs to the capacitor core package, and further causes the problem of unbalanced dynamic current equalization of the parallel IGBTs, and easily causes the disadvantage of unstable output of the inverter.

Disclosure of Invention

The application provides an inverter and electronic equipment, which can solve the problem of unbalanced dynamic current sharing of parallel IGBTs.

The application provides an inverter, which comprises a bus capacitor, wherein the bus capacitor comprises a capacitor core package and at least one phase output bus bar which is positioned on the side surface of the capacitor core package and arranged in parallel; each phase of output bus bar comprises a positive output bus bar and a negative output bus bar; in order to meet the requirement of high-power equipment, the inverter further comprises: at least two IGBTs are arranged in parallel between the positive output busbar and the negative output busbar of at least one phase of output busbar; the at least two IGBTs comprise a first IGBT and a second IGBT; the connecting position of the first IGBT and the positive output bus bar is closer to a capacitor core package than the connecting position of the second IGBT and the positive output bus bar; meanwhile, the connection position of the first IGBT and the negative output busbar is closer to the capacitor core package than the connection position of the second IGBT and the negative output busbar. On the basis, the equivalent inductance of the first IGBT, the second IGBT and the output bus bar at the connecting position is adjusted in the inverter by setting the connection mode of the first IGBT and the positive output bus bar and the negative output bus bar to be different from the connection mode of the second IGBT and the positive output bus bar and the negative output bus bar; specifically, by setting the connection impedance of the first IGBT and the positive output busbar at the connection position to R1, the connection impedance of the first IGBT and the negative output busbar at the connection position to R2, the connection impedance of the second IGBT and the positive output busbar at the connection position to R3, the connection impedance of the second IGBT and the negative output busbar at the connection position to R4, and at the same time, R1, R2, R3, and R4 satisfy the following relational expression: r1+ R2 > R3+ R4; that is, the total connection impedance (R1, R2) of the first IGBT and the positive output busbar and the negative output busbar at the connection position is larger than the total connection impedance (R3, R4) of the second IGBT and the positive output busbar and the negative output busbar at the connection position, so that the difference of equivalent inductance caused by different distances from the connection position to the capacitor core package is reduced, and the problem of unbalanced dynamic current sharing of the first IGBT and the second IGBT is solved.

In summary, in the inverter of the present application, at least two parallel IGBTs are different from the positive output busbar and the negative output busbar in connection manner, so that the total connection impedance between the IGBT and the output busbar at a small distance from the connection position to the capacitor core package is greater than the total connection impedance between the IGBT and the output busbar at a large distance from the connection position to the capacitor core package, thereby reducing the difference between the equivalent inductance of the at least two parallel IGBTs to the capacitor core package, and further ensuring the dynamic current-sharing balance of the parallel IGBTs.

In some possible implementation manners, the distances from the connection positions of the first IGBT and the positive output busbar and the negative output busbar to the capacitor core package are equal, and the first IGBT and the positive output busbar and the negative output busbar are connected in a first connection manner; the distances from the connecting positions of the second IGBT and the positive output busbar and the negative output busbar to the capacitor core package are equal, and the second IGBT and the positive output busbar and the negative output busbar are connected in a second connecting mode; the first connection mode is different from the second connection mode, and the connection impedance of the first connection mode is larger than that of the second connection mode; so as to simplify and adjust the equivalent inductance from the two IGBTs to the capacitor core package and simplify the manufacturing process of the inverter.

In some possible implementations, the first connection is a bolt connection, and the second connection is a welding connection.

In some possible implementations, the first connection mode is a non-full-welding type welding mode, and the second connection mode is a full-welding type welding mode.

In some possible implementations, the welding is laser welding.

In some possible implementation manners, the first connection manner adopts a first bolt connection, and the second connection manner adopts a second bolt connection; at least one of the connection contact area, the screw diameter and the screw length of the first bolt connection and the second bolt connection are different.

In some possible implementation manners, two IGBTs are arranged in parallel between the positive output busbar and the negative output busbar of each phase of the output busbar.

In some possible implementations, the inverter includes a three-phase output bus bar.

In some possible implementation manners, the plurality of IGBTs connected in parallel between the positive output busbar and the negative output busbar in each phase output busbar are arranged in the same manner, so as to ensure that the current values output by the IGBTs connected in parallel between each phase output busbar are the same.

Embodiments of the present application also provide an electronic device, including an inverter as provided in any one of the foregoing possible implementation manners.

Drawings

Fig. 1 is a schematic circuit diagram of an inverter according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of a bus capacitor according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a bus capacitor according to an embodiment of the present application.

Detailed Description

To make the purpose, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be fully described below with reference to the accompanying drawings in the present application, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms "first," "second," and the like in the description examples and claims of this application and in the drawings are used for descriptive purposes only and are not to be construed as indicating or implying relative importance, nor order. Furthermore, the terms "comprises" and "comprising," as well as any variations thereof, are intended to cover a non-exclusive inclusion, such as a list of steps or elements. The article or apparatus is not necessarily limited to those steps or elements explicitly listed, but may include other steps or elements not explicitly listed or inherent to such article or apparatus.

The embodiment of the application provides an electronic device, and the electronic device comprises an inverter. The electronic equipment can be electronic products such as vehicle-mounted equipment, a tablet personal computer and a mobile phone, and the embodiment of the application does not specially limit the specific form of the electronic equipment.

In the electronic equipment, the inverter adopts the parallel IGBT, and the parallel IGBT and the bus capacitor are not completely connected in the same way, so that the problem of unbalanced dynamic current equalization of the parallel IGBT is solved.

The inverter provided in the embodiments of the present application will be further described below.

First, referring to the equivalent circuit schematic diagram of the inverter shown in fig. 1, in the inverter, a first IGBT 10 and a second IGBT20 are arranged in parallel between two bus bars of a bus bar capacitor C to ensure that an output terminal OUT1 reaches a specific current value to meet the output requirement of the inverter.

It should be noted that fig. 1 only illustrates that the inverter includes three phases (or three groups) of IGBTs arranged in parallel, and each IGBT arranged in parallel includes two IGBTs (10, 20), but the present application is not limited thereto; for example, in some possible implementations, two parallel IGBTs may also be provided in the inverter, and each parallel IGBT includes three IGBTs or two IGBTs.

As will be understood by those skilled in the art, it is essential for the first IGBT 10 and the second IGBT20 to be arranged in parallel to ensure that the first IGBT 10 and the second IGBT20 are dynamically current-sharing.

In an actual structure of the inverter, as shown in fig. 2, a bus capacitor includes a capacitor core package 100 and at least one group of output busbars T (which may also be referred to as a one-phase output busbar T; including a positive output busbar 1 and a negative output busbar 2) arranged in parallel on side surfaces of the capacitor core package 100, and a first IGBT 10 and a second IGBT20 arranged in parallel are connected between the positive output busbar 1 and the negative output busbar 2 of the group of output busbars T. However, since the first IGBT 10 and the second IGBT20 are connected to different positions of the group of output busbars T of the bus capacitor, for example, one IGBT is closer to the capacitor core package 100 of the bus capacitor C than the other IGBT is connected to the group of output busbars; in this case, the equivalent inductances (ESLs) from the two IGBTs (10, 20) to the capacitor core package 100 have a difference, which causes a problem of dynamic current sharing imbalance of the two IGBTs (10, 20).

In order to solve the problem that the dynamic current sharing is unbalanced due to different equivalent inductances from the parallel-arranged IGBTs to the capacitor core package 100, in the inverter provided in the embodiment of the present application, the difference between the parallel-arranged IGBTs and the equivalent inductance from the capacitor core package 100 is reduced by adjusting that the connection positions of the parallel-arranged IGBTs and the positive output busbar 1 and the negative output busbar 2 are not completely the same, so as to ensure the dynamic current sharing of the parallel-arranged IGBTs.

The connection mode between the parallel IGBT and the positive output bus bar 1 and the negative output bus bar 2 will be further described below.

Referring to fig. 2, in the first IGBT 10 and the second IGBT20 arranged in parallel, the first IGBT 10 is connected between a connection position a1 of the positive output bus bar 1 and a connection position b1 of the negative output bus bar 2, and the second IGBT20 is connected between a connection position a2 of the positive output bus bar 1 and a connection position b2 of the negative output bus bar 2. The connection position a1 of the first IGBT 10 and the positive output busbar 1 is closer to the capacitor core package 100 than the connection position a2 of the second IGBT20 and the positive output busbar 1; that is, the distance s1 from the connection position a1 to the capacitor core package 100 is smaller than the distance s2 from the connection position a2 to the capacitor core package 100. Similarly, the connection position b1 of the first IGBT 10 and the negative output bus bar 2 is closer to the capacitor core package 100 than the connection position b2 of the second IGBT20 and the negative output bus bar 2; i.e. the distance from the connection position b1 to the capacitive core package 100 is smaller than the distance from the connection position b 2. That is to say, the routing distance from the first IGBT 10 to the capacitor core package 100 is less than the routing distance from the second IGBT20 to the capacitor core package 100, and in this case, the equivalent inductance of the routing portion from the first IGBT 10 to the capacitor core package 100 is less than the equivalent inductance of the routing portion from the second IGBT20 to the capacitor core package 100.

On this basis, there is the difference through setting up first IGBT 10 and second IGBT20 and female 1, the female 2 connected mode of arranging of anodal output in this application, adjusts first IGBT 10 and second IGBT20 and the female 1 of anodal output, female 2 connected impedance of arranging of negative pole output is different in the hookup location department to adjust first IGBT 10 and second IGBT20 to the equivalent inductance of electric capacity core package 100.

Specifically, the connection impedance of the connection mode adopted at the connection position a1 of the first IGBT 10 and the positive output bus bar 1 may be set to be R1, and the connection impedance of the connection mode adopted at the connection position b1 of the first IGBT 10 and the negative output bus bar 2 may be set to be R2; the connection impedance of the connection mode adopted at the connection position a2 of the second IGBT20 and the positive output bus bar 1 is R3, and the connection impedance of the connection mode adopted at the connection position b2 of the second IGBT20 and the negative output bus bar 2 is R4. Wherein, the sizes of R1, R2, R3 and R4 satisfy R1+ R2 > R3+ R4; that is, the total connection impedance (R1+ R2) of the first IGBT 10 and the output bus bar T at the two connection positions is greater than the total connection impedance (R3+ R4) of the second IGBT20 and the output bus bar T at the two connection positions; therefore, the difference between the equivalent inductance of the first IGBT 10 and the equivalent inductance of the second IGBT20 which are arranged in parallel and the equivalent inductance of the capacitor core package 100 are reduced, and the purpose of dynamic current sharing is achieved.

Here, it should be noted that, in the present application, the number of the IGBTs arranged in parallel is not particularly limited. For example, two parallel IGBTs (see fig. 2) may be provided, or three parallel IGBTs (see fig. 3) may be provided. In addition, the "bus bar" referred to in the present application may also be referred to as a "bus bar copper bar".

Note that the first IGBT 10 and the second IGBT20 arranged in parallel as described above do not necessarily refer to any two specific IGBTs, and it should be understood that any two IGBTs satisfying the above conditions among a plurality of IGBTs arranged in parallel may be regarded as the first IGBT 10 and the second IGBT 20.

For example, in the case that the IGBTs arranged in parallel include three IGBTs, referring to fig. 3, the connection positions (a1, b1) of one IGBT and the positive output busbar 1 and the negative output busbar 2 are closest to the capacitor core package 100, the connection positions (a3, b3) of one IGBT and the positive output busbar 1 and the negative output busbar 2 are farthest from the capacitor core package 100, and the connection positions (a2, b2) of one IGBT and the positive output busbar 1 and the negative output busbar 2 are located in the middle of the capacitor core package 100; that is, the a1 connection position, the a2 connection position, and the a3 connection position on the positive output bus bar 1 are sequentially arranged along the direction away from the capacitor core package 100, and the b1 connection position, the b2 connection position, and the b3 connection position on the negative output bus bar 2 are sequentially arranged along the direction away from the capacitor core package 100. In this case, as illustrated in fig. 3, the IGBT connected between the a1 connection position and the b1 connection position may be the first IGBT 10, and the IGBT connected between the a3 connection position and the b3 connection position may be the second IGBT 20; alternatively, the IGBT connected between the a2 connection position and the b2 connection position may be the first IGBT 10, and the IGBT connected between the a3 connection position and the b3 connection position may be the second IGBT20 (not illustrated in fig. 3). That is, of any two IGBTs among the three IGBTs arranged in parallel, the IGBT whose connection position is a small distance from the capacitor core package 100 is the first IGBT 10, and the IGBT whose connection position is a large distance from the capacitor core package 100 is the second IGBT 20.

In summary, in the inverter of the present application, there are differences in the connection manner between the at least two parallel IGBTs and the positive output busbar and the negative output busbar through setting up, so that the total connection impedance of the IGBT and the output busbar at the connection position where the connection position is short of the capacitor core package distance is greater than the total connection impedance of the IGBT and the output busbar at the connection position where the connection position is long of the capacitor core package distance, thereby reducing the difference between the equivalent inductance of the capacitor core package and the at least two parallel IGBTs, and further ensuring the dynamic current-sharing balance of the parallel IGBTs.

Referring to fig. 2, for reducing the difference between the equivalent inductances of the first IGBT 10 and the second IGBT20 and the capacitor core package 100 by adjusting the connection manners of the first IGBT 10 and the second IGBT20 and the positive output busbar 1 and the negative output busbar 2, the connection manner of the first IGBT 10 and the second IGBT20 and at least one of the four connection positions (a1, b1, a2, and b2) of the positive output busbar 1 and the negative output busbar 2 may be adjusted to be different from the connection manners of the other positions, so as to achieve the purpose of achieving dynamic current sharing when the equivalent inductances of the first IGBT 10 and the second IGBT20 and the capacitor core package 100 are the same.

For example, in some possible implementations, a connection with a larger connection impedance at the b1 connection location may be provided, with the same connection with a smaller connection impedance at the a1, a2, b2 connection locations.

For another example, in some possible implementations, a connection with a smaller connection impedance at the b2 connection location may be provided, with the same connection with a larger connection impedance at the a1, a2, b1 connection locations.

As another example, in some possible implementations, a connection with a larger connection impedance at the a1, b1 connection location may be provided, with the same connection with a smaller connection impedance at the a2, b2 connection location.

In the embodiment of the present application, the specific connection manner adopted by the two IGBTs (10, 20) at the four connection positions (a1, b1, a2, b2) is not particularly limited, as long as the equivalent inductance from the two IGBTs (10, 20) to the capacitor core package 100 can be adjusted by selecting a suitable connection manner, so as to achieve the purpose of dynamic current sharing of the two IGBTs (10, 20).

Of course, in some possible implementation manners, the distances from the four connection positions (a1, b1, a2, b2) to the capacitor core package 100 may also be adjusted on the basis that the specific connection manners of the four connection positions (a1, b1, a2, b2) are not completely the same. Namely, the equivalent inductance from the two IGBTs (10, 20) to the capacitor core package 100 is adjusted by combining the connection impedance of the two IGBTs (10, 20) at the connection position and the distance from the connection position to the capacitor core package 100 (i.e., the equivalent inductance of the trace portion), so that the two IGBTs (10, 20) reach dynamic current sharing balance.

In practice, in order to adjust the equivalent inductance from the two IGBTs (10, 20) to the capacitor core package 100, as shown in fig. 2, the distances from the connection positions (a1, b1) of the first IGBT 10 and the output bus bars (1, 2) to the capacitor core package 100 may be set to be equal, and the distances from the connection positions (a2, b2) of the second IGBT20 and the output bus bars (1, 2) to the capacitor core package 100 are set to be equal; that is to say, among the plurality of IGBTs arranged in parallel, the distances from the connection positions of the single IGBT and the positive output busbar 1 and the negative output busbar 2 to the capacitor core package 100 are equal.

On this basis, in order to simplify the manufacturing process of the inverter, the first IGBT 10 may be connected to the positive output busbar 1 and the negative output busbar 2 in the same connection manner (hereinafter, simply referred to as the first connection manner); the second IGBT20 is connected with the positive output busbar 1 and the negative output busbar 2 in the same connection mode (hereinafter referred to as the second connection mode); the first connection mode and the second connection mode are different in arrangement mode, and the connection impedance of the second connection mode is smaller than that of the first connection mode. The following examples are given as examples and will further illustrate the present application in connection with specific connection schemes.

Illustratively, in some possible implementation manners, the first connection manner and the second connection manner may adopt connection manners with high implementability, low cost and simple process; for example, connection means including, but not limited to, bolting, welding, etc. may be employed; therefore, the purpose of dynamic current sharing balance of the first IGBT 10 and the second IGBT20 is achieved on the basis of not increasing the cost of the inverter.

For example, in some possible implementations, the first connection manner may be a bolt connection manner, and the second connection manner may be a welding manner. That is, the first IGBT 10 is connected to the positive output busbar 1 and the negative output busbar 2 at the connection positions (a1 and b1) by bolts with relatively high connection impedance, and the second IGBT20 is connected to the positive output busbar 1 and the negative output busbar 2 at the connection positions (a2 and b2) by welding with relatively low connection impedance.

It can be understood that, for the bolt connection, the IGBT and the positive output busbar 1 and the negative output busbar 2 need to be provided with a connection hole at the connection position, and the connection hole is inserted with a screw and fastened by a nut. In practice, the connection impedance of the IGBT and the output busbar (1, 2) at the connection position can be adjusted by setting different connection contact areas of bolt connection, screw rod diameters of screws, screw rod lengths of screws, hole diameters of connection holes and the like. Of course, in the bolt connection, the diameters of two connection holes (one is located on the terminal of the IGBT and the other is located on the output busbar) at the same connection position may be the same or different; the screw diameters and the screw lengths of the screws adopted in different bolt connections can be the same or different; in practice, on the basis of ensuring the normal connection of the IGBT and the output busbar, the connection contact area, the screw diameter, the screw length, the size of the connection hole, and the like can be set according to the required connection impedance, so as to achieve the purpose of adjusting the connection impedance at the connection position, and further achieve the dynamic current-sharing balance of the first IGBT 10 and the second IGBT 20.

In addition, as for the welding, a laser welding method is generally adopted (but not limited thereto), and the IGBT and the positive output busbar 1 and the negative output busbar 2 are directly welded at the connection position by solder. In practice, the connection impedance of the IGBT and the output bus bars (1, 2) at the connection position can be adjusted by setting the welding degree of the IGBT and the output bus bars (1, 2) at the connection position; for example, full-weld or non-full-weld welding may be selected; of course, for the non-full-welding type welding, the welding degree of the non-full-welding type can be further adjusted according to actual requirements. It can be understood that, for welding per se, a connecting hole is not required to be arranged between the IGBT and the output busbar (1, 2), and welding can be directly carried out at the corresponding connecting position. In addition, it is also understood that full-soldering refers to soldering two devices (components) to be soldered entirely with solder in the designed soldering area, and non-full-soldering refers to soldering two devices (components) to be soldered locally with solder in the designed soldering area.

In addition, for the first connection mode, a bolt connection mode can be adopted, and for the second connection mode, welding is adopted, so that the connection impedance of the bolt connection adopted by the first connection mode is larger than that of welding adopted by the second connection mode, and the equivalent inductance from the two IGBTs (10 and 20) to the capacitor core package 100 is ensured to be as same as possible. For example, in some embodiments, the first IGBT 10 and the output busbar (1, 2) may be connected by the same bolt at the connection position (a1, b 1); namely, connecting holes with the same diameter are adopted at the connecting positions (a1 and b1), and screws with the same specification are adopted; the second IGBT20 and the output busbar (1, 2) are connected in a full-solder welding mode at the connection positions (a2, b 2).

For another example, in some possible implementations, the first connection manner may be a non-full-welding type welding manner, and the second connection manner may be a full-welding type welding manner. It is understood that under other equal soldering conditions (e.g., solder, designed soldering area), the connection impedance of the non-full-soldering solder is greater than that of the full-soldering solder to ensure that the equivalent inductance of the two IGBTs (10, 20) to the capacitor core package 100 is as equal as possible.

For another example, in some possible implementation manners, the first connection manner may adopt a first bolt connection, and the second connection manner may adopt a second bolt connection; at least one of the connection contact area, the screw diameter and the screw length of the first bolt connection and the second bolt connection can be set to be different, so that the connection impedance of the first bolt connection is set to be larger than that of the second bolt connection, and the equivalent inductance from the two IGBTs (10 and 20) to the capacitor core package 100 is ensured to be the same as far as possible.

Illustratively, the sizes of the connecting holes adopted in the first bolt connection and the second bolt connection are the same, the lengths of the screws adopted in the first bolt connection and the second bolt connection are the same, but the screw rod diameter of the screw adopted in the first bolt connection is smaller than that of the screw adopted in the second bolt connection, that is, the connecting contact area of the first bolt connection is smaller than that of the second bolt connection, so that the connecting impedance of the first bolt connection is larger than that of the second bolt connection.

In addition, it should be noted that fig. 2 and fig. 3 are both described by taking an example in which a three-phase output bus bar (that is, three groups of IGBTs arranged in parallel) is provided in an inverter, but the present application is not limited thereto, and in some possible implementation manners, a two-phase output bus bar (that is, two groups of IGBTs arranged in parallel) is provided in an inverter.

As can be understood by those skilled in the art, the positive output busbars in different phases are all connected to the positive power supply (BUS +) of the BUS capacitor, and the negative output busbars in different phases are all connected to the negative power supply (BUS-) of the BUS capacitor.

On this basis, in order to ensure that the current values output by the IGBTs arranged in parallel between each phase of output bus bar are the same, in some possible implementation manners, the arrangement manners of the multiple IGBTs arranged in parallel between the positive output bus bar and the negative output bus bar in each phase of output bus bar may be the same. That is to say, the number of the IGBTs arranged in parallel between the positive output busbar and the negative output busbar in each phase of output busbar is the same, and the connection mode between the IGBTs arranged in parallel in different phases and the positive output busbar and the negative output busbar, the distance from the capacitor core package 100, and the like are the same, so as to ensure that the equivalent inductances from the IGBTs arranged in parallel to the capacitor core package 100 are the same one to one.

Schematically, referring to fig. 2, the connection positions of two IGBTs (10, 20) respectively arranged in parallel in three phases and the positive output busbar and the negative output busbar are distributed in two rows along the side surface of the capacitor core package 100 (refer to fig. 2), a first IGBT 10 in the three phases is connected with the positive output busbar and the negative output busbar in a bolt connection manner (the size of the adopted connection hole and the specifications of the screw and the nut are respectively the same), and a second IGBT20 in the three phases is connected with the positive output busbar and the negative output busbar in a full-weld manner.

As can be seen from the above description, the problem of unbalanced dynamic current sharing of the parallel IGBTs (10, 20) is solved by setting the output busbars (1, 2) and the two parallel IGBTs (10, 20) in different connection modes; it is understood that the connection method adopted in practice is not limited to the bolt connection and the welding method mentioned in the foregoing embodiments, and other connection methods capable of adjusting the equivalent inductance at the connection position are also applicable to the present application.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.