Semiconductor device with a plurality of semiconductor chips

文档序号：1078459 发布日期：2020-10-16 浏览：2次中文

阅读说明：本技术 半导体装置 (Semiconductor device with a plurality of semiconductor chips ) 是由掛布光泰市川裕章于 2019-07-23 设计创作，主要内容包括：能够抑制栅极响应速度的降低并且增大利用陶瓷电路基板上的半导体芯片的载置面积。臂部(1、1a)具有半导体芯片(2、3)、电路图案(4、5)和控制布线(6a)。半导体芯片(2、3)在正面的任意的侧部具备控制电极(2a、3a)。电路图案(4)在俯视时呈矩形,以使半导体芯片(2、3)的侧部排列成一列并使控制电极(2a、3a)排列成一列的方式配置有半导体芯片(2、3)。电路图案(5)与控制电极(2a、3a)排列成一列。另外,控制布线(6a)将控制电极(2a、3a)与电路图案(5)电连接。(The area for mounting a semiconductor chip on a ceramic circuit board can be increased while suppressing a decrease in the gate response speed. The arm sections (1, 1a) have semiconductor chips (2, 3), circuit patterns (4, 5), and control wiring (6 a). The semiconductor chips (2, 3) are provided with control electrodes (2a, 3a) on any side portion of the front surface. The circuit pattern (4) is rectangular in plan view, and the semiconductor chips (2, 3) are arranged such that the side portions of the semiconductor chips (2, 3) are arranged in a line and the control electrodes (2a, 3a) are arranged in a line. The circuit pattern (5) and the control electrodes (2a, 3a) are arranged in a line. In addition, the control wiring (6a) electrically connects the control electrodes (2a, 3a) and the circuit pattern (5).)

1. A semiconductor device, comprising a first arm, the first arm comprising:

a first semiconductor chip including a first control electrode on any first side portion of a front surface;

a second semiconductor chip having a second control electrode on an arbitrary second side portion of the front surface;

a first circuit pattern in which the first semiconductor chip and the second semiconductor chip are arranged such that the first side portion and the second side portion are arranged in a line and the first control electrode and the second control electrode are arranged in a line;

a second circuit pattern arranged in a column with the first control electrode and the second control electrode; and

a first control wiring electrically connecting the first control electrode, the second control electrode, and the second circuit pattern.

2. The semiconductor device according to claim 1, wherein the semiconductor device comprises:

a first main current wiring connected to a first main electrode of the front surface of the first semiconductor chip perpendicularly to a connection direction of the first control wiring; and

and a second main current wiring connected to a second main electrode of the front surface of the second semiconductor chip perpendicularly to a connection direction of the first control wiring.

3. The semiconductor device according to claim 1 or 2, further comprising a second arm portion, wherein the second arm portion comprises:

a third semiconductor chip having a third control electrode on any third side portion of the front surface;

a fourth semiconductor chip having a fourth control electrode on an arbitrary fourth side portion of the front surface;

a third circuit pattern in which the third semiconductor chip and the fourth semiconductor chip are arranged such that the third side portion and the fourth side portion are arranged in a row and the third control electrode and the fourth control electrode are arranged in a row in parallel with the first side portion and the second side portion;

a fourth circuit pattern arranged in a column with the third control electrode and the fourth control electrode; and

a second control wiring electrically connecting the third control electrode, the fourth control electrode, and the fourth circuit pattern.

4. The semiconductor device according to claim 3, wherein the fourth circuit pattern is arranged on a side opposite to the second circuit pattern.

5. The semiconductor device according to claim 4, wherein the first main current wiring is electrically connected to the third circuit pattern,

the second main current wiring is electrically connected to the third circuit pattern.

6. The semiconductor device according to any one of claims 3 to 5, wherein the third control electrode and the fourth control electrode are arranged on the second arm portion side on the third circuit pattern.

7. The semiconductor device according to claim 6, wherein a fifth circuit pattern is arranged on the second arm portion on a side opposite to the first arm portion,

the semiconductor device further includes:

a third main current wiring electrically connecting a third main electrode of the front surface of the third semiconductor chip and the fifth circuit pattern perpendicularly to a connection direction of the second control wiring; and

a fourth main current wiring electrically connecting a fourth main electrode of the front surface of the fourth semiconductor chip and the fifth circuit pattern perpendicularly to a connection direction of the second control wiring.

8. The semiconductor device according to any one of claims 3 to 7, wherein the first control wiring continuously connects the first control electrode, the second control electrode, and the second circuit pattern,

the second control wiring continuously connects the third control electrode, the fourth control electrode, and the fourth circuit pattern.

9. The semiconductor device according to claim 7 or 8, wherein the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, and the fourth semiconductor chip are RC-IGBTs,

the first main current wiring, the second main current wiring, the third main current wiring, and the fourth main current wiring are connected to the first main electrode, the second main electrode, the third main electrode, and the fourth main electrode at a plurality of locations, respectively.

10. The semiconductor device according to claim 9, wherein the plurality of sites join FWD regions constituting the first main electrode, the second main electrode, the third main electrode, and the fourth main electrode to a boundary of an IGBT region.

11. The semiconductor device according to any one of claims 3 to 10, wherein a plurality of the first arm portions and the second arm portions are arranged so as to intersect with each other in a predetermined direction.

12. The semiconductor device according to claim 1, wherein the semiconductor device has a first main current wiring which connects a first main electrode of the front surface of the first semiconductor chip and a second main electrode of the front surface of the second semiconductor chip in antiparallel with a connection direction of the first control wiring.

13. The semiconductor device according to claim 12, further comprising a second arm portion, wherein the second arm portion comprises:

a third semiconductor chip having a third control electrode on any third side portion of the front surface;

a fourth semiconductor chip having a fourth control electrode on an arbitrary fourth side portion of the front surface;

a fourth circuit pattern arranged in a column with the third control electrode and the fourth control electrode; and

a second control wiring electrically connecting the third control electrode, the fourth control electrode, and the fourth circuit pattern.

14. The semiconductor device according to claim 13, wherein the fourth circuit pattern is arranged on a side opposite to the second circuit pattern.

15. The semiconductor device according to claim 14, wherein the third circuit pattern includes an extended region which is arranged on an opposite side of the connection direction of the first control wiring with respect to the first circuit pattern and which extends in a direction orthogonal to the connection direction of the first control wiring,

the first main current wiring is electrically connected to the extension region.

16. The semiconductor device according to claim 15, wherein the third control electrode and the fourth control electrode are arranged on opposite sides of the first arm portion on the third circuit pattern in the second arm portion.

17. The semiconductor device according to claim 16, wherein a fifth circuit pattern is arranged on the second arm portion on a side opposite to a connection direction of the second control wiring with respect to the third circuit pattern,

the semiconductor device further has a second main current wiring electrically connecting a third main electrode of the front surface of the third semiconductor chip, a fourth main electrode of the front surface of the fourth semiconductor chip, and the fifth circuit pattern in anti-parallel with a connection direction of the second control wiring.

18. The semiconductor device according to any one of claims 13 to 17, wherein the first control wiring continuously connects the first control electrode, the second control electrode, and the second circuit pattern,

the second control wiring continuously connects the third control electrode, the fourth control electrode, and the fourth circuit pattern.

19. The semiconductor device according to claim 17 or 18, wherein the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, and the fourth semiconductor chip are RC-IGBTs,

20. The semiconductor device according to any one of claims 13 to 18, wherein a plurality of the first arm portions and a plurality of the second arm portions are arranged so as to intersect with each other in a predetermined direction.

Technical Field

The present invention relates to a semiconductor device.

Background

The Semiconductor device includes Semiconductor elements such as an IGBT (Insulated Gate Bipolar Transistor) and a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Such a semiconductor device can exhibit a desired function by disposing a plurality of semiconductor units including the semiconductor element on a heat sink (see, for example, patent document 1).

As an example of the semiconductor unit, an RC (Reverse-Conducting) -IGBT chip formed of an IGBT and an FWD (Free wheeling diode) in one chip is arranged on the circuit pattern. A semiconductor device in which a plurality of such semiconductor units are arranged on a heat sink and electrically connected to each other is used as a power conversion device.

Disclosure of Invention

Technical problem

To miniaturize a semiconductor device, increase a current, and reduce a loss. In order to reduce the size and increase the current, it is necessary to dispose a plurality of semiconductor chips on a circuit pattern with high area efficiency. On the other hand, the gate response speed needs to be kept from decreasing so as not to increase the loss. However, it cannot be said that the arrangement of circuit patterns, semiconductor chips, and wirings in the semiconductor device has been optimized in terms of high area efficiency and no reduction in gate response speed.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor device capable of increasing a mounting area of a semiconductor chip while suppressing a decrease in gate response speed.

Technical scheme

According to an aspect of the present invention, there is provided a semiconductor device including a first arm portion, the first arm portion including: a first semiconductor chip including a first control electrode on any first side portion of a front surface; a second semiconductor chip having a second control electrode on an arbitrary second side portion of the front surface; a first circuit pattern in which the first semiconductor chip and the second semiconductor chip are arranged such that the first side portion and the second side portion are arranged in a line and the first control electrode and the second control electrode are arranged in a line; a second circuit pattern arranged in a line with the first control electrode and the second control electrode; and a first control wiring electrically connecting the first control electrode, the second control electrode, and the second circuit pattern.

Technical effects

According to the disclosed technology, the output current can be increased by increasing the mounting area of the semiconductor chip while suppressing a decrease in the gate response speed.

The above and other objects, features and advantages of the present invention will become apparent from the following description in connection with the accompanying drawings which illustrate preferred embodiments, which are exemplary of the present invention.

Drawings

Fig. 1 is a diagram for explaining an arm portion included in the semiconductor device according to the first embodiment.

Fig. 2 is a plan view of the semiconductor device according to the second embodiment.

Fig. 3 is a plan view of the semiconductor unit of the second embodiment.

Fig. 4 is a sectional view of the semiconductor unit of the second embodiment.

Fig. 5 is a circuit configuration diagram of a semiconductor unit according to a second embodiment.

Fig. 6 is a diagram for explaining connection between the bonding wire of the second embodiment and the output electrode of the semiconductor chip provided in the semiconductor unit.

Fig. 7 is a plan view of the semiconductor unit of the third embodiment.

Description of the symbols

1. 1a arm part

2. 3, 25-28 semiconductor chip

2a, 3a control electrode

4. 5, 24 a-24 e circuit pattern

6a control wiring

6b, 6c, 6d Main Current Wiring

10 semiconductor device

11 Heat dissipation substrate

12 a-12 e, 29 a-29 h bonding wire

20. 20 a-20 f, 30 semiconductor unit

21 ceramic circuit board

22 insulating panel

23 sheet metal

24a1, 24c1, 24e1 contact region

24b1, 24c2, 24d1, 24e2 attachment region

24c3 extended region

25 a-28 a gate electrode

25 b-28 b output electrodes

25b1 FWD region

25b2 IGBT region

29c1 bonding site

A first arm part

B second arm part

Detailed Description

[ first embodiment ]

Hereinafter, an arm included in the semiconductor device according to the first embodiment will be described with reference to fig. 1. Fig. 1 is a diagram for explaining an arm portion included in the semiconductor device according to the first embodiment. Fig. 1 (a) and (B) show the arm 1 included in the semiconductor device according to the first embodiment, and fig. 1 (C) and (D) show the arm 100 and 110 of the reference example included in the semiconductor device, respectively.

The semiconductor device of the first embodiment includes an arm portion 1 shown in fig. 1 (a). The arm portion 1 has semiconductor chips 2, 3, circuit patterns 4, 5, and a control wiring 6 a. The semiconductor chip 2 includes a control electrode 2a on an arbitrary side portion of the front surface, and the semiconductor chip 3 includes a control electrode 3a on an arbitrary side portion of the front surface. The semiconductor chips 2 and 3 include switching elements such as IGBTs and power MOSFETs. Such semiconductor chips 2 and 3 are provided with, for example, an input electrode (drain electrode or collector electrode) as a main electrode on the back surface, and a control electrode (gate electrode) and an output electrode (source electrode or emitter electrode) as a main electrode on the front surface. The semiconductor chips 2 and 3 include diodes such as SBD (Schottky Barrier Diode) and FWD as necessary. Such semiconductor chips 2 and 3 each have an output electrode (cathode) as a main electrode on the back surface thereof and an input electrode (anode) as a main electrode on the front surface thereof. The semiconductor chips 2 and 3 may further include RC-IGBTs that have both functions of an IGBT and an FWD on one chip. The circuit pattern 4 is, for example, rectangular in plan view, and the semiconductor chips 2 and 3 are arranged such that the side portions of the semiconductor chips 2 and 3 are arranged in a line and the control electrodes 2a and 3a are arranged in a line. The circuit pattern 5 is rectangular in plan view, and is aligned in a row with the control electrodes 2a and 3 a. The control wiring 6a electrically connects the control electrodes 2a and 3a to the circuit pattern 5. In the arm 1 shown in fig. 1 (a), the main current wirings 6b and 6c are connected to the main electrodes of the semiconductor chips 2 and 3 perpendicularly to the connection direction of the control wiring 6 a. The perpendicular direction may be 60 ° or more and 120 ° or less with respect to the direction perpendicular to the connection direction of the control wiring 6 a. The control wiring 6a and the main current wirings 6b and 6c are formed of bonding wires, lead frames, or strip-shaped conductive members.

The semiconductor device according to the first embodiment may include an arm portion 1a shown in fig. 1 (B) instead of the arm portion 1. The arm 1a is provided with the same reference numerals as those of the arm 1. In such an arm 1a, the main current wiring 6d is connected to the main electrodes of the semiconductor chips 2 and 3 in parallel with and in reverse to the connection direction of the control wiring 6 a. The parallel direction may be a direction of ± 30 ° with respect to the direction parallel to the connection direction of the control wiring 6 a. The control wiring 6a and the main current wiring 6d are formed of bonding wires, lead frames, or strip-shaped conductive members.

Next, a reference example of such an arm portion 1 will be described. First, the arm portion 100 shown in fig. 1 (C) has semiconductor chips 102, 103, circuit patterns 104, 105, and control wirings 106a1, 106a 2. The semiconductor chips 102 and 103 are, for example, RC-IGBT chips, and have a vertically long shape in plan view. The semiconductor chips 102 and 103 are provided with control electrodes 102a and 103a on the lower side in the front view, respectively. The circuit pattern 104 is rectangular in plan view, and the semiconductor chips 102 and 103 are arranged side by side such that the control electrodes 102a and 103a are arranged in a row. The circuit pattern 105 is arranged on the control electrodes 102a and 103a side separately from the circuit pattern 104. The control wirings 106a1 and 106a2 electrically connect the control electrodes 102a and 103a to the circuit pattern 105. In the arm 100, the main current wirings 106b and 106c are connected to the main electrodes of the semiconductor chips 102 and 103, respectively, at the upper side in the drawing. Such an arm portion 100 can obtain a large amount of output current by utilizing the chip area of the semiconductor chips 102 and 103 in the circuit pattern 104 to the maximum. However, since the semiconductor chips 102 and 103 have a vertically long shape, the current flowing inside the semiconductor chips 102 and 103 flows along the shape, and thus the current path becomes long, and the gate response speed is lowered. Therefore, the gate response speed is reduced relative to the arm portion 1.

In addition, the arm portion 110 shown in fig. 1 (D) has semiconductor chips 112, 113, circuit patterns 114, 115, and control wirings 116a1, 116a 2. The semiconductor chips 112 and 113 are, for example, RC-IGBT chips, and have a substantially square shape in plan view. The semiconductor chips 112 and 113 are provided with control electrodes 112a and 113a, respectively, on the lower side in the front view. The circuit pattern 114 is rectangular in plan view, and the semiconductor chips 112 and 113 are arranged side by side in the upper and lower directions so that the control electrodes 112a and 113a are located on the lower side in the drawing, respectively. The control wires 116a1, 116a2 extend leftward in the drawing from the control electrodes 112a, 113a in accordance with the arrangement of the semiconductor chips 112, 113. In the arm 110, the main current wirings 116b and 116c are connected to the main electrodes of the semiconductor chips 112 and 113 on the right side in the drawing. The circuit pattern 115 is rectangular in plan view, is arranged on the left side of the circuit pattern 114 in the figure, and is connected to the control wirings 116a1 and 116a 2. In the arm portion 110, since the semiconductor chips 112 and 113 have a substantially square shape, a current flowing inside flows along the shape, and thus a current path is shortened as compared with a current path of the arm portion 100, and a decrease in gate response speed is suppressed. However, the semiconductor chips 112, 113 occupy a large area of the circuit pattern 114 due to their shapes. Therefore, the chip area cannot be utilized to the maximum. Therefore, the chip area is reduced relative to the arm portion 1. In addition, when three or more semiconductor chips are arranged in parallel in the vertical direction, the circuit patterns 115 connected to the control wirings 116a1 and 116a2 are arranged to be longer and longer, and occupy a large area.

Thus, the semiconductor device includes the arm portions 1 and 1 a. The arm portions 1, 1a have semiconductor chips 2, 3, circuit patterns 4, 5, and control wirings 6 a. The semiconductor chip 2 includes a control electrode 2a on an arbitrary side portion of the front surface, and the semiconductor chip 3 includes a control electrode 3a on an arbitrary side portion of the front surface. The circuit pattern 4 is rectangular in plan view, and the semiconductor chips 2 and 3 are arranged such that the side portions of the semiconductor chips 2 and 3 are arranged in a line and the control electrodes 2a and 3a are arranged in a line. The circuit pattern 5 and the control electrodes 2a and 3a are arranged in a line. The control wiring 6a electrically connects the control electrodes 2a and 3a to the circuit pattern 5. This makes it possible for the arm portions 1 and 1a to suppress the decrease in the gate response speed and to suppress the occurrence of an uneven current. In addition, the temperature rise at the time of energization can be suppressed to prevent concentration of heat generation. Further, since the mounting area of the semiconductor chips 2 and 3 on the circuit pattern 4 can be used to the maximum, the output current can be increased. Therefore, the characteristics of the semiconductor device including the arm portions 1 and 1a can be improved.

[ second embodiment ]

In the second embodiment, the first embodiment will be specifically described. First, a semiconductor device will be described with reference to fig. 2. Fig. 2 is a plan view of the semiconductor device according to the second embodiment. The semiconductor device 10 includes a heat dissipating substrate 11 and semiconductor cells 20a to 20f electrically connected by bonding wires 12a to 12 e. The heat dissipating substrate 11 is made of, for example, aluminum, iron, silver, copper, or an alloy containing at least one of these, which is excellent in thermal conductivity. In addition, in order to improve corrosion resistance, a material such as nickel may be formed on the surface of the heat dissipating substrate 11 by plating or the like. Specifically, in addition to nickel, there are nickel-phosphorus alloys, nickel-boron alloys, and the like. The heat dissipation substrate 11 is appropriately formed with mounting holes used when mounting to an external device, contact regions for inputting and outputting current to and from the semiconductor units 20a to 20f, and the like. The semiconductor units 20a to 20f are arranged in a row along a predetermined direction on the front surface of the heat dissipating substrate 11 via solder, silver solder, or the like, for example. Such semiconductor units 20a to 20f are provided with semiconductor chips including predetermined semiconductor elements, and thus have desired functions. The number of the semiconductor units 20a to 20f shown in fig. 2 is an example, and a required number thereof may be provided. Hereinafter, the semiconductor units 20a to 20f will be collectively referred to as semiconductor units 20, and the details thereof will be described later. The bonding wires 12a to 12e are made of a metal having excellent conductivity, such as aluminum or copper, or an alloy containing at least one of these metals.

A cooler (not shown) may be attached to the back surface of the heat dissipation substrate 11 of the semiconductor device 10 via a thermal grease such as a silicone resin mixed with a metal oxide filler, thereby improving heat dissipation. The cooler in this case is made of, for example, aluminum, iron, silver, copper, or an alloy containing at least one of these materials, which is excellent in thermal conductivity. Further, as the cooler, a radiator composed of a plurality of fins, a cooling device using water cooling, or the like can be applied. The heat dissipating substrate 11 may be integrally formed with such a cooler. In this case, the heat dissipating substrate 11 is made of aluminum, iron, silver, copper, or an alloy containing at least one of these, which has excellent thermal conductivity. In addition, in order to improve corrosion resistance, a material such as nickel may be formed on the surface of the heat dissipation substrate 11 integrated with the cooler by plating or the like. Specifically, in addition to nickel, there are nickel-phosphorus alloys, nickel-boron alloys, and the like. The semiconductor units 20a to 20f and the heat dissipation substrate 11 of the semiconductor device 10 may be housed in a resin case (not shown). The resin case in this case is molded to include a control terminal for inputting the gate voltage and an external terminal for conducting the input-output voltage.

Next, the semiconductor unit 20 will be described with reference to fig. 3 to 5. Fig. 3 is a plan view of the semiconductor unit of the second embodiment, and fig. 4 is a sectional view of the semiconductor unit of the second embodiment. Fig. 4 shows a cross section at the one-dot chain line X-X in fig. 3. However, the description of the bonding wire is omitted. Fig. 5 is a circuit diagram of a semiconductor unit according to a second embodiment. The semiconductor unit 20 includes a first arm (upper arm) a and a second arm (lower arm) B, and has upper and lower arms formed thereon. As shown in fig. 3 and 4, the semiconductor unit 20 includes a ceramic circuit board 21 and semiconductor chips 25 to 28 provided on the front surface of the ceramic circuit board 21. The ceramic circuit board 21 of the semiconductor unit 20 is disposed on the heat dissipating board 11 via solder, silver solder, or the like (not shown) (see fig. 2).

The semiconductor chips 25 to 28 include RC-IGBT switching elements made of silicon or silicon carbide and formed of an IGBT and an FWD in one chip. The RC-IGBT chip is formed by connecting an IGBT and an FWD in an inverse parallel mode to form a circuit. The semiconductor chips 25 to 28 each include, for example, an input electrode (drain electrode or collector electrode) as a main electrode on the back surface, and a control electrode (gate electrode) and an output electrode (source electrode or emitter electrode) as a main electrode on the front surface. The semiconductor chips 25 to 28 are provided with gate electrodes 25a to 28a at the center of the front side and output electrodes 25b to 28b at the center of the front side. The ceramic circuit board 21 includes an insulating plate 22 and a metal plate 23 formed on the back surface of the insulating plate 22. The ceramic circuit board 21 has circuit patterns 24a to 24e formed on the front surface of the insulating plate 22. The insulating plate 22 is made of high thermal conductivity ceramics such as alumina, aluminum nitride, and silicon nitride having excellent thermal conductivity. The metal plate 23 is made of a metal having excellent thermal conductivity, such as aluminum, iron, silver, copper, or an alloy containing at least one of these metals. The circuit patterns 24a to 24e are made of metal having excellent conductivity, such as copper or copper alloy. In order to improve corrosion resistance, the circuit patterns 24a to 24e may be formed of a material such as nickel on the surface by plating or the like. Specifically, in addition to nickel, there are nickel-phosphorus alloys, nickel-boron alloys, and the like. The circuit patterns 24a to 24e have a thickness of, for example, 0.1mm to 1 mm. As the ceramic circuit board 21 having such a configuration, for example, a DCB (Direct Copper Bonding) board or an AMB (Active metal soldered) board can be used. The ceramic circuit board 21 can conduct heat generated in the semiconductor chips 25 to 28 to the heat dissipation board 11 side through the circuit patterns 24a and 24c, the insulating board 22, and the metal plate 23. The ceramic circuit board 21 is an example, and may be a metal base board or a lead frame having a die pad formed thereon.

The circuit pattern 24a constitutes a collector pattern of the first arm portion a. The circuit pattern 24a is bonded with a collector electrode formed on the back surface of the semiconductor chips 25 and 26 via solder. The circuit pattern 24a has a substantially rectangular shape, and a portion thereof including the contact region 24a1 protrudes to the lower side in fig. 3. In the circuit pattern 24a, the semiconductor chips 25 and 26 are disposed via solder (not shown) so that the gate electrodes 25a and 26a are arranged in a line. The semiconductor chips 25 and 26 are arranged such that the gate electrodes 25a and 26a face a side parallel to the arrangement direction of the semiconductor chips 25 and 26. The gate electrodes 25a, 26a face one side (left side in fig. 3) of the insulating plate 22. The number of the semiconductor chips 25 and 26 may be three or more. In this case, the semiconductor chips are also arranged such that the gate electrodes are oriented to one side parallel to the arrangement direction of the semiconductor chips and the gate electrodes are arranged in a line. The parallel in the present embodiment may be any direction within ± 30 ° with respect to the parallel direction.

The circuit pattern 24b constitutes a control pattern of the first arm portion a. The circuit pattern 24b is connected to bonding wires 29a connected to the gate electrodes 25a, 26a of the semiconductor chips 25, 26. The circuit pattern 24b has a connection region 24b1 located in a column with the gate electrodes 25a, 26a of the semiconductor chips 25, 26. In fig. 3, the circuit pattern 24b extends from the portion including the connection region 24b1 along one side (lower side in fig. 3) of the insulating plate 22, perpendicular to the arrangement direction of the semiconductor chips 25, 26.

The circuit pattern 24c constitutes an emitter pattern of the first arm portion a and a collector pattern of the second arm portion B. The circuit pattern 24c is connected with bonding wires 29c and 29d connected to output electrodes (emitter electrodes) 25b and 26b of the semiconductor chips 25 and 26. Further, the circuit pattern 24c is bonded with a collector electrode formed on the back surface of the semiconductor chips 27 and 28 via solder. The circuit pattern 24c has a substantially rectangular shape, and a portion thereof including the contact region 24c1 protrudes to the upper side in fig. 3. The circuit pattern 24c is arranged on the opposite side (right side in fig. 3) of the gate electrodes 25a and 26a in parallel with the circuit pattern 24 a. The circuit pattern 24c has a connection region 24c2 of the bonding wires 29c, 29d in parallel with the arrangement of the semiconductor chips 25, 26. In the circuit pattern 24c, the semiconductor chips 27 and 28 are disposed via solder (not shown) so that the gate electrodes 27a and 28a are aligned in a row. The semiconductor chips 27 and 28 are arranged such that the gate electrodes 27a and 28a face a side parallel to the arrangement direction of the semiconductor chips 27 and 28. The arrangement of the gate electrodes 27a, 28a may be parallel to the arrangement of the gate electrodes 25a, 26a of the first arm portion a. The gate electrodes 27a, 28a face the first arm a side (one side (left side in fig. 3) of the insulating plate 22). The number of the semiconductor chips 27 and 28 may be three or more. In this case, the semiconductor chips are also arranged such that the gate electrodes are oriented to one side parallel to the arrangement direction of the semiconductor chips and the gate electrodes are arranged in a line.

The circuit pattern 24d constitutes a control pattern of the second arm portion B. The circuit pattern 24d is connected with bonding wires 29b connected to the gate electrodes 27a, 28a of the semiconductor chips 27, 28. The circuit pattern 24d has a connection region 24d1, and the connection region 24d1 is located in a row with the gate electrodes 27a, 28a of the semiconductor chips 27,28 and is located on the opposite side of the connection region 24b1 with the semiconductor chips 25 to 27 interposed therebetween. In fig. 3, the circuit pattern 24d extends from the portion including the connection region 24d1 along one side (upper side in fig. 3) of the insulating plate 22, perpendicularly to the arrangement direction of the semiconductor chips 27, 28. The perpendicular direction in the present embodiment may be a direction that is 60 ° or more and 120 ° or less with respect to the direction orthogonal to the reference direction (the arrangement direction in this case). The circuit pattern 24e constitutes an emitter pattern of the second arm portion B. The circuit pattern 24e has a connection region 24e2, the connection region 24e2 is connected to bonding wires 29e, 29f, and the bonding wires 29e, 29f are connected to output electrodes (emitter electrodes) 27b, 28b of the semiconductor chips 27, 28. The circuit pattern 24e has a connection region 24e2 arranged in parallel with the circuit pattern 24c and on the opposite side (right side in fig. 3) of the gate electrodes 27a, 28 a. Therefore, the circuit pattern 24e has a portion disposed on the opposite side of the circuit pattern 24a with the circuit pattern 24c interposed therebetween. The circuit pattern 24e has an L shape that is orthogonal between two orthogonal sides of the circuit pattern 24c and two sides of the insulating plate 22. Such a circuit pattern 24e is provided with a connection region 24e2 in a right portion in fig. 3 of the insulating plate 22, and a contact region 24e1 in a lower portion in fig. 3 of the insulating plate 22.

The bonding wires 29a to 29f are made of metal such as aluminum or copper having excellent conductivity, or an alloy containing at least one of these metals. The bonding wires preferably have a diameter of 100 μm or more and 1mm or less. The bonding wire 29a electrically connects the gate electrode 25a of the semiconductor chip 25, the gate electrode 26a of the semiconductor chip 26, and the connection region 24b1 of the circuit pattern 24b arranged in a row by continuous bonding. The bonding wire 29b electrically connects the gate electrode 27a of the semiconductor chip 27, the gate electrode 28a of the semiconductor chip 28, and the connection region 24d1 of the circuit pattern 24d arranged in a row by continuous bonding. The bonding wire 29c electrically connects the output electrode 25b of the semiconductor chip 25 and the circuit pattern 24c perpendicularly to the connection direction of the bonding wire 29 a. At this time, the bonding wire 29c continuously connects a plurality of portions on the output electrode 25b of the semiconductor chip 25 and the connection region 24c2 of the circuit pattern 24 c. The bonding wire 29d electrically connects the output electrode 26b of the semiconductor chip 26 and the circuit pattern 24c perpendicularly to the connection direction of the bonding wire 29 a. At this time, the bonding wire 29d continuously connects a plurality of portions on the output electrode 26b of the semiconductor chip 26 to the connection region 24c2 of the circuit pattern 24 c. The bonding wire 29e electrically connects the output electrode 27b of the semiconductor chip 27 and the circuit pattern 24e perpendicularly to the connection direction of the bonding wire 29 b. At this time, the bonding wire 29e continuously connects a plurality of portions on the output electrode 27b of the semiconductor chip 27 to the connection region 24e2 of the circuit pattern 24 e. The bonding wire 29f electrically connects the output electrode 28b of the semiconductor chip 28 and the circuit pattern 24e perpendicularly to the connection direction of the bonding wire 29 b. At this time, the bonding wire 29f connects a plurality of portions on the output electrode 28b of the semiconductor chip 28 and the connection region 24e2 of the circuit pattern 24e by continuous bonding.

The inverter circuit shown in fig. 5 is thus configured by the semiconductor chips 25 to 28, the circuit patterns 24a to 24e, and the bonding wires 29a to 29 f. The semiconductor unit 20 constitutes a first arm portion (upper arm portion) a by the semiconductor chips 25, 26, the circuit patterns 24a, 24b, and the bonding wire 29 a. In addition, the semiconductor unit 20 constitutes a second arm portion (lower arm portion) B by the semiconductor chips 27,28, the circuit patterns 24c, 24d, and the bonding wire 29B. The semiconductor unit 20 is connected to an electrical device outside the semiconductor device 10 via an external connection terminal (not shown) formed of a lead frame or the like. The external connection terminal is provided with a C1 terminal (corresponding to contact zone 24a1), an E2 terminal (corresponding to contact zone 24E1), and an E1C2 terminal (corresponding to contact zone 24C 1). A high potential terminal of the external power supply is connected to the C1 terminal serving as the input P terminal, and a low potential terminal of the external power supply is connected to the E2 terminal serving as the input N terminal. A load (not shown) is connected to the E1C2 terminal of the semiconductor unit 20, which is the output U terminal. Thus, the semiconductor unit 20 functions as an inverter. In the semiconductor unit 20 having such a configuration, for example, external connection terminals (not shown) are bonded to the contact regions 24a1, 24c1, and 24e1, and the semiconductor chips 25 to 28 and the bonding wires 29a to 29f on the ceramic circuit board 21 are packaged with a package. In this case, as the encapsulating member, a thermosetting resin such as a maleimide-modified epoxy resin, a maleimide-modified phenol resin, or a maleimide resin can be used.

Next, stitch bonding of the bonding wires 29c, 29d, 29e, and 29f to the output electrodes 25b to 28b of the semiconductor chips 25 to 28 will be described with reference to fig. 6. Fig. 6 is a diagram for explaining connection between the bonding wire of the second embodiment and the output electrode of the semiconductor chip provided in the semiconductor unit. Note that fig. 6 shows an example of the semiconductor chip 25 among the semiconductor chips 25 to 28, and fig. 6 (a) and (B) show the semiconductor chips 25 as different types of RC-IGBT chips, respectively. As shown in fig. 6 (a), the semiconductor chip 25 is alternately configured with FWD regions 25b1 and IGBT regions 25b2 in the output electrode 25 b. When the bonding wire 29c is connected to such an output electrode 25b by stitch bonding, bonding is performed at a bonding site 29c1 at the boundary of the FWD region 25b1 and the IGBT region 25b 2. As shown in fig. 6 (B), the semiconductor chip 25 is bonded to the output electrode 25B of a type different from that of fig. 6 (a) at the bonding site 29c1 at the boundary between the FWD region 25B1 and the IGBT region 25B 2. This can suppress the heat generated from the output electrode 25b of the semiconductor chip 25 from being biased toward the bonding wire 29c, and can prevent the occurrence of a failure or the like due to the heat of the semiconductor chip 25. The same applies to the other semiconductor chips 26 to 28.

In the semiconductor device 10, a plurality of semiconductor units 20 are arranged in one direction on the heat dissipation substrate 11. The semiconductor unit 20 includes a first arm a (upper arm) and a second arm B (lower arm). The first arm portion (upper arm portion) a has semiconductor chips 25, 26, a circuit pattern 24a, and a bonding wire 29 a. The semiconductor chips 25 and 26 are RC-IGBT chips, have a substantially square shape, and are provided with gate electrodes 25a and 26a on any side portion of the front surface. The circuit pattern 24a is formed in a rectangular shape in plan view, and the semiconductor chips 25 and 26 are arranged such that the side portions of the substantially square semiconductor chips 25 and 26 are arranged in a line, and the gate electrodes 25a and 26a are arranged in a line. The connection region 24b1 of the circuit pattern 24b is aligned in a line with the gate electrodes 25a, 26 a. In addition, the bonding wire 29a electrically connects the gate electrodes 25a, 26a and the connection region 24b1 of the circuit pattern 24b by stitch bonding. The second arm portion (lower arm portion) B similarly has semiconductor chips 27,28 of substantially square shape, a circuit pattern 24c, and a bonding wire 29B. The semiconductor chips 27 and 28 are RC-IGBT chips, have a substantially square shape, and are provided with gate electrodes 27a and 28a on any side portion of the front surface. The circuit pattern 24c is formed in a rectangular shape in plan view, and the semiconductor chips 27 and 28 are arranged such that the side portions of the semiconductor chips 27 and 28 are arranged in a line and the gate electrodes 27a and 28a are arranged in a line. The connection region 24d1 of the circuit pattern 24d is aligned in a line with the gate electrodes 27a, 28 a. In addition, the bonding wire 29b electrically connects the gate electrodes 27a, 28a and the connection region 24d1 of the circuit pattern 24d by stitch bonding.

Thus, the first arm portion (upper arm portion) a and the second arm portion (lower arm portion) B can suppress a decrease in the gate response speed, and thus can suppress generation of an uneven current. This can suppress a temperature rise at the time of energization to prevent concentration of heat generation. Further, since the mounting area of the semiconductor chips 25 to 28 on the circuit patterns 24a and 24c can be used to the maximum, the output current can be increased. In the semiconductor unit 20, the bonding wires 29a wired to the gate electrodes 25a and 26a of the semiconductor chips 25 and 26 and the bonding wires 29b wired to the gate electrodes 27a and 28a of the semiconductor chips 27 and 28 are wired in opposite directions, respectively. Therefore, the semiconductor unit 20 is arranged such that the circuit pattern 24a and the semiconductor chips 25, 26 are substantially point-symmetrical with the circuit pattern 24c and the semiconductor chips 27,28, and with the bonding wires 29a, 29 b. Therefore, the heat generation bias of the semiconductor unit 20 at the time of energization is suppressed. Therefore, occurrence of a failure or the like due to the bias of heat generated by the semiconductor unit 20 can be prevented.

In the semiconductor unit 20, the bonding wires 29c to 29f are connected to the output electrodes 25b to 28b of the semiconductor chips 25 to 28 by stitch bonding so as to cross the boundary between the FWD region and the IGBT region. Therefore, the heat generated from the output electrodes 25b to 28b of the semiconductor chips 25 to 28 can be prevented from being biased toward the bonding wires 29c to 29f, and the occurrence of a failure or the like due to the heat of the semiconductor chips 25 to 28 can be prevented.

The number of the semiconductor chips 25 to 28 of the semiconductor unit 20 is an example, and is not limited to the case where two semiconductor chips are arranged for each arm, and the semiconductor unit is configured by two arms. For example, three or more semiconductor chips may be arranged for each arm. In this case, the semiconductor chips are also arranged such that the gate electrodes are oriented to one side parallel to the arrangement direction of the semiconductor chips and the gate electrodes are arranged in a line. In addition, for example, an IGBT chip and an FWD chip may be simultaneously arranged as semiconductor chips for each arm. In this case, the plurality of IGBT chips are also arranged such that the gate electrodes face a side parallel to the arrangement direction of the semiconductor chips and the gate electrodes are arranged in a line. The plurality of FWD chips may be arranged in another column parallel to the column of the IGBT chips, or may be arranged in the same column as the IGBT chips. In addition, for example, the semiconductor unit 20 may be constituted by three or more arms. In this case, the three or more arms are arranged side by side in a direction perpendicular to the arrangement direction of the semiconductor chips.

[ third embodiment ]

In the third embodiment, a case of a semiconductor cell different from the semiconductor cell 20 of the second embodiment will be described with reference to fig. 7. That is, in the semiconductor unit according to the third embodiment, the connection direction of the bonding wire connected to the output electrode of the semiconductor chip and the connection direction of the bonding wire connected to the gate electrode of the semiconductor chip are antiparallel. Fig. 7 is a plan view of the semiconductor unit of the third embodiment. In the semiconductor unit 30 of the third embodiment, the same components as those of the semiconductor unit 20 of the second embodiment are denoted by the same reference numerals, and descriptions thereof are omitted. The semiconductor unit 30 has the same ceramic circuit board (fig. 4) as the semiconductor unit 20, but has a different circuit pattern shape, and realizes the same circuit configuration (fig. 5).

The semiconductor unit 30 also includes a first arm (upper arm) a and a second arm (lower arm) B, and has upper and lower arms formed thereon. The circuit pattern 24a constitutes a collector pattern of the first arm portion a. The circuit pattern 24a is bonded with a collector electrode formed on the back surface of the semiconductor chips 25 and 26 via solder. The circuit pattern 24a has a substantially rectangular shape, and a portion thereof including the contact region 24a1 protrudes to the lower side in fig. 7. In the circuit pattern 24a, the semiconductor chips 25 and 26 are disposed via solder (not shown) so that the gate electrodes 25a and 26a are arranged in a line. The semiconductor chips 25 and 26 are arranged such that the gate electrodes 25a and 26a face a side parallel to the arrangement direction of the semiconductor chips 25 and 26. The gate electrodes 25a, 26a face one side (left side in fig. 7) of the insulating plate 22. Note that the number of the semiconductor chips 25 and 26 may be 3 or more. In this case, the semiconductor chips are also arranged such that the gate electrodes are oriented in a side parallel to the arrangement direction of the semiconductor chips and the gate electrodes are arranged in a line. The parallel in the present embodiment may be any direction within ± 30 ° with respect to the parallel direction.

The circuit pattern 24b constitutes a control pattern of the first arm portion a. The circuit pattern 24b is connected to bonding wires 29a connected to the gate electrodes 25a, 26a of the semiconductor chips 25, 26. The circuit pattern 24b has a connection region 24b1 located in a column with the gate electrodes 25a, 26a of the semiconductor chips 25, 26. In fig. 7, the circuit pattern 24b extends from the portion including the connection region 24b1 along one side (lower side in fig. 7) of the insulating plate 22 perpendicularly to the arrangement direction of the semiconductor chips 25, 26.

The circuit pattern 24c constitutes an emitter pattern of the first arm portion a and a collector pattern of the second arm portion B. The circuit pattern 24c is connected to bonding wires 29g connected to output electrodes (emitter electrodes) 25b and 26b of the semiconductor chips 25 and 26. Further, the circuit pattern 24c is bonded with a collector electrode formed on the back surface of the semiconductor chips 27 and 28 via solder. As shown in fig. 7, the circuit pattern 24c has a substantially L-shape along one of the right side and the upper side of the semiconductor unit 30. The right region of the circuit pattern 24c is disposed on the opposite side of the gate electrodes 25a and 26 a. In this region, semiconductor chips 27 and 28 are arranged. The upper region of the circuit pattern 24c is an extension region 24c3 extending leftward from above the right region along one side of the upper side of the semiconductor unit 30. That is, the extension region 24c3 is arranged on the opposite side of the connection direction of the bonding wire 29a with respect to the circuit pattern 24a, and extends in a direction orthogonal to the connection direction. The extension region 24c3 of the circuit pattern 24c includes a contact region 24c1 to which external connection terminals (not shown) are connected, and a connection region 24c2 of the bonding wire 29 g. The extension region 24c3 of the circuit pattern 24c has a connection region 24c2, and this connection region 24c2 is located on an extension line parallel to the arrangement of the semiconductor chips 25, 26 and connected to a bonding wire 29g connected to the output electrodes (emitter electrodes) 25b, 26b of the semiconductor chips 25, 26. In the circuit pattern 24c, the semiconductor chips 27 and 28 are disposed via solder (not shown) so that the gate electrodes 27a and 28a are aligned in a row. The semiconductor chips 27 and 28 are arranged such that the gate electrodes 27a and 28a face a side parallel to the arrangement direction of the semiconductor chips 27 and 28. The arrangement of the gate electrodes 27a, 28a may be parallel to the arrangement of the gate electrodes 25a, 26a of the first arm portion a. The gate electrodes 27a, 28a are located on the opposite side of the gate electrodes 25a, 26a and face the first arm portion a side (one side (right side in fig. 7) of the insulating plate 22). The number of the semiconductor chips 27 and 28 may be three or more. In this case, the semiconductor chips are also arranged such that the gate electrodes are oriented to one side parallel to the arrangement direction of the semiconductor chips and the gate electrodes are arranged in a line.

The circuit pattern 24d constitutes a control pattern of the second arm portion B. The circuit pattern 24d is connected with bonding wires 29b connected to the gate electrodes 27a, 28a of the semiconductor chips 27, 28. The circuit pattern 24d has a connection region 24d1, and the connection region 24d1 is located in a row with the gate electrodes 27a, 28a of the semiconductor chips 27,28 and at a position point-symmetrical to the connection region 24b 1. In fig. 7, the circuit pattern 24d extends from the portion including the connection region 24d1 along one side (upper side in fig. 7) of the insulating plate 22 perpendicularly to the arrangement direction of the semiconductor chips 27, 28. The perpendicular direction in the present embodiment may be a direction that is 60 ° or more and 120 ° or less with respect to the direction orthogonal to the reference direction (the arrangement direction in this case). The circuit pattern 24e constitutes an emitter pattern of the second arm portion B. The circuit pattern 24e has a connection region 24e2, the connection region 24e2 is connected to a bonding wire 29h, and the bonding wire 29h is connected to the output electrodes (emitter electrodes) 27b, 28b of the semiconductor chips 27, 28. The circuit pattern 24e has a land 24e2, and the land 24e2 is arranged on the opposite side (lower side in fig. 7) of the circuit pattern 24d in parallel with the circuit pattern 24c and the protruding portion of the circuit pattern 24 a. Such a circuit pattern 24e is also provided with a contact region 24e1 at a portion on the lower right side in fig. 7 of the insulating plate 22.

The bonding wires 29g and 29h are configured similarly to the bonding wires 29a to 29f of the second embodiment. The bonding wire 29a electrically connects the gate electrode 25a of the semiconductor chip 25, the gate electrode 26a of the semiconductor chip 26, and the connection region 24b1 of the circuit pattern 24b arranged in a row by continuous bonding. The bonding wire 29b electrically connects the gate electrode 27a of the semiconductor chip 27, the gate electrode 28a of the semiconductor chip 28, and the connection region 24d1 of the circuit pattern 24d arranged in a row by continuous bonding.

The bonding wire 29g electrically connects the output electrode 25b of the semiconductor chip 25, the output electrode 26b of the semiconductor chip 26, and the circuit pattern 24c in reverse and parallel to the connection direction of the bonding wire 29 a. At this time, the bonding wire 29g continuously joins and connects a plurality of portions on the output electrode 25b of the semiconductor chip 25, a plurality of portions on the output electrode 26b of the semiconductor chip 26, and the connection region 24c2 of the circuit pattern 24 c. The bonding wire 29h electrically connects the output electrode 27b of the semiconductor chip 27, the output electrode 28b of the semiconductor chip 28, and the circuit pattern 24e in reverse and parallel to the connection direction of the bonding wire 29 b. At this time, the bonding wire 29h connects a plurality of portions on the output electrode 27b of the semiconductor chip 27, a plurality of portions on the output electrode 28b of the semiconductor chip 28, and the connection region 24e2 of the circuit pattern 24e by continuous bonding. Note that the bonding wires 29g and 29h also perform stitch bonding as described in fig. 6.

In this manner, the inverter circuit shown in fig. 5 is configured by the semiconductor chips 25 to 28, the circuit patterns 24a to 24e, and the bonding wires 29a, 29b, 29g, and 29h, as in the second embodiment. The first arm portion (upper arm portion) a of the semiconductor unit 30 is constituted by the semiconductor chips 25, 26, the circuit patterns 24a, 24b, and the bonding wire 29 a. In addition, the second arm portion (lower arm portion) B of the semiconductor unit 30 is constituted by the semiconductor chips 27,28, the circuit patterns 24c, 24d, and the bonding wire 29B. The semiconductor unit 30 is connected to an electrical device outside the semiconductor device 10 via an external connection terminal (not shown) formed of a lead frame or the like. The external connection terminal is provided with a C1 terminal (corresponding to contact zone 24a1), an E2 terminal (corresponding to contact zone 24E1), and an E1C2 terminal (corresponding to contact zone 24C 1). A high potential terminal of the external power supply is connected to the C1 terminal serving as the input P terminal, and a low potential terminal of the external power supply is connected to the E2 terminal serving as the input N terminal. A load (not shown) is connected to the E1C2 terminal of the semiconductor unit 30, which is the output U terminal. Thus, the semiconductor unit 30 functions as an inverter. In the semiconductor unit 30 having such a configuration, for example, external connection terminals (not shown) are bonded to the contact regions 24a1, 24c1, and 24e1, and the semiconductor chips 25 to 28 and the bonding wires 29a, 29b, 29g, and 29h on the ceramic circuit board 21 are packaged with a package member.

In the semiconductor device 10 including the semiconductor unit 30, the first arm portion (upper arm portion) a and the second arm portion (lower arm portion) B can suppress a decrease in the gate response speed, and thus can suppress generation of an uneven current, as in the second embodiment. This can suppress a temperature rise at the time of energization to prevent concentration of heat generation. Further, since the mounting area of the semiconductor chips 25 to 28 on the circuit patterns 24a and 24c can be used to the maximum, the output current can be increased. In the semiconductor unit 30, the bonding wires 29a wired to the gate electrodes 25a and 26a of the semiconductor chips 25 and 26 and the bonding wires 29b wired to the gate electrodes 27a and 28a of the semiconductor chips 27 and 28 are wired in opposite directions, respectively. Therefore, the semiconductor unit 30 is arranged such that the circuit pattern 24a and the semiconductor chips 25 and 26, the circuit pattern 24c and the semiconductor chips 27 and 28 are substantially point-symmetrical with respect to the bonding wires 29a and 29 b. Therefore, the semiconductor unit 30 is suppressed from generating heat during energization. Therefore, occurrence of a failure or the like due to the bias of heat generated by the semiconductor unit 30 can be prevented.

The foregoing merely illustrates the principles of the invention. Further, it will be apparent to those skilled in the art that numerous modifications and variations can be made, and the present invention is not limited to the exact construction and application examples shown and described, and all modifications and equivalents corresponding thereto are deemed to be within the scope of the present invention as defined in the appended claims and equivalents thereof.

The claims (modification according to treaty clause 19)