阅读说明：本技术 具有电平移位器的集成电路 (Integrated circuit with level shifter ) 是由 S·E·芬恩 于 2019-03-20 设计创作，主要内容包括：半导体管芯包括耦合到正差分输入(202)和负差分输入(203)的电平移位器(254)。电平移位器(254)包括第一运算放大器(240),其被配置为生成耦合到正差分输出(280)和负差分输出(282)的内部共模电压。正交流(AC)耦合前馈路径包括耦合到正差分输入(202)和正差分输出(280)的第一电容器(210)。负AC耦合前馈路径包括耦合到负差分输入(203)和负差分输出(282)的第二电容器(211)。正直流(DC)前馈路径(260)耦合到正差分输入(202)、内部共模电压感测节点(242)和正差分输出(280)。负DC前馈路径(262)耦合到负差分输入(203)、内部共模电压感测节点(242)和负差分输出(282)。(The semiconductor die includes a level shifter (254) coupled to the positive differential input (202) and the negative differential input (203). The level shifter (254) includes a first operational amplifier (240) configured to generate an internal common mode voltage coupled to a positive differential output (280) and a negative differential output (282). A positive Alternating Current (AC) coupled feedforward path includes a first capacitor (210) coupled to a positive differential input (202) and a positive differential output (280). The negative AC coupled feed forward path includes a second capacitor (211) coupled to the negative differential input (203) and the negative differential output (282). A positive Direct Current (DC) feed-forward path (260) is coupled to the positive differential input (202), the internal common mode voltage sense node (242), and the positive differential output (280). A negative DC feed-forward path (262) is coupled to the negative differential input (203), the internal common mode voltage sense node (242), and the negative differential output (282).)

1. A semiconductor die, comprising:

a level shifter coupled to a positive differential input and to a negative differential input, the level shifter comprising a first operational amplifier, wherein the first operational amplifier is configured to generate an internal common-mode voltage at an internal common-mode voltage sense node that is independent of an input common-mode voltage of the positive and negative differential inputs, and wherein the internal common-mode voltage sense node is coupled to a positive differential output and to a negative differential output;

a quadrature flow coupled feedforward path, a positive AC coupled feedforward path, including a first capacitor coupled to the positive differential input and to the positive differential output;

a negative AC coupled feedforward path including a second capacitor coupled to the negative differential input and to the negative differential output;

a positive Direct Current (DC) feed-forward path coupled to the differential input, to the internal common mode voltage sense node, and to the positive differential output; and

a negative AC feed-forward path coupled to the differential input, to the internal common mode voltage sense node, and to the negative differential output.

2. The semiconductor die of claim 1, wherein the level shifter comprises:

a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor coupled in series between a first node coupled to receive the positive differential input and a second node coupled to receive the negative differential input;

a first transconductor coupled to a third node connecting the third resistor and the fourth resistor and controlled by an output of the operational amplifier; and

a second transconductor coupled to a fourth node connecting the fifth resistor and the sixth resistor and controlled by the output of the first operational amplifier.

3. The semiconductor die of claim 2, wherein the internal common mode voltage sense node is a fifth node connecting the fourth resistor to the fifth resistor.

4. The semiconductor die of claim 2, wherein the first transconductor and the second transconductor are Metal Oxide Semiconductor Field Effect Transistors (MOSFETs).

5. The semiconductor die of claim 2, wherein

The positive DC feed-forward path includes: the third resistor, a seventh resistor, and a second operational amplifier configured as a buffer amplifier having an output coupled to a first lead of the seventh resistor and having a positive input coupled to the third node, the seventh resistor having a second lead coupled to the positive differential output, and

the negative DC feed-forward path includes: the sixth resistor, an eighth resistor, and a third operational amplifier configured as a buffer amplifier having an output coupled to a first lead of the eighth resistor and having a positive input coupled to the fourth node, the eighth resistor having a second lead coupled to the negative differential output.

6. The semiconductor die of claim 1, wherein semiconductor die is configured to present an input impedance of about 50 ohms to the positive differential input and an input impedance of about 50 ohms to the negative differential input.

7. The semiconductor die of claim 1, further comprising an input common mode voltage reference configured to establish an input common mode voltage for the semiconductor die.

8. A semiconductor die, comprising:

a differential input regulation stage comprising:

a differential input configured to provide a predetermined input impedance and to provide a predetermined input common mode voltage, a level shifter coupled to the differential input and configured to generate an internal common mode voltage independent of the predetermined input common mode voltage at an internal common mode voltage sense node,

a quadrature flow coupled feedforward path, i.e., a positive AC coupled feedforward path, having a first capacitor coupled to the differential input and to a positive differential output of the differential input regulation stage,

a negative AC-coupled feed-forward path having a second capacitor coupled to the differential input and to a negative differential output of the differential input regulation stage,

a positive DC feed-forward path, i.e., a positive DC feed-forward path, coupled to the differential inputs, to the internal common mode voltage sense node, and to the positive differential output of the differential input regulation stage, an

A negative DC feed-forward path coupled to the differential input, to the internal common mode voltage sense node, and to the negative differential output of the differential input regulation stage, an

A data communication processing circuit coupled to the positive differential output, coupled to the negative differential output of the differential input regulation stage, and configured to output a data communication signal.

9. The semiconductor die of claim 8, wherein the data communication processing circuit is configured to receive signals having a common mode voltage level associated with the internal common mode voltage reference from the positive differential output and the negative differential output of the differential input regulation stage.

10. The semiconductor die of claim 8, wherein the data communication processing circuit is a continuous-time linear equalizer.

11. The semiconductor die of claim 8, wherein the data communication processing circuit is a decision feedback equalizer.

12. The semiconductor die of claim 8, wherein the die comprises 16 interface channels.

13. The semiconductor die of claim 8, wherein the die comprises 32 interface channels.

14. A communication interface integrated circuit, comprising:

a plurality of input pins;

a plurality of output pins;

a semiconductor die connected to the input pin and the output pin, the semiconductor die comprising:

an input regulation circuit, comprising:

a differential input coupled to a plurality of the input pins and configured to provide a predetermined input impedance and to provide a predetermined input common mode voltage,

a level shifter coupled to the differential input and configured to generate an internal common mode voltage independent of the predetermined input common mode voltage at an internal common mode voltage sense node,

a quadrature flow coupled feedforward path, i.e., a positive AC coupled feedforward path, having a first capacitor coupled to a positive differential input of the differential inputs and to a positive differential output of the input regulation circuit,

a negative AC-coupled feed-forward path having a second capacitor coupled to a negative differential input of the differential input and to a negative differential output of the input regulation circuit,

a positive Direct Current (DC) feedforward path coupled to the positive differential input of the differential inputs, to the internal common-mode voltage sensing node and to the positive differential output of the input regulation circuit, an

A negative DC feed-forward path coupled to the negative differential input of the differential inputs, to the internal common-mode voltage sense node and to the negative differential output of the input regulation circuit, an

A signal processing circuit coupled to a plurality of the output pins, coupled to the input conditioning circuit, and configured to receive the positive differential output and the negative differential output of the input conditioning circuit, process the positive differential output and the negative differential output of the input conditioning circuit, and output a data communication signal on the plurality of output pins.

15. The communication interface integrated circuit of claim 14, wherein the negative level shifter comprises: a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor coupled in series between the positive differential input and the negative differential input; a first transconductor coupled to a node connecting the third resistor and the fourth resistor and controlled by an output of an operational amplifier having a negative input coupled to the internal common-mode voltage sense node and a positive input coupled to an internal common-mode voltage reference; and a second transconductor coupled to a node connecting the fifth resistor and the sixth resistor and controlled by the output of the operational amplifier.

16. The communication interface integrated circuit of claim 15, wherein the internal common mode voltage sense node is a node connecting the fourth resistor to the fifth resistor.

17. The communication interface integrated circuit of claim 15, wherein the first transconductor and the second transconductor are Metal Oxide Semiconductor Field Effect Transistors (MOSFETs).

18. The communication interface integrated circuit of claim 15, wherein the data communication processing circuit is a continuous-time linear equalizer.

19. The communication interface integrated circuit of claim 15, wherein the data communication processing circuit is a decision feedback equalizer.

20. The communication interface integrated circuit of claim 15, wherein the differential input of the input regulation circuit is configured to present an input impedance of about 50 ohms on the plurality of input pins.

Technical Field

The present disclosure relates generally to broadband data transmission over wires.

Background

When the wideband transmitter is separate from the wideband receiver, the receiver desirably conditions the input signal received from the transmitter. In addition, the receiver desirably presents an interface to the transmitter that conforms to the transmitter's expectations or can accommodate the transmitter's expected range.

Disclosure of Invention

According to at least one example, a semiconductor die includes a level shifter coupled to a positive differential input and to a negative differential input, the level shifter including a first operational amplifier, wherein the first operational amplifier is configured to generate an internal common mode voltage independent of an input common mode voltage of the positive and negative differential inputs at an internal common mode voltage sensing node, and wherein the internal common mode voltage sensing node is coupled to the positive differential output and to the negative differential output. The semiconductor die includes: a positive Alternating Current (AC) coupled feedforward path including a first capacitor coupled to a positive differential input and to a positive differential output; a negative AC coupled feedforward path including a second capacitor coupled to the negative differential input and to the negative differential output; a positive Direct Current (DC) feed-forward path coupled to the differential input, to the internal common mode voltage sense node, and to the positive differential output; and a negative DC feed-forward path coupled to the differential input, to the internal common mode voltage sense node, and to the negative differential output.

According to at least one example, a semiconductor die includes a differential input conditioning stage and a data communication processing circuit. The differential input regulation stage comprises: a differential input configured to provide a predetermined input impedance and to provide a predetermined input common mode voltage; a level shifter coupled to the differential input and configured to generate an internal common mode voltage independent of the predetermined input common mode voltage at an internal common mode voltage sensing node; a positive Alternating Current (AC) coupled feedforward path having a first capacitor coupled to the differential input and to a positive differential output of the differential input regulation stage; a negative AC coupled feed forward path having a second capacitor coupled to the differential input and to a negative differential output of the differential input regulation stage; a positive Direct Current (DC) feed-forward path coupled to the differential input, to the internal common mode voltage sense node, and to a positive differential output of the differential input regulation stage; and a negative DC feed-forward path coupled to the differential input, to the internal common mode voltage sense node, and to a negative differential output of the differential input regulation stage. The data communication processing circuit is coupled to the positive differential output, to the negative differential output of the differential input conditioning stage, and configured to output a data communication signal.

According to at least one example, a communication interface integrated circuit comprises: a plurality of input pins, a plurality of output pins, and a semiconductor die connected to the input pins and the output pins. The semiconductor die includes an input conditioning circuit, the input conditioning circuit comprising: a differential input coupled to the plurality of input pins and configured to provide a predetermined input impedance and to provide a predetermined input common mode voltage; a level shifter coupled to the differential input and configured to generate an internal common mode voltage independent of the predetermined input common mode voltage at an internal common mode voltage sensing node; a positive Alternating Current (AC) coupled feedforward path having a first capacitor coupled to a positive differential input of the differential input and to a positive differential output of the input regulation circuit; a negative AC-coupled feed-forward path having a second capacitor coupled to a negative differential input of the differential input and to a negative differential output of the input regulation circuit; a positive Direct Current (DC) feedforward path coupled to a positive differential input of the differential input, to the internal common-mode voltage sensing node, and to a positive differential output of the input regulation circuit, and a negative DC feedforward path coupled to a negative differential input of the differential input, to the internal common-mode voltage sensing node, and to a negative differential output of the input regulation circuit. The semiconductor die further includes a signal processing circuit coupled to the plurality of output pins, coupled to the input conditioning circuit, and configured to receive the positive and negative differential outputs of the input conditioning circuit, process the positive and negative differential outputs of the input conditioning circuit, and output a data communication signal on the plurality of output pins.

Drawings

Fig. 1 illustrates an integrated circuit according to various examples.

Fig. 2 illustrates a communication node according to various examples.

Fig. 3 illustrates a wideband differential conditioning circuit in accordance with various examples.

Fig. 4 illustrates another wideband differential conditioning circuit, in accordance with various examples.

Fig. 5 illustrates yet another wideband differential conditioning circuit, in accordance with various examples.

Detailed Description

In the past, when connecting wired communication paths to integrated circuits on a Printed Circuit Board (PCB), it was customary to provide Alternating Current (AC) coupling on the PCB external to the integrated circuit. In an example, such AC coupling supports connecting transmitters and receivers with different common mode voltage requirements. For example, the input signal is fed through an AC coupling capacitor positioned close to the integrated circuit on the PCB. Due to the limitations of PCB layout and the increase in PCB density, it is desirable in certain Integrated Circuit (IC) designs to: (a) provisions are made within the IC to interconnect transmitters external to the IC with on-chip receivers having different common-mode voltage requirements, rather than relying on AC coupling capacitors located on a PCB external to the IC, and (b) to provide a DC signal path with high-speed data throughput. These design goals constitute contradictory requirements to some extent and therefore present significant design challenges.

The present specification provides examples of systems that address the above-mentioned design goals. According to a disclosed example, a system includes a semiconductor die, a set of input and output pins connected to the semiconductor die, and a package encapsulating the semiconductor die. The system provides broadband data processing. In an example, the system provides a data channel retimer, a data transfer buffer, a data transfer repeater, a data high speed interface, or a data path interface. The system is suitable for long-range serial wired communications, where "long range" refers to communications over a distance from 2 centimeters to 200 meters. However, the system is not limited to long distances, and in examples, the system is used on a short distance package between two dies or for links across large dies. In an example, the system provides data throughput of at least 1 gigabit per second (Gbps) throughput. In an example, the system provides a data throughput of at least 10 Gbps. In an example, the system provides a data throughput of at least 25 Gbps. In an example, the system provides a data throughput of at least 50 Gbps. In an example, the system provides a data throughput of at least 100 Gbps. The teachings of the present specification are applicable to systems that provide different high speed data throughputs.

Fig. 1 shows a diagram of an Integrated Circuit (IC)10 or chip according to various examples. IC 10 includes a package 12, a semiconductor die 14 encapsulated within package 12, a plurality of inputs 16 connected to die 14, and a plurality of outputs 18 connected to die 14. In an example, the package 12 comprises a plastic or ceramic material. IC 10 has any number of inputs 16 and any number of outputs 18. Inputs 16 and outputs 18 are connected to die 14 in any desired pattern and physical layout. Although shown as wires or leads in fig. 1, in an example, the inputs 16 and outputs 18 are pads or contact points. In an example, IC 10 is a multi-channel retimer, a multi-channel buffer, a multi-channel repeater, or a multi-channel interface. In an example, IC 10 is a communication interface integrated circuit. In an example, IC 10 is a multi-channel communication interface integrated circuit. Die 14 is fabricated using any of a variety of known semiconductor fabrication processes. In some examples, IC 10 comprises at least a portion of a communication system, examples of which are described below.

Fig. 2 shows a communication system 100. In an example, the system 100 is implemented in a wired data communication path and may be implemented in part by the IC 10 described above. In an example, the system 100 includes a data transmitter 101 communicatively coupled to a communication node 103. In an example, the communication node 103 comprises the IC 10. The communication node 103 includes: a first differential input 102 coupled to a first differential input conditioning stage 104, the first differential input conditioning stage 104 coupled to a first data communication processing circuit 106, the first data communication processing circuit 106 coupled to a first signal output 108; a second differential input 112 coupled to a second differential input conditioning stage 114, the second differential input conditioning stage 114 coupled to a second data communication processing circuit 116, the second data communication processing circuit 116 coupled to a second signal output 118; and a third differential input 122 coupled to a third differential input conditioning stage 124, the third differential input conditioning stage 124 coupled to a third data communication processing circuit 126, the third data communication processing circuit 126 coupled to a third signal output 128. In use, the signal outputs 108, 118, 128 output data communication signals. In an example, additional components are included in the communication node 103, such as additional signal inputs, additional differential input conditioning stages, additional data communication processing circuits, and/or additional outputs.

A differential signal consists of the difference between two separate signals, for example the voltage difference between two different voltage signals. One component of the differential signal is referred to as the positive component of the differential signal and the other component of the differential signal is referred to as the negative component of the differential signal, although both components have positive and negative values at different times. In an example, the differential signal is used in case noise is likely to disturb the value of the signal, since noise typically disturbs each component of the differential signal in the same sense, which does not affect the difference between the two components of the differential signal, i.e. the signal content. In other words, in an example, differential signaling provides enhanced noise immunity compared to single-ended signaling.

The first differential input 102, components 104 and 106, and signal output 108 comprise a first channel of node 103; second differential input 112, components 114 and 116, and signal output 118 comprise a second channel of node 103; and differential input 122, components 124 and 126, and signal output 128 comprise a third channel of node 103. In an example, node 103 includes any desired number of channels. In the example, node 103 includes 16 channels. In the example, node 103 includes 24 channels. In the example, node 103 includes 32 channels. In an example, transmitter 101 is communicatively coupled to node 103 via differential inputs 102, 112, 122 over a long-range broadband wired communication path. For convenience of description, the "long distance" ranges from 1 cm to 200 m. However, the node 103 is not limited to applications involving long distances, and in examples, the node 103 is used on a short distance package between two dies or for links across a large die. For convenience of description, "broadband" includes data communication at data communication rates of up to 1Gbps or up to 10Gbps or up to 25Gbps or higher. The trend in the data communications industry is to extend the upper limit of data throughput, thereby extending the scope of the term "broadband".

In an example, the data communication processing circuit 106, 116, 126 is a continuous-time linear equalizer, a decision feedback equalizer, or other differential receiver. The data communication processing circuits 106, 116, 126 are sometimes referred to as signal processing circuits. The data communication processing circuitry 106, 116, 126 is sometimes referred to as a receiver or alternatively includes a receiver.

Each of the differential inputs 102, 112, and 122 includes a positive differential input and a negative differential input. The signal content on the differential inputs 102, 112, 122 is contained in the difference between the voltages of the positive differential input and the corresponding negative differential input. For example, the differential input 102 is the difference between a positive differential input and a negative differential input corresponding to the differential input 102. The average voltage between a positive differential input and its corresponding negative differential input is referred to as the common mode voltage of the differential inputs 102, 112, 122. The transmitter 101 provides or outputs differential inputs 102, 112, 122. The transmitter 101 is configured to output differential inputs 102, 112, 122 having a predetermined common mode voltage. It is desirable that the differential input regulation stages 104, 114, 124 be configured to compatibly interface with a predetermined common mode voltage level output by the transmitter 101. Each of the data communication processing circuits 106, 116, 126 has a predetermined internal common mode voltage, which in an example is different from a predetermined common mode voltage associated with the transmitter 101.

In an example, each of the differential input regulation stages 104, 114, 124 provides a desired input impedance to the transmitter 101 (the input impedance seen by the transmitter 101 to the differential inputs 102, 112, 124) and provides an input common mode voltage that conforms to the desired common mode voltage of the transmitter 101. In an example, the input impedance provided by each of the differential input regulation stages 104, 114, 124 is about 50 ohms. As used herein, the expression "about 50 ohms" means between 45 ohms and 55 ohms. In other examples, the differential input regulation stages 104, 114, 124 provide different predetermined input impedances. In an example, the differential input regulation stage 104, 114, 124 provides an internal common mode voltage to the data communication processing circuit 106, 116, 126 that is different from the input common mode voltage. In some cases, the internal common mode voltage is considered to be independent of the input common mode voltage. In an example, the differential input conditioning stages 104, 114, 124 provide positive and negative differential AC-coupled signal paths and positive and negative real DC signal paths to feed differential data received from the transmitter 101 to the data communication processing circuits 106, 116, 126. These combined AC-coupled signal paths and true DC signal paths implemented by the differential input conditioning stages 104, 114, 124 facilitate improved bandwidth and greater resistance to baseline wander.

In an example, the signal outputs 108, 118, 128 are differential outputs. In an example, the signal outputs 108, 118, 128 are not differential outputs, but single-ended signal outputs. In an example, the content of the signal output 108, 118, 128 is data or data communication content.

Fig. 3 illustrates a differential input conditioning circuit 200 according to various examples. In an example, each of the differential input conditioning stages 104, 114, 124 described above with reference to fig. 2 is implemented at least in part as the circuit 200 shown in fig. 3. In some cases, the differential input regulation circuit 200 is referred to as a differential regulation stage. The circuit 200 provides various functions that fall under the heading "differential input regulation". As seen by transmitter 101, circuit 200 provides a desired input impedance and input common mode voltage level. The circuit 200 provides a desired internal common mode voltage level for internal signal processing circuitry (e.g., data communication processing circuitry 106, 116, 126), where the internal common mode voltage may be different from the input common mode voltage seen by the transmitter 101. In other words, the circuit 200 provides an internal common mode voltage that is independent of the input common mode voltage. In operation, the circuit 200 provides the AC-coupled differential signals to internal processing circuitry, such as the data communication processing circuitry 106, 116, 126. Further, the circuit 200 provides a true DC signal path to internal processing circuitry, such as the data communication processing circuitry 106, 116, 126. The true DC signal path is also a level shifted true DC signal path. While in the above description all components of the circuit 200 together provide all of the functionality attributed to the circuit 200, some components are more responsible for some functions than others.

The circuit 200 includes a positive differential input 202 and a negative differential input 203. In some cases, the positive differential input 202 and the negative differential input 203 are collectively referred to as differential inputs of the circuit 200. The differential inputs are said to provide a predetermined input impedance and to provide a predetermined input common mode voltage.

In an example, the circuit 200 includes a first resistor 204 coupled to the positive differential input 202 at a first lead and coupled to a first lead of a first capacitor 206 at a second lead. A second lead of the first capacitor 206 is coupled to ground. The circuit 200 also includes a second resistor 205 coupled at a first lead to the negative differential input 203 and coupled at a second lead to a first lead of a capacitor 206 and a second lead of the first resistor 204. In an example, the circuit 200 further includes a switch 207 and an input common mode voltage reference 208. In an example, the input common mode voltage reference 208 is provided as a voltage source derived from a DC voltage source distributed within the circuit 200, for example from an access voltage divider that steps down the DC voltage source to a desired voltage value. When switch 207 is controlled to be closed, input common mode voltage reference 208 is coupled into circuit 200 and sets the input common mode voltage of circuit 200. The same design of circuit 200 is used to accommodate different input common mode voltages desired by different transmitters 101, for example, by adjusting the level or value of input common mode voltage reference 208, such as by dividing a standard supply voltage level across a pair of resistors (not shown) or using a potentiometer (not shown). When the switch 207 is controlled to be open, as shown in fig. 3, the input common mode voltage of the circuit 200 is floated by the first capacitor 206, and in this example, the input common mode voltage is determined by a transmitter (e.g., transmitter 101) coupled to the differential inputs 202, 203. The values of the first resistor 204 and the second resistor 205 establish the input impedance of the circuit 200 seen by the transmitter 101. In an example, the resistance of the first resistor 204 and the second resistor 205 is about 50 ohms, but in other examples, the resistance of the first resistor 204 and the second resistor 205 is different than 50 ohms.

The circuit 200 also includes a second capacitor 210 and a third capacitor 211. The second capacitor 210 AC couples the positive differential input 202 to the positive differential output 280 and the third capacitor 211 AC couples the negative differential input 203 to the negative differential output 282. A first lead of the second capacitor 210 is coupled to the positive differential input 202 and a second lead of the second capacitor 210 is coupled to the positive differential output 280. A first lead of the third capacitor 211 is coupled to the negative differential input 203 and a second lead of the third capacitor is coupled to the negative differential output 282. In an example, the second capacitor 210 and the third capacitor 211 establish an interface capacitance seen by the transmitter 101 and establish a maximum data throughput or maximum speed of the circuit 200. In an example, the second capacitor 210 and the third capacitor 211 have capacitance values of about 1 picofarad (pF). In an example, the second capacitor 210 and the third capacitor 211 have capacitance values less than about 2.5 pF. In other examples, the second capacitor 210 and the third capacitor 211 have capacitance values other than 1 pF. The second capacitor 210 provides a positive differential AC signal path and the third capacitor 211 provides a negative differential AC signal path. The positive differential AC signal path is sometimes referred to as a positive AC-coupled feed-forward path, and the negative differential AC signal path is sometimes referred to as a negative AC-coupled feed-forward path. The second capacitor 210 blocks low frequency components of the positive differential input 202 and the third capacitor 211 blocks low frequency components of the negative differential input 203. The second capacitor 210 passes the high frequency component of the positive differential input 202 to the positive differential output 280 and the third capacitor 211 passes the high frequency component of the negative differential input 203 to the negative differential output 282.

In an example, the circuit 200 also includes a third resistor 220, a fourth resistor 222, a fifth resistor 230, and a sixth resistor 232. A first lead of a third resistor 220 is coupled to the positive differential input 202 and a second lead of the third resistor 220 is coupled to a first lead of a fourth resistor 222. A second lead of the fourth resistor 222 is coupled to a first lead of a sixth resistor 232. A second lead of the sixth resistor 232 is coupled to a first lead of the fifth resistor 230 and a second lead of the fifth resistor 230 is coupled to the negative differential input 203. The third resistor 220 and the fourth resistor 222 are coupled in series with each other. The fourth resistor 222 and the sixth resistor 232 are coupled in series with each other. The sixth resistor 232 and the fifth resistor 230 are coupled in series with each other. A third resistor 220, a fourth resistor 222, a sixth resistor 232 and a fifth resistor 230 are coupled in series with each other in the given order.

The resistors 220, 222, 230, 232 provide an internal common mode voltage at node 242, and at node 242, a second lead of the fourth resistor 222 is coupled to a first lead of the sixth resistor 232. In some cases, pin 242 is referred to as an internal common mode voltage sense node. The voltage at node 242 also provides feedback to circuit 200 to establish and maintain a desired internal common mode voltage. Resistors 220, 222, 230, 232 also participate in level shifting of the internal common mode voltage of circuit 200 relative to the input common mode voltage of circuit 200.

In an example, the circuit 200 also includes a first operational amplifier (op amp)224 and a second operational amplifier 234. The positive lead of the first operational amplifier 224 is coupled to the second lead of the third resistor 220 and the first lead of the fourth resistor 222, the negative lead of the first operational amplifier 224 is coupled to the output of the first operational amplifier 224, and the output of the first operational amplifier 224 is also coupled to the first lead of the seventh resistor 226. A second lead of the seventh resistor 226 is coupled to the positive differential output 280 and a second lead of the second capacitor 210. The first operational amplifier 224, when connected, acts as a unity gain amplifier or buffer amplifier feeding the level shifted internal common mode voltage component and the low frequency component of the positive differential input 202 into the positive differential output 280 to be superimposed with the AC coupled high frequency component of the positive differential input 202 passed to the positive differential output 280 through the second capacitor 210. The signal path from the positive differential input 202 through the third resistor 220, through the first operational amplifier 224, through the seventh resistor 226 to the positive differential output 280 is referred to as the positive DC feed forward path 260.

The positive lead of the second operational amplifier 234 is coupled to the second lead of the sixth resistor 232 and the first lead of the fifth resistor 230, the negative lead of the second operational amplifier 234 is coupled to the output of the second operational amplifier 234, and the output of the second operational amplifier 234 is also coupled to the first lead of the eighth resistor 236. A second lead of the eighth resistor 236 is coupled to the negative differential output 282 and to a second lead of the third capacitor 211. The second operational amplifier 234 functions as a unity gain amplifier or buffer amplifier when connected to feed the level shifted internal common mode voltage component and the low frequency component of the negative differential input 203 into the negative differential output 282 to be superimposed with the AC coupled high frequency component of the negative differential input 203 passed to the negative differential output 282 through the third capacitor 211. The signal path from the negative differential input 203 through the fifth resistor 230, through the second operational amplifier 234, through the eighth resistor 236 to the negative differential output 282 is referred to as the negative DC feed forward path 262.

In an example, the circuit 200 further comprises a third operational amplifier 240, a first transconductor 243 and a second transconductor 245. In an example, the transconductor is a voltage controlled current source. The negative input 242 of the third operational amplifier 240 is coupled to the second lead of the fourth resistor 222 and the first lead of the sixth resistor 232, the positive input of the third operational amplifier 240 is coupled to an internal common mode voltage reference 244, and the output 246 of the third operational amplifier 240 is coupled to an input of a first transconductor 243 and an input of a second transconductor 245. The internal common mode voltage reference 244 is provided as a voltage source derived from a DC voltage source distributed within the circuit 200, for example from an access voltage divider that steps down the DC voltage source to a predetermined value of the internal common mode voltage. The output of the first transconductor 243 is coupled to the second lead of the third resistor 220. The output of the second transconductor 245 is coupled to a first lead of a fifth resistor 230. The third operational amplifier 240 controls the first transconductor 243 to drive the current through the third resistor 220 and controls the second transconductor 245 to drive the current through the fifth resistor 230 to drive the internal common mode voltage to be consistent with the internal common mode voltage reference 244 (e.g., the voltage difference between 244 and the node 242 is about zero). In some cases, the first transconductor 243 and the second transconductor 245 are referred to as current generators or voltage controlled current sources. The internal common mode voltage is used as feedback in the control loop by the third operational amplifier 240.

Resistors 220, 222, 232, and 230; a third operational amplifier 240; and transconductors 243, 245 create a level shifter 254. In some cases, level shifter 254 is referred to as an internal common mode voltage stage and is coupled to the differential input and configured to generate an internal common mode voltage independent of the predetermined input common mode voltage. The third operational amplifier 240 and transconductors 243, 245 maintain the internal common mode voltage of the differential outputs 280, 282 and provide a level shift relative to the input common mode voltage of the circuit 200. The third operational amplifier 240 senses the actual internal common mode voltage of the circuit 200 at its negative input 242 (the node connecting the second lead of the fourth resistor 222 and the first lead of the sixth resistor 232) and compares this feedback value to an internal common mode voltage reference 244. When the sensed value of the internal common mode voltage on the negative input 242 is different from the internal common mode voltage reference 244, the output 246 of the third operational amplifier 240 controls the transconductors 243, 245 to flow current through the resistors 220, 222, 230, 232 to adaptively adjust the actual internal common mode voltage to be equal to the internal common mode voltage reference 244. A sensed value of the actual internal common mode voltage is present at the node formed by the second lead of the fourth resistor 222 and the first lead of the sixth resistor 232.

In an example, most components of circuit 200 exhibit symmetry in topology and component values between a positive differential portion of circuit 200 and a negative differential portion of circuit 200. The resistance of the first resistor 204 is approximately equal to the resistance of the second resistor 205. The capacitance of the second capacitor 210 is approximately equal to the capacitance of the third capacitor 211. The resistance of the third resistor 220 is approximately equal to the resistance of the fifth resistor 230. The resistance of the fourth resistor 222 is approximately equal to the resistance of the sixth resistor 232. The resistance of the seventh resistor 226 is approximately equal to the resistance of the eighth resistor 236.

In an example, the first resistor 204 is about 50 ohms, the second resistor 205 is about 50 ohms, the third resistor 220 is about 10 kiloohms, the fifth resistor 230 is about 10 kiloohms, the fourth resistor 222 is about 200 kiloohms, the sixth resistor 232 is about 200 kiloohms, the seventh resistor 226 is about 20 kiloohms, and the eighth resistor 236 is about 20 kiloohms. In other examples, the resistance values of resistors 204, 205, 220, 222, 230, 232, 226, 236 are different from the resistance values listed above. In an example, the resistance of the sum of the resistance of the third resistor 220 and the resistance of the fourth resistor 222 is much greater than the resistance of the first resistor 204; the resistance of the fourth resistor 222 is much greater than the resistance of the third resistor 220; the resistance of the sum of the resistance of the fifth resistor 230 and the resistance of the sixth resistor 232 is much greater than the resistance of the second resistor 205; the resistance of the sixth resistor 232 is much greater than the resistance of the fifth resistor 230. As used herein, "substantially greater" in the context of "the resistance of resistor X is substantially greater than the resistance of resistor Y" means at least 10 times greater. In an example, the first capacitor 206 is about 50pF, the second capacitor 210 is about 1pF, and the third capacitor 211 is about 1 pF. In other examples, the capacitance values of the capacitors 206, 210, 211 are different from the capacitance values listed above.

Fig. 4 illustrates a differential input conditioning circuit 300 according to various examples. The circuit 300 is substantially similar to the circuit 200 described above, wherein the first transconductor 243 of the circuit 200 is replaced by a first NMOSFET 247, the second transconductor 245 of the circuit 200 is replaced by a second NMOSFET 248, and the polarity of the input to the operational amplifier 240 is as shown in fig. 4. The MOSFET is a Metal Oxide Semiconductor (MOS) Field Effect Transistor (FET). The source lead of the first NMOSFET 247 and the source lead of the second NMOSFET 248 are coupled to ground. In an example, the transconductor 243, 245 is replaced by a first Bipolar Junction Transistor (BJT) and a second BJT. Resistors 220, 222, 232, and 230; a third operational amplifier 240; and the NMOSFETs 247, 248 establish a negative level shifter 256 (e.g., the internal common mode voltage level is less than the input common mode voltage level).

Fig. 5 illustrates a differential input conditioning circuit 400 according to various examples. The circuit 400 is substantially similar to the circuit 200 described above, in that the first transconductor 243 of the circuit 200 is replaced by a first PMOSFET 277, the second transconductor 245 of the circuit 200 is replaced by a second PMOSFET 278, and the polarity of the input to the operational amplifier 240 is as shown in fig. 5. The source lead of the first PMOSFET 277 is coupled to a voltage source 273 and the source lead of the second PMOSFET 278 is coupled to a voltage source 275. In the example, the voltage sources 273, 275 are powered by the same voltage source. Resistors 220, 222, 232, and 230; a third operational amplifier 240; and PMOSFETs 277, 278 establish a positive level shifter 276 (e.g., the internal common mode voltage level is greater than the input common mode voltage level).

In this specification, the terms "couple" or "coupling" refer to an indirect or direct connection. Thus, if a first device couples to a second device, that connection may be through a direct connection or through an indirect connection via other devices and connections.

Modifications may be made in the described embodiments within the scope of the claims, and other embodiments are possible.