阅读说明：本技术 一种超低功耗定时开关系统及实现方法 (Ultra-low power consumption timing switch system and implementation method ) 是由 张春红 高恬溪 单晓涛 于 2021-07-08 设计创作，主要内容包括：一种超低功耗定时开关系统及实现方法,包括LX04低频振荡器、频率占空比调节模块和触发模块；LX04低频振荡器、频率占空比调节模块和触发模块依次连接,LX04低频振荡器用于产生信号,频率占空比调节模块按照期望调整LX04低频振荡器输出的脉冲,触发模块利用频率占空比调节模块输出的信号来控制负载的通断。该定时开关内含有一个超低功耗的频率占空比可调的定时器,它的功耗远低于现有的低频振荡器,达到了nW级别,触发模块通过该定时器的信号来控制负载的通断。通过这种方式,大大减少了系统本身的静态功耗和定时功耗。(An ultra-low power consumption timing switch system and an implementation method thereof comprise an LX04 low-frequency oscillator, a frequency duty cycle adjusting module and a triggering module; the LX04 low-frequency oscillator, the frequency duty cycle adjusting module and the triggering module are sequentially connected, the LX04 low-frequency oscillator is used for generating signals, the frequency duty cycle adjusting module adjusts pulses output by the LX04 low-frequency oscillator according to expectation, and the triggering module controls the on-off of a load by using the signals output by the frequency duty cycle adjusting module. The timing switch is internally provided with a timer with ultralow power consumption and adjustable frequency duty ratio, the power consumption of the timer is far lower than that of the existing low-frequency oscillator, the nW level is reached, and the trigger module controls the on-off of a load through a signal of the timer. In this way, the static power consumption and timing power consumption of the system itself are greatly reduced.)

1. An ultra-low power consumption timing switch system is characterized by comprising an LX04 low-frequency oscillator, a frequency duty cycle adjusting module and a triggering module; the LX04 low-frequency oscillator, the frequency duty cycle adjusting module and the triggering module are sequentially connected, the LX04 low-frequency oscillator is used for generating signals, the frequency duty cycle adjusting module adjusts pulses output by the LX04 low-frequency oscillator according to expectation, and the triggering module controls the on-off of a load by using the signals output by the frequency duty cycle adjusting module.

2. The ultra-low power consumption timing switch system of claim 1, wherein the LX04 low frequency oscillator comprises three LX01 voltage detection chips, a resistor R1, a resistor R2 and a PMOS transistor Q1; the three LX01 voltage detection chips are respectively LX01-A, LX01-B and LX01-C, the output of the LX01-A is connected with the input of the LX01-B through a pull-up resistor R1, the output of the LX01-B is connected with the input of the LX01-C through a pull-up resistor R2, meanwhile, the resistor R1 and the resistor R2 are also connected with the grid electrode of a PMOS tube Q1, and the output of the LX01-C is connected with the input of the LX01 through a pull-up resistor; the source of the PMOS transistor Q1 is connected to the first power supply VDD1, and the drain is connected to the output VOD of LX 01-C.

3. The ultra-low power consumption timing switch system of claim 2, wherein all three LX01 voltage detecting chips are grounded.

4. The ultra-low power consumption timing switch system of claim 2, wherein the frequency duty cycle adjusting module comprises a frequency divider, a NOR gate resistor R3 and a capacitor C1; the output VOD1 of LX01-C is connected to the input of the divider; the frequency divider has an output a and an output b, wherein the output a is directly connected with the input a of the OR-NOT gate, the output b is connected with an RC delay circuit formed by R3 and C1, the signal of the output b path is delayed, and the anode of C1 is connected with the other input b of the NOR gate.

5. The ultra-low power consumption timing switch system as claimed in claim 4, wherein the cathode of C1 is grounded.

6. The ultra-low power consumption timing switch system of claim 4, wherein the trigger module comprises an LX01 voltage detection circuit, a pull-up resistor R4, an NMOS-Q2, a power management module and a load; the output OUT of the frequency duty ratio adjusting module is connected with the input end of the LX01 voltage detection circuit, the output VOD2 of the frequency duty ratio adjusting module is connected with the grid electrode of the NMOS-Q2 through a pull-up resistor R4, the drain electrode of the NMOS-Q2 is connected with a second power supply VDD2, and the source electrode of the NMOS-Q2 is connected with the input end of power supply management; the load is placed on the output of the power management.

7. The ultra-low power consumption timing switch system of claim 6, wherein one end of the power management is grounded.

8. An implementation method of an ultra-low power consumption time switch is characterized in that, based on any one of claims 1 to 7, the ultra-low power consumption time switch system comprises the following steps:

when the voltage of Vin is lower than the threshold VTH of the LX01 voltage detection circuit, the output is in a high-impedance state, the output of LX01 is kept at a high level, when the voltage of Vin is higher than the threshold VTH of the LX01 voltage detection circuit, the output is pulled to GND, the output of LX01 voltage detection circuit transitions to a low level, and the voltage to Vin is kept lower than the falling threshold VTL of the LX01 voltage detection circuit; when the LX01-B outputs a high level, the PMOS-Q1 is in a high-impedance state, when the output is low level, the PMOS-Q1 is conducted, the conduction and high-impedance states of the PMOS-Q1 and the LX01-C are complementary, when the output of the LX01-C is in a high-impedance state, the PMOS-Q1 is in a conduction state, and when the output of the LX01-C is grounded, the PMOS-Q1 is in a high-impedance state;

the duty ratio of the periodic signal, namely the proportion of the activated load to the shutdown time, is controlled by adjusting the values of a resistor R3 and a capacitor C1 in the RC delay circuit;

when the LX01-D output VOD2 is low, the PMOS-Q2 is conducted, the VDD2 is converted into the voltage VDD3 required by the load through power management, the load system is activated, when the LX01-D output is high, the PMOS-Q2 is disconnected, the power management output VDD3 is 0V, and the load enters a shutdown state.

Technical Field

The invention belongs to the technical field of timing switches, and particularly relates to an ultra-low power consumption timing switch system and an implementation method thereof.

Background

The existing measuring instrument usually acquires environmental parameters at regular time through a sensor to realize a measuring function, and a large amount of power consumption is consumed in the timing process when the sensor does not start measuring in the real-time detection process. This presents an inconvenience for many applications, particularly in applications that require battery power or that do not facilitate battery replacement.

Disclosure of Invention

The invention aims to provide an ultra-low power consumption timing switch system and an implementation method thereof, so as to solve the problems.

In order to achieve the purpose, the invention adopts the following technical scheme:

an ultra-low power consumption timing switch system comprises an LX04 low-frequency oscillator, a frequency duty cycle adjusting module and a trigger module; the LX04 low-frequency oscillator, the frequency duty cycle adjusting module and the triggering module are sequentially connected, the LX04 low-frequency oscillator is used for generating signals, the frequency duty cycle adjusting module adjusts pulses output by the LX04 low-frequency oscillator according to expectation, and the triggering module controls the on-off of a load by using the signals output by the frequency duty cycle adjusting module.

Further, the LX04 low-frequency oscillator comprises three LX01 voltage detection chips, a resistor R1, a resistor R2 and a PMOS tube Q1; the three LX01 voltage detection chips are respectively LX01-A, LX01-B and LX01-C, the output of the LX01-A is connected with the input of the LX01-B through a pull-up resistor R1, the output of the LX01-B is connected with the input of the LX01-C through a pull-up resistor R2, meanwhile, the resistor R1 and the resistor R2 are also connected with the grid electrode of a PMOS tube Q1, and the output of the LX01-C is connected with the input of the LX01 through a pull-up resistor; the source of the PMOS transistor Q1 is connected to the first power supply VDD1, and the drain is connected to the output VOD of LX 01-C.

Further, all three LX01 voltage detection chips are grounded.

Further, the frequency duty cycle adjusting module comprises a frequency divider, a nor gate resistor R3 and a capacitor C1; the output VOD1 of LX01-C is connected to the input of the divider; the frequency divider has an output a and an output b, wherein the output a is directly connected with the input a of the OR-NOT gate, the output b is connected with an RC delay circuit formed by R3 and C1, the signal of the output b path is delayed, and the anode of C1 is connected with the other input b of the NOR gate.

Further, the negative terminal of C1 is grounded.

Further, the trigger module comprises an LX01 voltage detection circuit, a pull-up resistor R4, an NMOS-Q2, a power management module and a load; the output OUT of the frequency duty ratio adjusting module is connected with the input end of the LX01 voltage detection circuit, the output VOD2 of the frequency duty ratio adjusting module is connected with the grid electrode of the NMOS-Q2 through a pull-up resistor R4, the drain electrode of the NMOS-Q2 is connected with a second power supply VDD2, and the source electrode of the NMOS-Q2 is connected with the input end of power supply management; the load is placed on the output of the power management.

Further, one end of the power management is grounded.

Further, an implementation method of an ultra-low power consumption timing switch includes the following steps:

when the voltage of Vin is lower than the threshold VTH of the LX01 voltage detection circuit, the output is in a high-impedance state, the output of LX01 is kept at a high level, when the voltage of Vin is higher than the threshold VTH of the LX01 voltage detection circuit, the output is pulled to GND, the output of LX01 voltage detection circuit transitions to a low level, and the voltage to Vin is kept lower than the falling threshold VTL of the LX01 voltage detection circuit; when the LX01-B outputs a high level, the PMOS-Q1 is in a high-impedance state, when the output is low level, the PMOS-Q1 is conducted, the conduction and high-impedance states of the PMOS-Q1 and the LX01-C are complementary, when the output of the LX01-C is in a high-impedance state, the PMOS-Q1 is in a conduction state, and when the output of the LX01-C is grounded, the PMOS-Q1 is in a high-impedance state;

the duty ratio of the periodic signal, namely the proportion of the activated load to the shutdown time, is controlled by adjusting the values of a resistor R3 and a capacitor C1 in the RC delay circuit;

when the LX01-D output VOD2 is low, the PMOS-Q2 is conducted, the VDD2 is converted into the voltage VDD3 required by the load through power management, the load system is activated, when the LX01-D output is high, the PMOS-Q2 is disconnected, the power management output VDD3 is 0V, and the load enters a shutdown state.

Compared with the prior art, the invention has the following technical effects:

the invention relates to an ultra-low power consumption timing switch device and an implementation method thereof, the scheme mainly comprises three parts, namely an LX04 low-frequency oscillator which is a source of signals, a frequency duty ratio adjusting module adjusts pulses output by an LX04 according to expectation, and a triggering module controls the on-off of a load by using the signals output by the frequency duty ratio adjusting module. The LX04 low-frequency oscillator generates an alternating current signal with a fixed period under a certain direct current voltage, and when R1 of the module is 1.4M omega, R2 of the module is 100M omega, the PMOS threshold voltage Vgs (th) is-1V, and the power supply VDD is 1.2V, the average power consumption is only 64 nA. The timing switch is internally provided with a timer with ultralow power consumption and adjustable frequency duty ratio, the power consumption of the timer is far lower than that of the existing low-frequency oscillator, the nW level is reached, and the trigger module controls the on-off of a load through a signal of the timer. In this way, the static power consumption and timing power consumption of the system itself are greatly reduced.

The NOR gate outputs the two signals after NOR operation, and the duty ratio of the output signals can be adjusted by adjusting the parameters of the RC delay circuit.

Drawings

FIG. 1 is a schematic diagram of the system architecture of the present invention;

fig. 2 is a signal control schematic diagram of an LX01 voltage detection circuit according to the present invention.

Fig. 3 is a logic timing diagram of the present invention.

Detailed Description

The invention is further described below with reference to the accompanying drawings:

referring to fig. 1 to 3, the present invention relates to an ultra-low power consumption time switch system and an implementation method thereof, the scheme mainly includes three parts, LX04 low frequency oscillator, which is a source of signal, a frequency duty cycle adjusting module adjusts pulse output by LX04 according to expectation, and a trigger module controls on/off of a load by using the signal output by the frequency duty cycle adjusting module.

The LX04 low-frequency oscillator can be composed of three or more LX01 voltage detection chips, the output of LX01-A is connected with the input of LX01-B through a pull-up resistor R1, the output of LX01-B is connected with the input of LX01-C through a pull-up resistor R2 and is also connected with the grid of a PMOS tube Q1, and the output of LX01-C is connected with the input of LX01 through a pull-up resistor. The source of the PMOS transistor Q1 is connected to the power supply VDD1, and the drain is connected to the output VOD of LX 01-C. The module generates an alternating current signal with a fixed period under a certain direct current voltage, and when the R1 is 1.4M Ω, the R2 is 100M Ω, the PMOS threshold voltage vgs (th) is-1V, and the power supply VDD is 1.2V, the average power consumption is only 64 nA.

In the frequency duty cycle adjusting module, the output VOD1 of the LX01-C is connected with the input of the frequency divider, and the frequency divider module can increase the period of the waveform generated by the LX04 oscillator. The frequency divider has two outputs a and b, the logic of the outputs a and b is just opposite, wherein a is directly connected with the input a of a NOR gate of the delay adding module, b is connected with an RC delay circuit formed by R3 and C1, the signal of the path b is delayed, the anode of C1 is connected with the other input b of the NOR gate, the NOR gate outputs the two signals after completing NOR operation, and the duty ratio of the output signal can be adjusted by adjusting the parameter of the RC delay circuit.

In the trigger module, the output OUT of the frequency duty ratio regulation module is connected with the input end of the LX01 voltage detection circuit, the output VOD2 of the frequency duty ratio regulation module is connected with the grid electrode of NMOS-Q2 through a pull-up resistor, the drain electrode of the NMOS-Q2 is connected with VDD2, the source electrode of the NMOS-Q2 is connected with the input end of power supply management, and the voltage of the VDD2 is selected according to the requirements of loads.

As shown in FIG. 1, the invention comprises an LX04 low frequency oscillator, a frequency duty cycle adjustment module and a trigger module.

The LX04 ultra-low power consumption low-frequency oscillator is mainly composed of three or more LX01 passive voltage detection chips, and fig. 1 illustrates three LX01 voltage detection chips as an example. When the voltage of Vin is lower than the threshold VTH of the LX01 voltage detection circuit, the output is in a high-impedance state, the output of LX01 is kept at a high level, when the voltage of Vin is higher than the threshold VTH of the LX01 voltage detection circuit, the output is pulled to GND, the output of LX01 voltage detection circuit transitions to a low level, and the voltage of Vin is kept lower than the falling threshold VTL of the LX01 voltage detection circuit, and a signal diagram thereof is shown in fig. 2. The output of the LX01-A is connected with the input of the LX01-B through a pull-up resistor R1, the output of the LX01-B is connected with the input of the LX01-C through a pull-up resistor R2, and is also connected with the grid of a PMOS tube Q1, when the LX01-B outputs a high level, the PMOS-Q1 is in a high-impedance state, and when the output level is low, the PMOS-Q1 is conducted. The output of the LX01-C is connected with the input of the LX01-A, the source of the PMOS transistor Q1 is connected with the power supply VDD1, and the drain is connected with the output VOD of the LX 01-C. The PMOS-Q1 is complementary with the on and high-resistance states of the LX01-C, when the output of the LX01-C is in a high-resistance state, the PMOS-Q1 is in an on state, and when the output of the LX01-C is grounded, the PMOS-Q1 is in a high-resistance state, so that the leakage current of a system is reduced, and the waveform of an output signal is ensured to a certain extent. The module can generate an alternating current signal with a fixed period under a certain direct current voltage, the frequency of the alternating current signal is influenced by resistance values of R1 and R2, and the frequency of the signal is reduced when the resistance value is increased. To reduce the leakage current in the on state of LX01, a large resistance resistor is usually selected. When R1 is 2M Ω and R2 is 100M Ω, the average power consumption of the module is only 64nA when the PMOS threshold voltage vgs (th) is-1V and the power supply VDD1 is 1.2V.

In the frequency duty ratio adjusting module, the frequency divider is used for controlling the duration of a period and is determined by the number of bits of the frequency divider. The outputs a, b of the frequency divider have opposite logics, wherein the output a of the frequency divider is connected with the input interface a of the nor gate, the output b of the frequency divider is connected with the RC delay circuit, the anode of the capacitor C1 is connected with the input interface b of the nor gate, and the duty ratio of the periodic signal, namely the ratio of the activated load to the dead time, is controlled by adjusting the values of a resistor R3 and a capacitor C1 in the RC delay circuit. The power supply of the LX04 ultra-low power consumption low-frequency oscillator and the frequency duty cycle adjusting module is supplied by low-voltage VDD 1.

In the trigger module, the output OUT of the NOR gate is connected with the input end Vin of the LX01-D voltage detection circuit, the output VOD2 of the LX01-D is connected with the grid of the PMOS tube Q2 through the pull-up resistor R2, the source is connected with the VDD2, the drain is connected with the input Vin of power management, the voltage of the VDD2 is not adjusted and is not suitable for being used as the power supply of a load, therefore, the VDD2 is subjected to direct current conversion through the power management unit and is converted into the power supply suitable for the load, and the output VDD3 of the power management module is connected with the positive electrode of the load. When the LX01-D output VOD2 is low, the PMOS-Q2 is conducted, the VDD2 is converted into the voltage VDD3 required by the load through power management, the load system is activated, when the LX01-D output is high, the PMOS-Q2 is disconnected, the power management output VDD3 is 0V, and the load enters a shutdown state.

FIG. 3 is a logic timing diagram of the circuit of the present invention showing the timing relationship between the output signal VOD1 of LX04, the signals div _ a, div _ b of the divider outputs a, b, the signal nor of the NOR gate output OUT, and the output signal VOD2 of LX 01-D. The divider multiple selected in the figure is 1/8, and divides the frequency of the signal output by LX 04. div _ b and div _ a are opposite in logic, and the rising edge and the falling edge of the signal div _ b are lengthened and smoothed by the delay circuit formed by R3 and C1, so that the nor signal nor generates a high-level pulse in the rising edge stage of the div _ b. LX01-D inverts the logic of nor, which outputs VOD2 as shown in FIG. 3.