阅读说明：本技术 一种基于电力边缘网关的动态存储缓冲区读取控制方法 (Dynamic storage buffer area reading control method based on power edge gateway ) 是由 李澄 李春鹏 徐妍 宋庆武 单华 李军 于 2020-05-14 设计创作，主要内容包括：本发明公开了一种基于电力边缘网关的动态存储缓冲区及读取控制方法,涉及数据存储、超级计算、信息系统等领域,具体包含DDR数据使用模块和DDR数据传输模块,所述DDR数据传输模块包含读请求FIFO、DDR读控制器、DDR存储器、读数据FIFO；所述DDR数据使用模块包含DDR读请求产生模块、DDR数据使用端和计数模块；本发明提出的动态存储缓冲区读取控制方法,利用计数模块和两个缓存FIFO,通过比较计数模块的计数值和读请求数据量,有效实现了对DDR存储器的缓存数据的动态读取,避免了数据的溢出和读数据FIFO的存储拥塞。(The invention discloses a dynamic storage buffer area based on a power edge gateway and a reading control method, which relate to the fields of data storage, super calculation, information systems and the like, and particularly comprise a DDR data use module and a DDR data transmission module, wherein the DDR data transmission module comprises a reading request FIFO, a DDR reading controller, a DDR memory and a reading data FIFO; the DDR data use module comprises a DDR read request generation module, a DDR data use end and a counting module; the dynamic storage buffer area reading control method provided by the invention utilizes the counting module and the two buffer FIFO modules, and effectively realizes the dynamic reading of the buffer data of the DDR memory by comparing the counting value of the counting module with the reading request data volume, thereby avoiding the overflow of the data and the storage congestion of the reading data FIFO.)

1. A dynamic storage buffer area based on a power edge gateway is characterized in that: the DDR data transmission module comprises a read request FIFO, a DDR read controller, a DDR memory and a read data FIFO;

the DDR data use module comprises a DDR read request generation module, a DDR data use end and a counting module;

the DDR read request generation module is respectively connected with the read request FIFO and the counting module, the output end of the read request FIFO is connected with the input end of the DDR read controller, the output end of the DDR read controller is connected with the input end of the DDR memory, the output end of the DDR memory is connected with the input end of the read data FIFO, the read data FIFO is connected with the DDR data using end, and the output end of the DDR data using end is connected with the input end of the counting module.

2. A dynamic storage buffer reading control method based on the power edge gateway of claim 1, characterized in that: the method specifically comprises the following steps;

the counting value M of the counting module is set as the storage capacity of a read data FIFO initially, and when the DDR read request generation module has a read data requirement, the DDR read request generation module firstly detects whether the read request FIFO is a FULL FIFO FULL signal; if the read request FIFO is full, the DDR read request generation module continues to wait, if the read request FIFO is not full, the DDR read request generation module continues to check whether the count value M of the counting module is greater than or equal to the current read request data volume X, if the count value M of the counting module is smaller than the current read request data volume X, the DDR read request generation module continues to wait, and if the count value M of the counting module is greater than or equal to the current read request data volume X, the DDR read request generation module sends write enable to the read request FIFO and simultaneously sends the current read request data volume X to the read request FIFO and the counting module.

3. The dynamic memory buffer read control method of claim 2, wherein: the counting module can receive a read request data volume X from the DDR read request generation module and a read data volume Y from the DDR data using end, and when the counting module receives the read request data volume X from the DDR read request generation module, the counting module enables a counting value M = M-X; when the counting module receives the data reading quantity Y of the DDR data using end, enabling the counting value M of the counting module to = M + Y; if the counting module receives the read request data volume X and the read data volume Y at the same time, the read data volume Y from the DDR data using end is received first, the counting value M of the counting module is enabled to = M + Y, and then the counting value M of the counting module is enabled to = M-X in response to the read request data volume X from the DDR read request generating module.

4. The dynamic memory buffer read control method of claim 2, wherein: the read request FIFO sends a read data request to the DDR read controller, the DDR read controller sends DDR read control information to the DDR memory, and the DDR memory sends read data to the read data FIFO after receiving the read control information; the DDR data using end judges data FIFO empty information according to the current data using requirement, if the data FIFO is empty, the DDR data using end waits, and if the data FIFO is not empty, the DDR data using end sends data FIFO read enable to the data FIFO; the data FIFO sends read data to the DDR data using end after receiving the data FIFO read enabling request, and simultaneously records the read data quantity Y; and the DDR data using end sends the read data volume Y to the counting module after receiving the read data.

Technical Field

The invention relates to the field of electrical engineering science, in particular to the fields of data storage, super computing, information systems and the like, and particularly relates to a dynamic storage buffer area reading control method based on a power edge gateway.

Background

With the rapid development of information technology, how to realize the efficient storage of large-capacity data gradually becomes a problem to be solved urgently. The DDR memory uses an advanced synchronous circuit, so that the main steps of transmission and output of the designated address and data are independently executed and are kept in complete synchronization with the CPU. Meanwhile, a DLL (Delay Locked Loop) technology is used, when data is valid, the memory controller can use the data filtering signal to accurately locate the data, the speed of the SDRAM can be doubled essentially without increasing the clock frequency, and the data can be read at the rising edge and the falling edge of the clock pulse, so that the speed is twice that of the standard SDRAM.

Although the DDR memory has a fast transmission rate and low power consumption, the data reading characteristic is that there is a certain delay, and data is not returned immediately after a read request is sent, which requires a certain clock cycle delay. Certain uncertainty exists in the transmission process, data is easy to overflow, and the situation of reading error of the data can be caused, so that the reading efficiency of the DDR is reduced.

Disclosure of Invention

In view of the above-mentioned defects of the prior art, the technical problem to be solved by the present invention is to avoid the channel blockage of the data storage buffer, and to improve the efficiency of the pipeline structure by using a counting method. The method disclosed by the invention separates the command request from the read data, and effectively realizes the dynamic reading of the data volume by using the counting module and the two cache FIFOs, thereby improving the working efficiency of the DDR.

A read control method of a dynamic memory buffer area is based on a DDR data use module and a DDR data transmission module, wherein the DDR data transmission module comprises a read request FIFO, a DDR read controller, a DDR memory and a read data FIFO, the DDR data use module comprises a DDR read request generation module, a DDR data use end and a counting module, a counting value M of the counting module is initially set as the memory capacity of the read data FIFO, when the DDR read request generation module has a read data requirement, the DDR read request generation module firstly detects whether the read request FIFO is a FULL FIFO FULL signal, if the read request FIFO is FULL, the DDR read request generation module continues to wait, if the read request FIFO is not FULL, the DDR read request generation module continues to detect whether the counting value M of the counting module is more than or equal to the current read request data volume X, if the DDR read request FIFO is less than the current read request data volume X, if the DDR read request generation module continues to wait, if the DDR read request generation module is more than or equal to the read, and simultaneously sends the current amount of read request data X to the read request FIFO and the counting module.

A read control method for a dynamic memory buffer area is characterized in that a counting module can receive a read request data volume X from a DDR read request generation module and a read data volume Y from a DDR data using end, and when the counting module receives the read request data volume X from the DDR read request generation module, the counting module enables a counting value M = M-X; when the counting module receives the data reading quantity Y of the DDR data using end, enabling the counting value M of the counting module to = M + Y; if the counting module receives the read request data volume X and the read data volume Y at the same time, the read data volume Y from the DDR data using end is received first, the counting value M = M + Y of the counting module is enabled, and then the counting value M = M-X of the counting module is enabled to respond to the read request data volume X from the DDR read request generating module.

A read control method of a dynamic memory buffer area is characterized in that a read request FIFO sends a read data request to a DDR read controller, the DDR read controller sends DDR read control information to a DDR memory, and the DDR memory sends read data to the read data FIFO after receiving the read control information; the DDR data using end firstly judges the empty information of the data FIFO according to the current data using requirement, if the data FIFO is empty, the DDR data using end waits, and if the data FIFO is not empty, the DDR data using end sends data FIFO reading enable to the data FIFO; the data FIFO sends read data to the DDR data using end after receiving the data FIFO read enabling request, and simultaneously records the read data quantity Y; and sending the read data quantity Y to the counting module after the DDR data use end data.

Compared with the prior art, the invention adopting the technical scheme has the following technical effects:

the invention provides a read control method of a dynamic storage buffer area, which separates a request data command from obtained request data, utilizes a counting module and two cache FIFOs, and effectively realizes the dynamic reading of the cache data of a DDR memory by comparing the counting value of the counting module with the read request data volume, thereby avoiding the overflow of the data and the storage congestion of the read data FIFO.

Drawings

FIG. 1 is a system block diagram of the present invention;

FIG. 2 is a flow diagram of read request generation of the present invention;

FIG. 3 is a reference timing diagram according to an embodiment of the present invention.

Detailed Description

In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular internal procedures, techniques, etc. in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.

The invention discloses a dynamic storage buffer area reading control method based on a power edge gateway. In the DDR data use module, a DDR read request generation module gives a FIFO write enable signal and a data volume to a read request FIFO according to a request FIFO FULL signal given by the read request FIFO in the DDR data transmission module and a current count value M of a counting module, and the data volume is assumed to be X, and the X is sent to the counting module. In the DDR data transmission module, the DDR controller analyzes the read data from the read request FIFO and sends the read control related information to the DDR memory. After K clocks, the DDR memory gives out the read data and sends the read data to the read data FIFO buffer. And at the DDR data using end, reading enabling of the data FIFO is given according to a data FIFO empty signal given by a read data FIFO of the DDR data transmission module. And the data volume Y read by the DDR data using end can be obtained according to the read data or the enabled effective clock period, the Y is sent to the counting module, and the read data is used by the lower module. In the counting module, the initial value M of the counting module is the storage capacity of the read data FIFO. When X is received, M = M-X; upon receipt of Y, M = M + Y; when receiving X and Y at the same time, firstly performing M = M + Y, and then performing M = M-X.

The dynamic storage buffer area reading control method provided by the invention utilizes the counting module and the two buffer FIFO modules, and effectively realizes the dynamic reading of the buffer data of the DDR memory by comparing the counting value of the counting module with the reading request data volume, thereby avoiding the overflow of the data and the storage congestion of the reading data FIFO.

Referring to fig. 1, it is a system block diagram of the present invention. The DDR data transmission device mainly comprises a DDR data use module and a DDR data transmission module. The DDR data use module comprises three sub-modules which are respectively a DDR read request generation module, a counting module and a DDR data use end; the DDR data transmission module comprises 4 sub-modules which are respectively a read request FIFO, a read data FIFO, a DDR read controller and a DDR memory.

First, the initial count value M of the counting module is set to the storage capacity value of the read data FIFO. Referring to fig. 2, the DDR read request generation module first determines whether the read request FIFO is FULL according to the request FIFO FULL signal output by the read request FIFO. If it is full, a wait is made without generating the associated enable signal and data. If not, continuously judging whether the data volume X of the current request is less than or equal to the counting value M of the counting module, if so, giving a request FIFO write enable signal and read request data of the read request FIFO and giving the request data volume X to the counting module by the DDR read request generation module. Otherwise, the module continues to wait.

The DDR reads the controller and analyzes the data from reading the request FIFO, give the relevant read control information of DDR memorizer, mainly include: read command, read address, read enable signal. And after receiving a group of read control signals given by the DDR read controller, the DDR memory outputs read data through the delay of K clocks. The read data FIFO buffers the data output by the DDR memory at the current stage. The DDR data use end judges whether the FIFO is empty or not according to a data FIFO empty signal given by the data reading FIFO. If the data is empty, the DDR data consumer waits. If not, a data FIFO read enable signal is presented to the read data FIFO. The read data FIFO receives the enable signal, and then provides the read data and records the read data amount Y. After receiving the read data, the DDR data use terminal sends a read data volume Y to the counting module and sends the read data to the lower module.

For the counting module, after receiving the data quantity X of the request removal given by the DDR read request module, the counting module performs M = M-X operation; after the counting module receives the read data quantity Y from the DDR data use module, performing M = M + Y operation; if X and Y are received simultaneously, responding to the read data volume Y of the DDR data using end firstly to enable the count value M = M + Y, and then responding to the read request data volume X of the DDR data request module to enable the count value M = M-X;