阅读说明：本技术 半导体器件及其制作方法 (Semiconductor device and method for manufacturing the same ) 是由 刘俊文 于 2020-07-31 设计创作，主要内容包括：本申请公开了一种半导体器件及其制作方法,涉及半导体制造领域。该半导体器件至少包括衬底；衬底内设置有第一阱区、第二阱区、第一类重掺杂区以及第二类重掺杂区；第一类重掺杂区和第二类重掺杂区位于衬底的顶部,第二阱区内设置有第一类重掺杂区和第二类重掺杂区；衬底上的寄生三极管区域设置有若干个辅助栅,任意一个辅助栅横跨位于第一类重掺杂区和第二类重掺杂区之间的N个第一类浅沟槽隔离,N为大于等于2的整数；第一类浅沟槽隔离的深度小于衬底中第二类浅沟槽隔离的深度；解决了目前寄生三极管性能一般的问题；达到了提升寄生三极管的性能,有助于扩展寄生三极管的使用范围的效果。(The application discloses a semiconductor device and a manufacturing method thereof, and relates to the field of semiconductor manufacturing. The semiconductor device includes at least a substrate; a first well region, a second well region, a first heavy doping region and a second heavy doping region are arranged in the substrate; the first heavily doped region and the second heavily doped region are positioned at the top of the substrate, and the first heavily doped region and the second heavily doped region are arranged in the second well region; a parasitic triode region on the substrate is provided with a plurality of auxiliary gates, any one auxiliary gate crosses N first-class shallow trench isolations between the first-class heavy doping region and the second-class heavy doping region, and N is an integer greater than or equal to 2; the depth of the first shallow trench isolation is smaller than that of the second shallow trench isolation in the substrate; the problem that the performance of the parasitic triode is general at present is solved; the performance of the parasitic triode is improved, and the effect of expanding the application range of the parasitic triode is facilitated.)

1. A semiconductor device, characterized by comprising at least a substrate;

a first well region, a second well region, a first heavy doping region and a second heavy doping region are arranged in the substrate;

the first well region and the first heavily doped region have a first conductivity type, the second well region and the second heavily doped region have a second conductivity type, and the first conductivity type is opposite to the second conductivity type;

the first heavily doped region and the second heavily doped region are positioned at the top of the substrate, and the first heavily doped region and the second heavily doped region are arranged in the second well region;

a parasitic triode region on the substrate is provided with a plurality of auxiliary gates, any one auxiliary gate crosses N first-class shallow trench isolations between the first-class heavily doped region and the second-class heavily doped region, and N is an integer greater than or equal to 2;

the depth of the first shallow trench isolation is smaller than that of the second shallow trench isolation in the substrate.

2. The semiconductor device of claim 1, wherein the first type of shallow trench isolation and the second type of shallow trench isolation are formed in a same process.

3. The semiconductor device according to claim 1, wherein the first conductivity type is an N-type, and the second conductivity type is a P-type;

or the first conduction type is P type, and the second conduction type is N type.

4. A method of fabricating a semiconductor device, the method comprising:

forming a first well region and a second well region in a substrate, the first well region having a first conductivity type and the second well region having a second conductivity type, the first conductivity type being opposite to the second conductivity type;

forming a first shallow trench isolation and a second shallow trench isolation in the substrate, wherein the depth of the first shallow trench isolation is smaller than that of the second shallow trench isolation, and the first shallow trench isolation is positioned between the second shallow trench isolations;

forming a plurality of auxiliary gates on the surface of the substrate, wherein any auxiliary gate spans N first-type shallow trench isolations, and N is an integer greater than or equal to 2;

forming a first type heavily doped region and a second type heavily doped region on the top of the substrate;

the auxiliary gate is positioned above the parasitic triode region, and the first heavily doped region and the second heavily doped region are arranged in the substrate on two sides of any one auxiliary gate.

5. The method of claim 4, wherein the forming the first type heavily doped region and the second type heavily doped region on top of the substrate comprises:

forming a first type heavily doped region and a second type heavily doped region on the top of the substrate through an ion implantation process;

and in the region where the parasitic triode is formed, the auxiliary gate is used as a self-aligned barrier layer.

6. The method of claim 4, wherein the forming a first type of shallow trench isolation and a second type of shallow trench isolation in the substrate comprises:

defining a first type of groove opening pattern and a second type of groove opening pattern on the surface of the substrate through a photoetching process, wherein the opening size of the first type of groove opening pattern is smaller than that of the second type of groove opening pattern;

etching the substrate according to the first type groove opening pattern and the second type groove opening pattern to form a first type groove and a second type groove, wherein the depth of the first type groove is smaller than that of the second type groove;

and filling the first type of groove and the second type of groove to form the first type of shallow groove isolation and the second type of shallow groove isolation.

7. The method of claim 6, wherein forming a plurality of auxiliary gates on the surface of the substrate comprises:

forming a polycrystalline silicon layer on the surface of the substrate;

and etching the polysilicon layer to form a plurality of auxiliary gates.

8. The method of claim 6, wherein forming the first well region and the second well region in the substrate comprises:

forming the first well region and the second well region in the substrate by an ion implantation process.

Technical Field

The application relates to the field of semiconductor manufacturing, in particular to a semiconductor device and a manufacturing method thereof.

Background

In a semiconductor device structure manufactured by adopting a CMOS manufacturing process, a parasitic triode formed by a source region, a well region and an epitaxial layer is inherent. Such as: the PNP type parasitic triode is composed of the P type epitaxial layer, the N type well region and the P type source region, and the NPN type parasitic triode is composed of the N type epitaxial layer, the P type well region and the N type source region.

Although it is usually necessary to avoid the effect of the parasitic transistor on its performance, the parasitic transistor is also used in some integrated circuit designs. The triode is parasitic, so that no additional process step is needed to optimize the performance of the triode, and the performance of the parasitic triode is general, so that the use of the parasitic triode and the design of part of circuits are limited.

Disclosure of Invention

To solve the problems in the related art, the present application provides a semiconductor device and a method of fabricating the same. The technical scheme is as follows:

in a first aspect, embodiments of the present application provide a semiconductor device, including at least a substrate;

a first well region, a second well region, a first heavy doping region and a second heavy doping region are arranged in the substrate;

the first well region and the first-class heavily doped region are of a first conductivity type, the second well region and the second-class heavily doped region are of a second conductivity type, and the first conductivity type is opposite to the second conductivity type;

the first heavily doped region and the second heavily doped region are positioned at the top of the substrate, and the first heavily doped region and the second heavily doped region are arranged in the second well region;

a parasitic triode region on the substrate is provided with a plurality of auxiliary gates, any one auxiliary gate crosses N first-class shallow trench isolations between the first-class heavy doping region and the second-class heavy doping region, and N is an integer greater than or equal to 2;

the depth of the first type of shallow trench isolation is less than the depth of the second type of shallow trench isolation in the substrate.

Optionally, the first type of shallow trench isolation and the second type of shallow trench isolation are formed in the same process.

Optionally, the first conductivity type is N-type, and the second conductivity type is P-type;

or the first conduction type is P type, and the second conduction type is N type.

In a second aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device, where the method includes:

forming a first well region and a second well region in the substrate, the first well region having a first conductivity type, the second well region having a second conductivity type, the first conductivity type being opposite to the second conductivity type;

forming a first shallow trench isolation and a second shallow trench isolation in the substrate, wherein the depth of the first shallow trench isolation is smaller than that of the second shallow trench isolation, and the first shallow trench isolation is positioned between the second shallow trench isolations;

forming a plurality of auxiliary gates on the surface of the substrate, wherein any auxiliary gate spans N first-type shallow trench isolations, and N is an integer greater than or equal to 2;

forming a first type heavily doped region and a second type heavily doped region on the top of the substrate;

the auxiliary gate is positioned above the parasitic triode region, and a first type heavily doped region and a second type heavily doped region are arranged in the substrate on two sides of any one auxiliary gate.

Optionally, forming a first type heavily doped region and a second type heavily doped region on the top of the substrate includes:

forming a first type heavily doped region and a second type heavily doped region on the top of the substrate through an ion implantation process;

wherein, in the area where the parasitic triode is formed, the auxiliary gate is used as a self-aligned barrier layer.

Optionally, forming a first type of shallow trench isolation and a second type of shallow trench isolation in the substrate includes:

defining a first type of groove opening pattern and a second type of groove opening pattern on the surface of the substrate through a photoetching process, wherein the opening size of the first type of groove opening pattern is smaller than that of the second type of groove opening pattern;

etching the substrate according to the first type groove opening pattern and the second type groove opening pattern to form a first type groove and a second type groove, wherein the depth of the first type groove is smaller than that of the second type groove;

and filling the first type of groove and the second type of groove to form the first type of shallow trench isolation and the second type of shallow trench isolation.

Optionally, forming a plurality of auxiliary gates on the substrate surface includes:

forming a polycrystalline silicon layer on the surface of the substrate;

and etching the polysilicon layer to form a plurality of auxiliary gates.

Optionally, forming a first well region and a second well region in the substrate includes:

the first well region and the second well region are formed in the substrate by an ion implantation process.

The technical scheme at least comprises the following advantages:

forming a first well region and a second well region in a substrate, forming first shallow trench isolations and second shallow trench isolations with different depths in the substrate, forming a plurality of auxiliary gates on the surface of the substrate, wherein any one auxiliary gate crosses N first shallow trench isolations, and forming a first heavily doped region and a second heavily doped region on the top of the substrate; the problem that the performance of the parasitic triode is general at present is solved; the performance of the parasitic triode is improved, and the effect of expanding the application range of the parasitic triode is facilitated.

Drawings

In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a top view of a conventional semiconductor device;

fig. 2 is a structural sectional view of a conventional semiconductor device;

fig. 3 is a schematic structural diagram of a semiconductor device provided in an embodiment of the present application;

fig. 4 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

fig. 5 is a schematic implementation diagram of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

fig. 6 is an implementation schematic diagram of a manufacturing method of a semiconductor device according to an embodiment of the present application.

Detailed Description

The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.

Taking a conventional semiconductor device for forming a PNP parasitic transistor as an example, fig. 1 shows a top view of the semiconductor device, and fig. 2 shows a cross-sectional view of the semiconductor device corresponding to fig. 1, as shown in fig. 1 and fig. 2, the conventional semiconductor device includes a substrate 10, a P-type well region 11, an N-type well region (NWELL)12, a P + region 13, an N + region 14, and a shallow trench isolation 16 disposed between the N + region 14 and the P + region 13 are provided in the substrate 10. In the semiconductor device shown in fig. 1 and 2, the P-type well region 11 serves as a Collector (Collector) of a parasitic transistor, the N + region 14 in the N-type well region 12 serves as a Base (Base) of the parasitic transistor, and the P + region 13 in the N-type well region 12 serves as an Emitter (Emitter) of the parasitic transistor. At present, the emitter-base-collector channel of the parasitic triode is long, and the performance of the parasitic triode is influenced.

In order to solve the general performance problem of the parasitic triode at present, an embodiment of the present application provides a structural schematic of a semiconductor device, as shown in fig. 3, the semiconductor device at least includes:

the semiconductor device comprises a substrate 31, wherein a first well region 32, a second well region 33, a first type heavily doped region 34 and a second type heavily doped region 35 are arranged in the substrate 31.

The first well region 32 and the first heavily doped region of the type 34 have a first conductivity type and the second well region 33 and the second heavily doped region of the type 35 have a second conductivity type, the first conductivity type being opposite to the second conductivity type.

The first heavily doped region 34 and the second heavily doped region 35 are located on the top of the substrate 31, the first heavily doped region 34 and the second heavily doped region 35 are arranged in the second well region 33, and the first heavily doped region 34 is arranged in the first well region 32.

The second heavily doped region 35 in the second well region 33 serves as a base (B) of the parasitic transistor, the first heavily doped region 34 in the second well region 33 serves as an emitter (E) of the parasitic transistor, and the first heavily doped region 34 in the first well region 32 serves as a collector (C) of the parasitic transistor.

The parasitic triode region on the substrate 31 is provided with a plurality of auxiliary gates 38, and any one auxiliary gate 38 spans the N first-type shallow trench isolations 36 between the first-type heavily doped region 34 and the second-type heavily doped region 35.

N is an integer of 2 or more.

The N first-type shallow trench isolations 36 are arranged at intervals between the first-type heavily doped region 34 and the second-type heavily doped region 35. The first type shallow trench isolation is used for separating the first type heavily doped region and the second type heavily doped region.

In one example, as shown in fig. 3, any one of the auxiliary gates 38 in the semiconductor device crosses 2 shallow trench isolations 36 of the first kind between the heavily doped region 34 of the first kind and the heavily doped region 35 of the second kind.

The substrate between the N first-type shallow trench isolations 36 is covered with an auxiliary gate, which is not lead out.

The first type of shallow trench isolation is located in a parasitic triode region in the substrate.

A second type of shallow trench isolation 37 is also provided in the substrate 31.

The depth of the first type of shallow trench isolation 36 is less than the depth of the second type of shallow trench isolation 37 in the substrate.

The second type of shallow trench isolation 37 is not located in the parasitic triode region in the substrate.

As can be seen from fig. 3, the length of the channel between the emitter and the base of the parasitic triode in the semiconductor device provided by the embodiment of the present application is reduced compared with the length of the channel of the parasitic triode in the existing semiconductor device, so as to achieve the effect of improving the performance of the parasitic triode.

In an alternative embodiment based on the embodiment shown in fig. 3, the first type of shallow trench isolation and the second type of shallow trench isolation are formed in the same process.

When the groove required by the shallow groove isolation is etched on the substrate, the groove required by the first type of shallow groove isolation and the groove required by the second type of shallow groove isolation are etched simultaneously.

In an alternative embodiment based on the embodiment shown in fig. 3, the first conductivity type is P-type and the second conductivity type is N-type; or the first conductive type is N type, and the second conductive type is P type.

According to different conduction types, the parasitic triode is NPN type or PNP type.

Referring to fig. 4, a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present application is shown, where the method at least includes the following steps:

step 401 forms a first well region and a second well region in a substrate.

The first well region has a first conductivity type, the second well region has a second conductivity type, and the first conductivity type is opposite to the second conductivity type.

Step 402, forming a first type of shallow trench isolation and a second type of shallow trench isolation in a substrate.

The depth of the first type of shallow trench isolation is smaller than that of the second type of shallow trench isolation, and the first type of shallow trench isolation is positioned between the second type of shallow trench isolation.

The first type of shallow trench isolation is arranged at intervals between the second type of shallow trench isolation.

As shown in fig. 5, a first well region 32 and a second well region 33 are formed on a substrate 31, and a first shallow trench isolation 36 and a second shallow trench isolation 37 are formed in the substrate.

And 403, forming a plurality of auxiliary gates on the surface of the substrate, wherein any auxiliary gate crosses the N first-type shallow trench isolations.

N is an integer of 2 or more.

In one example, as shown in fig. 6, 1 auxiliary gate 38 spans 2 shallow trench isolations of the first type 36.

It should be noted that the number of N is determined according to actual situations, and is not limited in the embodiments of the present application.

In the subsequent process steps, the auxiliary gate crossing the first type of shallow trench isolation is not led out, and the auxiliary gate is not removed.

At step 404, a first type heavily doped region and a second type doped region are formed on top of the substrate.

In one example, as shown in fig. 3, a first type heavily doped region 34 and a second type doped region 35 are formed on top of the substrate 31.

A first type heavily doped region 34 and a second type heavily doped region 35 are disposed in the second well region 33, and a first type heavily doped region 34 is disposed in the first well region 32. The second heavily doped region 35 in the second well region 33 serves as a base (B) of the parasitic transistor, the first heavily doped region 34 in the second well region 33 serves as an emitter (E) of the parasitic transistor, and the first heavily doped region 34 in the first well region 32 serves as a collector (C) of the parasitic transistor.

In the semiconductor device, the auxiliary gate 38 is located above the parasitic triode region, and the first heavily doped region 34 and the second heavily doped region 35 are arranged in the substrate on both sides of any one auxiliary gate 38.

In summary, in the manufacturing method of the semiconductor device provided in the embodiment of the present application, the first well region and the second well region are formed in the substrate, the first shallow trench isolations and the second shallow trench isolations with different depths are formed in the substrate, the plurality of auxiliary gates are formed on the surface of the substrate, any one of the auxiliary gates crosses over the N first shallow trench isolations, and the first heavily doped region and the second heavily doped region are formed on the top of the substrate; the problem that the performance of the parasitic triode is general at present is solved; the performance of the parasitic triode is improved, and the effect of expanding the application range of the parasitic triode is facilitated.

In an alternative embodiment based on the embodiment shown in fig. 4, the step 404, i.e. the step of "forming the first type heavily doped region and the second type heavily doped region on top of the substrate" can be implemented as follows:

and forming a first type heavily doped region and a second type heavily doped region on the top of the substrate by an ion implantation process.

When the ion implantation process is carried out, the auxiliary gate is used as a self-aligned barrier layer in the region where the parasitic triode is formed.

In an alternative embodiment based on the embodiment shown in fig. 4, the step 402, that is, the step "forming the first type shallow trench isolation and the second type shallow trench isolation in the substrate", may be implemented by the following steps:

step 4021, defining a first type of groove opening pattern and a second type of groove opening pattern on the surface of the substrate through a photoetching process, wherein the opening size of the first type of groove opening pattern is smaller than that of the second type of groove opening pattern.

And coating photoresist on the surface of the substrate, exposing by using a mask plate containing a first type groove opening pattern and a second type groove opening pattern, and forming the first type groove opening pattern and the second type groove opening pattern on the surface of the substrate after developing.

Step 4022, etching the substrate according to the first type groove opening pattern and the second type groove opening pattern to form a first type groove and a second type groove, wherein the depth of the first type groove is smaller than that of the second type groove.

According to the inherent characteristics of the etching process, the depth of the groove with small opening size can be shallow, so that after the etching is finished, the depth of the first type groove is smaller than that of the second type groove.

Step 4023, filling the first type of groove and the second type of groove to form a first type of shallow groove isolation and a second type of shallow groove isolation.

Optionally, depositing polycrystalline silicon, filling the first type of trench and the second type of trench with the polycrystalline silicon, removing the polycrystalline silicon on the surface of the substrate after filling, and forming the first type of shallow trench isolation and the second type of shallow trench isolation in the substrate, wherein the depth of the first type of shallow trench isolation is smaller than that of the second type of shallow trench isolation.

In an alternative embodiment based on fig. 4, the step 403, that is, the step of "forming a plurality of auxiliary gates on the surface of the substrate", may be implemented by the following steps:

4031, a polysilicon layer is formed on the surface of the substrate.

And depositing a layer of polysilicon on the surface of the substrate to form a polysilicon layer.

4032, the polysilicon layer is etched to form a plurality of auxiliary gates.

Optionally, an auxiliary gate pattern is defined on the surface of the substrate, the position of the auxiliary gate pattern is located in a region where a parasitic triode is to be formed, and the polysilicon layer is etched according to the defined auxiliary gate pattern to form an auxiliary gate.

In an alternative embodiment based on the embodiment shown in fig. 4, the step 401, i.e. the step of "forming the first well region and the second well region in the substrate", can be implemented as follows:

the first well region and the second well region are formed in the substrate by an ion implantation process.

A first well region and a second well region are formed in a predetermined region of a substrate by implanting ions of different conductivity types, respectively.

It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.