阅读说明：本技术 基于fpga的高分辨率视频图像压缩传输方法及系统 (High-resolution video image compression transmission method and system based on FPGA ) 是由 孙风雷 于 2020-07-01 设计创作，主要内容包括：基于FPGA的高分辨率视频图像压缩传输方法和系统。方法包括：获取视频数据流至FPGA,通过色域转换得到YCbCr4:4:4格式,循环向16个视频行缓存RAM写入,8个RAM为1组,分为2组,每写完一组RAM后,从左向右依次读取数据,每次读取8列,形成8X8的图像数据块,直到将整组数据读取完；对8x8图像数据块依次进行DCT变换、ZIGZAG扫描、量化、RLE游程编码以及哈夫曼编码,直到将8行数据按照8x8图像数据块全部处理完,若最后一块不足8个像素的点则对应补齐；直到整帧图像处理结束,完成压缩。系统包括FPGA,FPGA包括：视频数据流输入、写RAM控制、视频缓存RAM、8*8块产生、DCT、ZIGZAG扫描、量化、RLE游程编码、哈夫曼编码等。只用单个FPGA实现高分辨率视频图像压缩,极大减小数据量。(High-resolution video image compression and transmission method and system based on FPGA. The method comprises the following steps: acquiring a video data stream to an FPGA (field programmable gate array), obtaining a YCbCr4:4:4 format through color gamut conversion, circularly writing into 16 video line cache RAMs, wherein 8 RAMs are 1 group and are divided into 2 groups, reading data from left to right sequentially after each group of RAM is written, reading 8 columns each time, and forming an 8X8 image data block until the whole group of data is read completely; performing DCT transformation, ZIGZAG scanning, quantization, RLE run-length coding and Huffman coding on an 8x8 image data block in sequence until 8 lines of data are completely processed according to an 8x8 image data block, and correspondingly filling if the last block is less than 8 pixels; and completing compression until the whole frame image processing is finished. The system comprises an FPGA, and the FPGA comprises: video data stream input, write RAM control, video buffer RAM, 8x8 block generation, DCT, ZIGZAG scanning, quantization, RLE run length coding, huffman coding, etc. And only a single FPGA is used for realizing high-resolution video image compression, so that the data volume is greatly reduced.)

1. The high-resolution video image compression transmission method based on the FPGA is characterized by comprising the following steps:

acquiring a video data stream to the FPGA through an interface of the FPGA, and judging the format of the video data stream:

if the format of the video data stream is YCbCr4:4:4, writing the video data stream into a video cache RAM of the FPGA;

if the format of the video data stream is not YCbCr4:4:4, obtaining the format of YCbCr4:4:4 through color gamut conversion, and writing the format into a video cache RAM of the FPGA; the video cache RAM comprises two groups of 8 RAMs, and each RAM is used for caching a line of video data stream data;

writing each line of video data stream data into two groups of RAMs in sequence and circularly, caching the two groups of RAMs according to ping-pong operation, reading the data in the 8 RAMs of the group at the same time after the first group of RAMs is written, reading 8 columns each time to form an 8x8 image data block for processing, and writing the newly-entered data cache into a second group of RAMs;

performing DCT transformation, ZIGZAG scanning, quantization, RLE run-length coding and Huffman coding on an 8x8 image data block in sequence until 8 rows of data are completely processed according to an 8x8 image data block, and if the last block is less than 8 rows, performing compensation on the last pixel points; and processing the 8 rows of data of the second group of RAM until the whole frame of image processing is finished, and finishing compression.

2. The FPGA-based high-resolution video image compression transmission method according to claim 1,

DCT transform, is used for carrying on the conversion from time domain to frequency domain to the video signal, obtain 8x8 coefficient matrix;

a ZIGZAG scan for converting the DCT-transformed 8x8 coefficient matrix into one-dimensional 1x64 coefficients in a predetermined arrangement order and sequentially outputting the coefficients;

quantizing the coefficients reordered by the ZIGZAG by using a quantization table, performing division operation on the coefficients and corresponding values in the quantization table, and quantizing the luminance signal and the color difference signal by using different quantization tables respectively;

RLE run-length coding is used for representing continuous '0' in the quantized coefficient data in a run-length mode, and outputting amplitude, run-length RRRR and classification SSSS;

huffman coding, which is used to maximize the amount of compressed video data based on the frequency of use.

3. The FPGA-based high-resolution video image compression transmission method according to claim 1,

DCT transformation, which is realized by table look-up:

presetting the coefficient value in a ROM of an FPGA, and then obtaining an operation result by inquiring an ROM address when performing DCT operation, so that an 8x8 image data block is converted into an 8x8 coefficient matrix; in the 8 × 8 coefficient matrix, the first system in the upper left corner is a direct current DC coefficient, and the remaining 63 are alternating current AC coefficients.

4. The FPGA-based high-resolution video image compression transmission method according to claim 1,

compressing the continuous '0' values in the quantized coefficients of an image data block, comprising the steps of:

counting the input coefficient value, and if the input coefficient is not '0', outputting an encoding result; if the input coefficient is '0', counting the number of continuous '0' and outputting another coding result according to the number of '0'; and counting the rest input coefficients according to the mode, and if the coefficients from the beginning to the last at a certain position are all continuous 0, outputting an end EOB mark and ending the coding.

5. The FPGA-based high-resolution video image compression transmission method according to claim 1,

huffman coding, comprising the steps of: presetting a Huffman coding table in a ROM of an FPGA, coding by inquiring the ROM address during coding, outputting the code length and code words, and outputting the coding result in sequence to form a compressed data stream;

during coding, different coding modes are adopted for a DC coefficient and an AC coefficient, and different coding modes are also adopted for the amplitude and the classification SSSS after RLE run length coding:

for the DC coefficient, the current DC coefficient is subtracted by the previous DC coefficient, and then the alternating coding of VLC variable length Huffman coding and VLI variable length integer coding is carried out;

alternating coding of VLC variable length Huffman coding and VLI variable length integer coding is directly adopted for the AC coefficient;

VLI variable length integer coding is adopted for the amplitude of RLE run length coding;

VLC variable length Huffman coding is adopted for the classification SSSS.

6. High resolution video image compression transmission system based on FPGA, including the FPGA who locates the integrated circuit board, its characterized in that, FPGA includes:

the video data stream input interface is used for acquiring a video data stream to the FPGA and judging whether the video data stream is in a YCbCr4:4:4 format or not;

the color gamut conversion module is used for converting the video data stream format into the YCbCr4:4:4 format when the video data stream input interface judges that the video data stream format is not the YCbCr4:4:4 format;

the video cache RAM comprises two groups of 8 RAMs, wherein each RAM is used for caching a line of video data stream data with the format of YCbCr4:4: 4;

the writing RAM control unit is used for writing each line of video data stream data into the two groups of RAMs in a circulating mode according to the sequence, and the two groups of RAMs perform cache writing according to ping-pong operation;

an 8 × 8 block generating unit, configured to generate 8 × 8 blocks of data and read data from a set of RAMs at the same time, 8 columns each time, thereby forming 8 × 8 blocks of image data until the data in the set of RAMs is completely read;

the DCT unit is used for converting a time domain into a frequency domain of the video signal to obtain an 8x8 coefficient matrix;

a ZIGZAG scanning unit for converting the DCT-transformed 8x8 coefficient matrix into one-dimensional 1x64 coefficients according to a predetermined arrangement sequence and sequentially outputting the coefficients;

the quantization unit is used for quantizing the coefficients reordered by the ZIGZAG by using a quantization table, dividing the coefficients by corresponding values in the quantization table, and quantizing the brightness signal and the color difference signal by using different quantization tables;

the RLE run-length coding unit is used for representing continuous '0' in the quantized coefficient data in a run-length mode and outputting amplitude, run-length RRRR and classification SSSS;

a Huffman coding unit for maximizing the amount of compressed video data according to the use frequency.

7. The FPGA-based high-resolution video image compression transmission method according to claim 6,

the DCT transformation unit is used for obtaining an operation result by inquiring the address of the ROM according to the coefficient value of the ROM preset in the FPGA when DCT operation is carried out, so that an 8x8 image data block is transformed into an 8x8 coefficient matrix; in the 8 × 8 coefficient matrix, the first system in the upper left corner is a direct current DC coefficient, and the remaining 63 are alternating current AC coefficients.

8. The FPGA-based high-resolution video image compression transmission method according to claim 6,

the RLE run-length coding unit is used for counting the input coefficient value and outputting a coding result if the input coefficient is not 0; if the input coefficient is '0', counting the number of continuous '0' and outputting another coding result according to the number of '0'; and counting the rest input coefficients according to the mode, and if the coefficients from the beginning to the last at a certain position are all continuous 0, outputting an end EOB mark and ending the coding.

9. The FPGA-based high-resolution video image compression transmission method according to claim 6,

the Huffman coding unit is used for coding by inquiring the ROM address according to a Huffman coding table preset in the ROM of the FPGA, outputting the code length and the code word, and sequentially outputting the coding result to form a compressed data stream;

during coding, different coding modes are adopted for a DC coefficient and an AC coefficient, and different coding modes are also adopted for the amplitude and the classification SSSS after RLE run length coding:

for the DC coefficient, the current DC coefficient is subtracted by the previous DC coefficient, and then the alternating coding of VLC variable length Huffman coding and VLI variable length integer coding is carried out;

alternating coding of VLC variable length Huffman coding and VLI variable length integer coding is directly adopted for the AC coefficient;

VLI variable length integer coding is adopted for the amplitude of RLE run length coding;

VLC variable length Huffman coding is adopted for the classification SSSS.

10. The FPGA-based high resolution video image compression transmission method of claim 6, wherein the FPGA further comprises:

an FF00 replacing unit, which is used for replacing a 16-system number FF00 of 2 bytes when a 16-system FF appears in the coded data stream after the Huffman coding unit is coded;

the header adding unit is used for adding a JPEG encoding head to the compressed data according to the information of the encoding head preset in the RAM of the FPGA so as to package the data into a complete JPEG format picture data stream; the information of the encoding head comprises resolution, quantization table and Huffman table information;

the UDP communication interface is used for packaging the packaged image data stream into UDP messages and sending the UDP messages through the interface, and when the UDP communication interface is packaged, a specific frame mark is added before the data of each frame is started so as to be convenient for separating each frame at a receiving end;

and the UART configuration interface is connected with a register set of the FPGA and is used for setting the resolution of the video image and the quantization table information defined by the user through the UART configuration interface so as to adjust the required image compression ratio.

Technical Field

The invention relates to video image compression, in particular to a high-resolution video image compression and transmission method and system based on FPGA.

Background

The video transmission system is applied to various industries, and in order to meet various requirements of users, the types of the existing video interfaces are more and more abundant, and the transmission capability is more and more strong. Such as early analog interfaces VGA, CVBS interface, to digital interfaces DVI, HDMI, DP, etc., to name but a few. The resolution ratio of the transmission is higher and higher, and the frame rate is higher and higher, but the defects of high requirement on transmission cables, short transmission distance, inflexible transmission and the like exist at the same time.

In practical use, users often need to transmit a high-definition video image more flexibly and at a longer distance or to transmit a high-definition video image by using a common communication interface, for example, a 4K-resolution video image is transmitted through a network interface, which requires that the video image is compressed and then transmitted. The existing compression processing transmission mode has transmission problem when the communication bandwidth is limited, and can be completed only when a certain requirement is provided for a communication interface, and the processing mode has more requirements/waste on hardware resources, and needs to be improved.

Disclosure of Invention

Aiming at the defects and defects of the related prior art, the invention provides the high-resolution video image compression and transmission method and the system based on the FPGA, the high-resolution video image compression is realized by combining an innovative compression coding algorithm under the condition of only using a single FPGA, the data volume is greatly reduced, the larger resolution can be transmitted by using the smaller bandwidth, the high-resolution video can be transmitted by using the lower-speed communication interface, and the video transmission can be completed under the condition of limited communication bandwidth.

In order to achieve the above object, the present invention employs the following techniques:

the high-resolution video image compression transmission method based on the FPGA is characterized by comprising the following steps:

acquiring a video data stream to the FPGA through an interface of the FPGA, and judging the format of the video data stream:

if the format of the video data stream is YCbCr4:4:4, writing the video data stream into a video cache RAM of the FPGA;

if the format of the video data stream is not YCbCr4:4:4, obtaining the format of YCbCr4:4:4 through color gamut conversion, and writing the format into a video cache RAM of the FPGA; the video cache RAM comprises two groups of 8 RAMs, and each RAM is used for caching a line of video data stream data;

writing into 16 video line cache RAMs circularly, wherein 8 RAMs are 1 group and are divided into 2 groups, reading data from left to right sequentially after each group of RAM is written, reading 8 columns each time, and forming an 8X8 image data block for processing until the whole group of data is read; the method comprises the following steps: writing each line of video data stream data into two groups of RAMs in sequence and circularly, caching the two groups of RAMs according to ping-pong operation, reading the data in the 8 RAMs of the group at the same time after the first group of RAMs is written, reading 8 columns each time to form an 8x8 image data block for processing, and writing the newly-entered data cache into a second group of RAMs;

performing DCT transformation, ZIGZAG scanning, quantization, RLE run-length coding and Huffman coding on an 8x8 image data block in sequence until 8 rows of data are completely processed according to an 8x8 image data block, and if the last block is less than 8 rows, performing compensation on the last pixel points; and processing the 8 rows of data of the second group of RAM until the whole frame of image processing is finished, and finishing compression.

Further, DCT transformation is used for converting the time domain of the video signal into the frequency domain, and an 8x8 coefficient matrix is obtained; a ZIGZAG scan for converting the DCT-transformed 8x8 coefficient matrix into one-dimensional 1x64 coefficients in a predetermined arrangement order and sequentially outputting the coefficients; quantizing the coefficients reordered by the ZIGZAG by using a quantization table, performing division operation on the coefficients and corresponding values in the quantization table, and quantizing the luminance signal and the color difference signal by using different quantization tables respectively; RLE run-length coding is used for representing continuous '0' in the quantized coefficient data in a run-length mode, and outputting amplitude, run-length RRRR and classification SSSS; huffman coding, which is used to maximize the amount of compressed video data based on the frequency of use.

Furthermore, DCT transformation is realized by adopting a table look-up mode:

presetting the coefficient value in a ROM of an FPGA, and then obtaining an operation result by inquiring an ROM address when performing DCT operation, so that an 8x8 image data block is converted into an 8x8 coefficient matrix; in the 8 × 8 coefficient matrix, the first system in the upper left corner is a direct current DC coefficient, and the remaining 63 are alternating current AC coefficients.

Further, compressing the continuous '0' values in the quantized coefficients of an image data block, comprising the steps of: counting the input coefficient value, and if the input coefficient is not '0', outputting an encoding result; if the input coefficient is '0', counting the number of continuous '0' and outputting another coding result according to the number of '0'; and counting the rest input coefficients according to the mode, and if the coefficients from the beginning to the last at a certain position are all continuous 0, outputting an end EOB mark and ending the coding.

Further, the Huffman coding comprises the following steps: presetting a Huffman coding table in a ROM of an FPGA, coding by inquiring the ROM address during coding, outputting the code length and code words, and outputting the coding result in sequence to form a compressed data stream;

during coding, different coding modes are adopted for a DC coefficient and an AC coefficient, and different coding modes are also adopted for the amplitude and the classification SSSS after RLE run length coding:

for the DC coefficient, the current DC coefficient is subtracted by the previous DC coefficient, and then the alternating coding of VLC variable length Huffman coding and VLI variable length integer coding is carried out;

alternating coding of VLC variable length Huffman coding and VLI variable length integer coding is directly adopted for the AC coefficient;

VLI variable length integer coding is adopted for the amplitude of RLE run length coding;

VLC variable length Huffman coding is adopted for the classification SSSS.

The invention also provides a high-resolution video image compression and transmission system based on the FPGA, which comprises the FPGA arranged on the board card, and is characterized in that the FPGA comprises:

the video data stream input interface is used for acquiring a video data stream to the FPGA and judging whether the video data stream is in a YCbCr4:4:4 format or not;

the color gamut conversion module is used for converting the video data stream format into the YCbCr4:4:4 format when the video data stream input interface judges that the video data stream format is not the YCbCr4:4:4 format;

the video cache RAM comprises two groups of 8 RAMs, wherein each RAM is used for caching a line of video data stream data with the format of YCbCr4:4: 4;

the writing RAM control unit is used for writing each line of video data stream data into the two groups of RAMs in a circulating mode according to the sequence, and the two groups of RAMs perform cache writing according to ping-pong operation;

an 8 × 8 block generating unit, configured to generate 8 × 8 blocks of data and read data from a set of RAMs at the same time, 8 columns each time, thereby forming 8 × 8 blocks of image data until the data in the set of RAMs is completely read;

the DCT unit is used for converting a time domain into a frequency domain of the video signal to obtain an 8x8 coefficient matrix;

a ZIGZAG scanning unit for converting the DCT-transformed 8x8 coefficient matrix into one-dimensional 1x64 coefficients according to a predetermined arrangement sequence and sequentially outputting the coefficients;

the quantization unit is used for quantizing the coefficients reordered by the ZIGZAG by using a quantization table, dividing the coefficients by corresponding values in the quantization table, and quantizing the brightness signal and the color difference signal by using different quantization tables;

the RLE run-length coding unit is used for representing continuous '0' in the quantized coefficient data in a run-length mode and outputting amplitude, run-length RRRR and classification SSSS; and

a Huffman coding unit for maximizing the amount of compressed video data according to the use frequency.

Furthermore, the DCT transformation unit is used for obtaining an operation result by inquiring the address of the ROM according to the coefficient value of the ROM preset in the FPGA when DCT operation is carried out, so that an 8x8 image data block is transformed into an 8x8 coefficient matrix; in the 8 × 8 coefficient matrix, the first system in the upper left corner is a direct current DC coefficient, and the remaining 63 are alternating current AC coefficients.

Further, the quantization unit is used for counting the input coefficient value, and if the input coefficient is not '0', outputting an encoding result; if the input coefficient is '0', counting the number of continuous '0' and outputting another coding result according to the number of '0'; and counting the rest input coefficients according to the mode, and if the coefficients from the beginning to the last at a certain position are all continuous 0, outputting an end EOB mark and ending the coding.

Further, the Huffman coding unit is used for coding by inquiring the ROM address according to a Huffman coding table preset in the ROM of the FPGA, outputting the code length and the code word, and sequentially outputting the coding result to form a compressed data stream;

during coding, different coding modes are adopted for a DC coefficient and an AC coefficient, and different coding modes are also adopted for the amplitude and the classification SSSS after RLE run length coding:

for the DC coefficient, the current DC coefficient is subtracted by the previous DC coefficient, and then the alternating coding of VLC variable length Huffman coding and VLI variable length integer coding is carried out;

alternating coding of VLC variable length Huffman coding and VLI variable length integer coding is directly adopted for the AC coefficient;

VLI variable length integer coding is adopted for the amplitude of RLE run length coding;

VLC variable length Huffman coding is adopted for the classification SSSS.

Further, the FPGA further includes:

an FF00 replacing unit, which is used for replacing a 16-system number FF00 of 2 bytes when a 16-system FF appears in the coded data stream after the Huffman coding unit is coded;

the header adding unit is used for adding a JPEG encoding head to the compressed data according to the information of the encoding head preset in the RAM of the FPGA so as to package the data into a complete JPEG format picture data stream; the information of the encoding head comprises resolution, quantization table and Huffman table information;

the UDP communication interface is used for packaging the packaged image data stream into UDP messages and sending the UDP messages through the interface, and when the UDP communication interface is packaged, a specific frame mark is added before the data of each frame is started so as to be convenient for separating each frame at a receiving end;

and the UART configuration interface is connected with a register set of the FPGA and is used for setting the resolution of the video image and the quantization table information defined by the user through the UART configuration interface so as to adjust the required image compression ratio.

The invention has the beneficial effects that:

1. JPEG compression work on the high-resolution video image frame can be finished only by using one FPGA hardware module; the compression comprises the steps of judgment, color gamut conversion, RAM cache and ping-pong operation, 8x8 block generation, and 8x 8-based DCT (discrete cosine transformation) conversion, ZIGZAG (zero-valued wavelet transform) scanning, quantization, RLE (recursive least squares) and Huffman coding operation, and the like, and can be realized on one FPGA (field programmable gate array) module, so that hardware building resources are saved;

2. the real-time response can be made according to the setting of a user, the user can set a proper compression ratio according to the resolution of an input image and the bandwidth of an output interface, and the system can compress the image according to the setting of the user so as to meet different requirements of the user;

3. DCT transformation processing in a table look-up mode is adopted, so that the definition presetting of coefficient values is favorably realized, a foundation is provided for continuous 0 compression in RLE coding, and then different coding modes are adopted for processing according to a DC system, an AC coefficient, amplitude and classification SSSS after RLE coding compression is combined, so that a more effective and better compression effect is achieved;

4. by applying the invention, after the work of high-resolution video frame compression coding is finished, the compressed data can be transmitted out through the gigabit network port, the function of transmitting high-resolution video images through the gigabit network port is realized, and the high-resolution video images of 4K @30 frames can be transmitted through the gigabit network port through experiments. Due to the flexibility of the FPGA, the types of the input interface and the output interface can be flexibly changed in application so as to meet actual requirements. By means of the advantage of the high-speed parallel characteristic of the FPGA, the video compression processing speed is high, the time delay is small, and the method can be applied to video transmission occasions from a plurality of board cards to board cards and the like. And the amount of compressed video data is greatly reduced, the requirement on transmission bandwidth is reduced, the requirement on a transmission cable is correspondingly reduced, the transmission distance is longer, and the stability is higher.

Drawings

Fig. 1 is a flowchart of a method for compressing and transmitting a high-resolution video image based on an FPGA according to an embodiment of the present application.

Fig. 2 is a schematic diagram of 8 × 8 image data block formation according to an embodiment of the present application.

Fig. 3 is a schematic diagram illustrating an alternative VLC and VLI encoding method according to an embodiment of the present application.

Fig. 4 is a structural diagram of an FPGA-based high-resolution video image compression transmission system according to an embodiment of the present application.

Fig. 5 is a diagram of an example of hardware of an FPGA-based high-resolution video image compression transmission system according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present invention are clearly and completely described below, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention.

All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.