阅读说明：本技术 漏极共享分离lna (Drain-shared split LNA ) 是由 迈尔斯·萨内 埃姆雷·艾兰哲 于 2019-01-28 设计创作，主要内容包括：本文公开了具有低噪声放大器(LNA)的接收机前端(300)。可以使用输出FET的栅极来使共源共栅导通或截止,该共源共栅具有配置有“公共源极”的输入FET和配置有“公共栅极”的输出FET。提供第一开关(235),其允许在每个LNA的输入FET的源极端子之间建立或破坏连接。在输入FET的漏极端子之间提供漏极开关(260),以将输入FET并联放置。这增加了放大器的输入级的g<Sub>m</Sub>,从而改善放大器的噪声系数。(A receiver front-end (300) with a Low Noise Amplifier (LNA) is disclosed. The gates of the output FETs may be used to turn on or off the cascode, which has an input FET configured with a "common source" and an output FET configured with a "common gate". A first switch (235) is provided which allows a connection to be established or broken between the source terminals of the input FETs of each LNA. In thatA drain switch (260) is provided between the drain terminals of the input FETs to place the input FETs in parallel. This increases the g of the input stage of the amplifier m Thereby improving the noise figure of the amplifier.)

1. An amplifier, comprising:

a plurality of Low Noise Amplifiers (LNAs), each of the low noise amplifiers comprising an input transistor and an output transistor;

at least two control input terminals, each coupled to an output transistor of a respective one of the LNAs; and

at least one drain switch connecting drain terminals of input transistors of at least two of the LNAs during a first mode of operation and disconnecting the drain terminals during at least a second mode of operation.

2. The amplifier of claim 1, further comprising at least one source switch connecting source terminals of input transistors of at least two of the LNAs during a first mode of operation and disconnecting the source terminals during at least a second mode of operation.

3. The amplifier of claim 1, wherein a signal coupled to the control input terminal turns the respective output transistor on and off.

4. The amplifier of claim 1, further comprising a gate capacitance module having a first terminal and a second terminal, the first terminal coupled to a gate of an associated one of the input transistors and the second terminal coupled to a source of the associated input transistor.

5. The amplifier recited in claim 4 further comprising a control module having at least one switch control signal output, wherein each drain switch has a switch control signal input to which the respective switch control signal output is coupled.

6. The amplifier recited in claim 4 wherein each gate capacitance module includes a gate capacitor and a gate switch coupled in series between a first terminal and a second terminal of the gate capacitance module.

7. The amplifier recited in claim 6 wherein the gate switch is open when the associated transistor is conductive and closed when the associated transistor is non-conductive.

8. The amplifier recited in claim 1 further comprising at least one gate capacitance module, each gate capacitance module having a first terminal and a second terminal, the first terminal coupled to a gate of an associated one of the input transistors and the second terminal coupled to ground.

9. The amplifier recited in claim 8 further comprising a control module having at least one switch control signal output, wherein each gate capacitance module has a switch control signal input to which the respective switch control signal output is coupled.

10. The amplifier recited in claim 8 wherein each gate capacitance module includes a gate capacitor and a gate switch coupled in series between a first terminal and a second terminal of the gate capacitance module.

11. The amplifier recited in claim 10 wherein the gate switch is open when the associated input transistor is on and the gate switch is closed when the associated input transistor is off.

12. The amplifier of claim 1, further comprising:

a degeneration component; and

a degeneration switch coupled in series with the degeneration component, the series combination of the degeneration component and the degeneration switch coupled between the source of one of the input transistors and circuit ground.

13. The amplifier recited in claim 12 wherein the degeneration component is a degeneration inductor.

14. The amplifier recited in claim 12 wherein the degeneration switch is open when the drain switch is closed and closed when the drain switch is open.

15. The amplifier of claim 12, further comprising at least a second degeneration component and a second degeneration switch, the second degeneration component and the second degeneration switch coupled in series between a source of a second input transistor and ground, and the second degeneration switch being closed when the first degeneration switch is open.

16. The amplifier recited in claim 12 further comprising a control module having a switch control signal output, wherein the degeneration switch has a switch control signal input to which the switch control signal output is coupled.

17. The amplifier of claim 4, further comprising:

a degeneration component; and

a degeneration switch coupled in series with the degeneration component, the series combination of the degeneration component and the degeneration switch coupled between the source grounds of one of the input transistors.

18. The amplifier recited in claim 17 wherein the degeneration component is an inductor.

19. The amplifier of claim 17, wherein the amplifier is,

wherein each gate capacitance module comprises a gate capacitor and a gate switch coupled in series between a first terminal and a second terminal of the gate capacitance module,

wherein the degeneration switch is open when the drain switch is closed and closed when the drain switch is open, and

wherein the gate switch is closed when the drain switch is closed and the gate switch is open when the drain switch is open.

20. The amplifier of claim 17, further comprising at least a second degeneration inductor and a second degeneration switch,

wherein each gate capacitance module comprises a gate capacitor and a gate switch coupled in series between a first terminal and a second terminal of the gate capacitance module,

wherein the degeneration switch is open when the drain switch is closed and closed when the drain switch is open,

wherein when the drain switch is closed, the gate switch is closed, and when the drain switch is open, the gate switch is open, and

wherein the second degeneration inductor and the second degeneration switch are coupled in series between a source of the second input transistor and ground, and the second degeneration switch is closed when the first degeneration switch is open.

21. The amplifier recited in claim 17 further comprising a control module having switch control signal outputs, wherein the degeneration switch has a switch control signal input to which one of the switch control signal outputs is coupled and each gate capacitance module has a switch control signal input to which one of the switch control signal outputs is coupled.

22. A method for amplifying a signal in more than one amplifier, comprising:

coupling a signal to be amplified to inputs of at least a first LNA and a second LNA, each LNA having an input transistor and an output transistor, each transistor having a first terminal, a second terminal, and a third terminal;

coupling a second terminal of an output transistor of the first LNA to a third terminal of an input transistor of the first LNA;

coupling a second terminal of an output transistor of the second LNA to a third terminal of an input transistor of the second LNA;

turning on output transistors of the first LNA and the second LNA during a first mode;

during the first mode, opening a switch between a third terminal of an input transistor of the first LNA and a third terminal of an input transistor of the second LNA;

turning off one of the output transistors during a second mode; and

closing a switch between the second input transistor and the third terminal of the first input transistor in the second mode.

23. The method of claim 22, further comprising:

opening a switch between a second terminal of the first transistor and a second terminal of the second transistor during the first mode; and

closing a switch between the second transistor and a second terminal of the first transistor in the second mode.

24. The method of claim 22, further comprising, during the second mode, closing a gate switch to place a capacitance between a first terminal of the first transistor and a second terminal of the first transistor when the LNA having the first transistor is off.

25. The method of claim 24, further comprising opening the switch during the first mode to remove the capacitor from between a first terminal of the first transistor and a second terminal of the first transistor.

26. The method of claim 25, wherein the capacitance of the capacitor is selected such that an input impedance seen by observing the LNA is substantially the same during the first mode as during the second mode.

27. The method of claim 25, wherein the first and second transistors are field effect transistors, and the first terminal is a gate, the second terminal is a source, and the third terminal is a drain.

28. The method of claim 22, further comprising closing a gate switch to place a capacitor between a first terminal of the first transistor and ground during the second mode if an LNA having the first transistor is off.

29. The method of claim 28, further comprising opening a switch to disconnect a capacitor from between a first terminal of the first transistor and ground during the first mode.

30. The method of claim 29, wherein the capacitance of the capacitor is selected such that an input impedance seen by observing the LNA is substantially the same during the first mode as during the second mode.

31. The method of claim 29, wherein the first and second transistors are field effect transistors, and the first terminal is a gate, the second terminal is a source, and the third terminal is a drain.

32. The method of claim 22, further comprising opening a first degeneration switch to disconnect a second terminal of one of the first and second transistors from ground when changing from the first mode to the second mode.

33. The method of claim 32, further comprising, during the second mode, closing a gate switch to place a capacitor between a first terminal of the first transistor and a second terminal of the first transistor.

34. The method of claim 32, further comprising, during the first mode, opening a switch to disconnect a capacitor from between a first terminal of the first transistor and a second terminal of the first transistor.

35. The method of claim 32, further comprising, during the second mode, closing a gate switch to place a capacitor between the first terminal and the ground.

36. The method of claim 32, further comprising, during the first mode, opening a switch to disconnect a capacitor from between the first terminal of the first transistor and ground.

(1) Field of the invention

Various embodiments described herein relate to amplifiers, and more particularly, to low noise amplifiers for use in communication devices.

Background

Disclosure of Invention

A receiver front end capable of receiving and processing an in-band non-contiguous Carrier Aggregation (CA) signal using multiple Low Noise Amplifiers (LNAs) is disclosed. In accordance with some embodiments of the disclosed method and apparatus, each of the plurality of amplifiers is an LNA that is configured as a cascode (i.e., a two-stage amplifier having two transistors, a first transistor configured as a "common-source" input transistor such as an input Field Effect Transistor (FET), and a second transistor configured as an output transistor (e.g., an output FET) in a "common-gate" configuration. FET does not conduct current from drain terminal to source terminal) to turn off the input FET. A first switch is provided which allows a connection to be established or broken between the source terminals of the input FETs of each LNA. Further, the second switch enables switchable gate-to-source and/or gate-to-ground capacitors to be selectively applied to the input FET of at least one of the LNAs. In some embodiments, a further switch is provided which enables a source-to-ground degeneration inductor to be disconnected from the source terminal of the input FET of the LNA where the output FET is switched off. Selectively turning the output FETs on and off enables the amplifier to operate in a single mode and a split mode. Furthermore, the use of switches ensures that the input impedance to the amplifier is the same in the single mode and the split mode. In addition, a drain switch is provided that couples the drain terminals of each input FET together during a single mode. In the disconnect mode, the switches are opened to decouple the drain terminals.

The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.

Drawings

Fig. 1 is a diagram of a portion of a cellular telephone front end with an LNA coupled to a variable attenuator.

Fig. 2 is a diagram of a front-end amplifier with a degenerated switch, gate capacitor module and using multiple LNAs operating in single mode or split mode.

Fig. 3 is a simplified schematic diagram of another embodiment of an amplifier having a source split LNA and drain switches and including a resistor that may be selectively placed in parallel across an inductor and a capacitor in each output load matching circuit.

Fig. 4 is a graph illustrating the improvement in noise figure achieved by using drain switches.

FIG. 5 is a graph showing the noise figure versus current I according to the input frequency_DDGraphs and tables of the relationships between.

Fig. 6 illustrates a method according to one embodiment for amplifying a signal (e.g., a CA signal) using more than one amplifier.

Fig. 7 is a diagram of another embodiment of a method including removing parallel drain resistance during a single mode.

Like reference numbers and designations in the various drawings indicate like elements.

Detailed Description

Fig. 2 is a diagram of a front-end amplifier 200 of a communication receiver, in which multiple Low Noise Amplifiers (LNAs) 202, 204 are used to amplify signals. The signal to be amplified is coupled through the front end signal input terminal 206. In a first mode, referred to as a "single mode," one of the output FETs 208, 212 associated with the LNAs 202, 204 is turned on (i.e., is actively amplifying a signal applied to the input of the LNAs 202, 204). The amplified outputs of the activated LNAs 202, 204 are coupled to output terminals 232, 234. The output FETs 208, 212 of the other LNA204, 202 are turned off (i.e., no current is allowed to flow from drain to source). In one embodiment of the disclosed method and apparatus, each LNA 202, 204 includes a pair of Field Effect Transistors (FETs) 208, 210 and 212, 214. Each pair forms a two-stage LNA in a cascode architecture. However, those skilled in the art will appreciate that other types of transistors may be used, including but not limited to bipolar junction transistors. Further, any type of FET may be used to implement the LNA, including but not limited to Metal Oxide Semiconductors (MOSFETs), Junction Field Effect Transistors (JFETs), insulated gate FETs (igfets), metal semiconductor FETs (mesfets), and the like. Although some types of transistors may be better suited for particular applications, the concepts associated with the disclosed methods and apparatus do not preclude the use of any particular type of transistor. Still further, additional transistors may be included within the LNAs (e.g., LNAs 202, 204), either as additional amplifier stages, or stacked with those FETs 208, 212 shown. Further, in some embodiments, the particular type of transistors and the number of such transistors may vary from one LNA 202, 204 to another or within each LNA 202, 204.

An LNA control signal applied to a control input terminal 216, 218 coupled to the gate of an output transistor (e.g., FET) of the LNA implemented by FETs 208, 212 controls whether the output FET208, 212 of each LNA 202, 204 is on or off (i.e., conducts a substantial amount of current from the drain terminal to the source terminal). In one embodiment, the LNA control signal is generated by a control module, such as LNA controller 217. The LNA controller 217 may generate the LNA control signal based on information about the type of signal to be received by the amplifier 200, the content carried by the signal, or based on a user command to select one or more channels. The LNA controller 217 may be a general purpose processor capable of receiving commands and processing the commands to generate control signals to the LNAs and associated switches disclosed throughout this disclosure. Alternatively, the LNA controller 217 is a dedicated processor specifically designed for generating the control signal. Those skilled in the art will understand how to have such a processor receive a command to enter a first mode, such as a split mode, and determine the particular configuration of the switch control signal and the LNA control signal to be generated. In some cases, the LNA controller 217 may be as simple as a logic block with a look-up table. Alternatively, in some embodiments, the LNA controller 217 may also rely on additional information in determining the state of the switch control signal and the LNA control signal.

In the single mode, an LNA control signal to one of the LNAs 202, 204 causes the output FETs 208, 212 of that LNA 202, 204 to be conductive. LNA control of the other LNA204, 202 causes the output FETs 212, 208 of that LNA 202, 204 to turn off. In the split mode, the output FETs 208, 212 of both LNAs 202, 204 are on. Those skilled in the art will appreciate that additional LNAs not shown in fig. 2 may be similarly coupled to extend the amplifier to select additional channels using additional modes of operation.

The output load matching circuit 220, 222 coupled to the output port 224, 226 of each LNA 202, 204 provides the following approach: by this method, the output impedance can be matched to the load. In one case, an input matching circuit 228 is provided to match the input impedance of the amplifier to the source terminal. Input matchingThe circuit 228 includes an input matching inductor 229 and an input DC block capacitor 233. In some embodiments, output shunt capacitors 230, 231 provide relatively low capacitive reactance to ground for signals within the frequency range of the input signal applied to the inputs of LNAs 202, 204, respectively. In some embodiments, a separate V may be provided for each LNA_DDA voltage source is supplied to increase the isolation between the LNAs 202, 204. In other embodiments, the same supply terminal may be used to provide V to two or more of the LNAs_DD。

The isolation achieved by the front end 200 shown in fig. 2 is enhanced by the fact that there is significant isolation between the output port 232 of the first LNA 202 and the output port 234 of the second LNA 204. In amplifier 200, isolation between the outputs of the front end will improve signals separated by some intervening channels. That is, as the spacing of frequencies increases, the level of gain-frequency overlap of one narrow-band tuned output with another narrow-band tuned output will decrease. This reduction will enhance the isolation between the outputs. In the lower gain mode of operation, output isolation will be improved.

One problem to be solved when using two LNAs in this way is that the input impedance of the front-end amplifier 200 will vary depending on the mode in which the receiver is operating. That is, due to the difference in the gate-to-source capacitance Cgs of the FET transistors when the output FET of the LNA is on and when the output FET of the LNA is off, the input impedance presented in the single mode will be significantly different from the impedance presented in the split mode. A large difference in input impedance will result in a large input mismatch, which in turn has a large adverse effect on almost every aspect of the amplifier 200. This effect may lead to an increase in the noise figure, a decrease in the gain and a degradation of the linearity, e.g. as measured by the third order intercept (IP 3). C of input FET210, 214 from a conductive state to a non-conductive state for each LNA 202, 204_gsResulting in large changes in both the real and imaginary parts of the input impedance of amplifier 200 when operating in single and split modes. Provides a transistor that can be closed in a single mode to couple the source of the first input FET210 toA source switch 235 at the source of the second input FET 214 to reduce this effect. Closing the switch 235 during the single mode to connect the sources of the two input FETs 210, 214 causes the input impedance presented in the split mode (i.e., when both output FETs 208, 212 of the two LNAs 202, 204 are on) to be closer to the input impedance presented during the single mode in which the switch 235 is open. However, this still represents a large impedance change compared to the split mode. In the detached mode, the source switch 235 is opened. Opening the source switch 235 during the split mode improves noise isolation between the output terminals 216, 218.

In addition to the source switch 235, in some embodiments, the front-end amplifier 200 has at least one gate capacitance module 240 that includes a gate capacitor 242 and a gate switch 244 connected in series between a first terminal and a second terminal of the module 240. When the second LNA204 is turned off, the gate switch 244 may be switched to insert the gate capacitor 242 in parallel with the gate and source of the input FET210 to provide additional input capacitance. By adding additional capacitance of the gate capacitor 242, the input impedance during the single mode more closely matches the input impedance during the split mode. Thus, with both the gate switch 244 and the source switch 235 closed during a single mode, the input impedance will match very closely the input impedance presented during split mode (during split mode, both switches 244, 235 are open). In the single mode, gate switch 244 and source switch 235 are closed. In the split mode, the gate switch 244 and the source switch 235 are opened.

Further, the front-end amplifier 200 has at least a first degeneration switch 252 to disconnect degeneration components, such as the first degeneration inductor 238, from the second LNA204 during the single mode. In some embodiments, the second degeneration switch 254 is placed between the source of the first FET210 and a second degeneration component, such as the second degeneration inductor 236, to allow the degeneration inductor 236 to be removed from the LNA 400. Thus, it may be selected which inductor 236, 238 is removed during a single mode. It will be clear to one of ordinary skill in the art that either of the two degeneration switches 252, 254 may be provided separately, or the two switches 252, 254 may be provided together.

When the source switch 235 is closed, the degeneration inductors 236, 238 are open. Thus, when the source switch 235 is open during the split mode, each LNA 202, 204 sees only the inductance of one degeneration inductor 236, 238, the one degeneration inductor 236, 238 being coupled to the respective source of the input FET210, 214 associated with that LNA 202, 204. By opening one of the degeneration switches 252, 254 in a single mode, the active LNAs 202, 214 operating in a single mode have an inductive load between source and ground that is equal to the inductance of only one of the degeneration inductors 236, 238, thereby more closely matching the inductance present during the split mode. Providing the second degeneration switch 254 provides flexibility as to which inductance is present at the source of the activated input FETs 210, 214, regardless of which output FET208, 212 is turned on during a single mode.

In addition to the switches 235, 244, 252, 254, a drain switch 260 is provided to enable the drain terminal of the input FET210 to be coupled to the drain terminal of the input FET 214 during a single mode. In an amplifier operating in a single mode without drain switch 260, the input of one of the input FETs 210, 214 is substantially unused. Closing the drain switch 260 places the two input FETs 210, 214 in parallel. By placing the two input FETs 210, 214 in parallel, the unused input FETs 210, 214 are added to g of the input stage of the front-end amplifier 200_m(i.e., transconductance). Transconductance is the change in drain current divided by the slight change in gate-to-source voltage with a constant drain-to-source voltage. In this case, the drain current is the sum of the currents through each input FET210, 214 (i.e., the currents through the conductive FETs 208, 212). G of amplifier_mThe increase in (b) results in an increase in the noise figure of the amplifier. Conversion frequency of f_T≈g_m(2πC_gs). Thus, due to C_gsIs substantially constant, so that the frequency (f) is switched_T) With g_mIs increased.

Applied to FET208 when a signal is sent to the LNA1 outputThe LNA1 control signal at input 216 provides a bias to allow FET208 to conduct. The LNA2 control signal applied to the input of FET 212 is at ground potential to prevent FET 212 from conducting. By closing drain switch 260, the drain terminal of input FET 214 is conducted in parallel with input FET210, causing some of the current flowing through FET208 to be shunted. It can be seen that since both input FETs 210, 214 are conductive (assuming R of the drain switch 260)_onRelatively low and the two LNAs 202, 204 are substantially identical), substantially twice the current will flow through FET 208. Doubling the total current consumption while maintaining the same current through both input FETs 210, 214, thereby making the effective input device f_TDoubled. However, the input FET 214 requires additional DC bias current to generate g_mAnd therefore the amplifier 200 will consume more power if both input FETs 210, 214 are on. The bias of the input FETs 210, 214 can be set to optimize f_TThe relation to power consumption. Thus, the amplifier 200 is flexible in its operation, allowing a user to determine how to balance the trade-off between power consumption and noise figure in a single mode.

Since the drain switch 260 is open (i.e., non-conductive) during the split mode, the drain switch 260 has minimal effect on the operation of the amplifier 200 in the split mode. Since LNAs 202, 204 operate in common mode, C_off(the capacitance of the drain switch 260 when it is not conducting) has minimal effect on the forward signal. However, if the drain switch 260 is too large, it may negatively impact the isolation of the output LNA output 1 and LNA output 2 in the split mode. In addition, the large drain switch 260 increases the shunt capacitance to the substrate on which the components of the amplifier 200 are fabricated. Such an increase in shunt capacitance may increase the noise contribution from the cascode amplifier. The use of a silicon-on-insulator (SOI) integrated circuit system mitigates this effect to some extent because the additional shunt capacitance added is typically relatively small for SOI integrated circuits.

Furthermore, the size of the drain switch 260 may have an effect on the noise figure. If the drain switch 260 is too small, R of the drain switch 260_onAt both endsThe DC voltage drop (i.e., resistance through the switch when the switch is closed) results in a voltage V across the input FET 214_DSIs reduced. This results in a less efficient g_mThis will have a negative effect on the noise figure. However, because R_onIs at g_mOccurring after a stage, so R_onThe contribution to the noise figure is not very significant.

Fig. 3 is a simplified schematic diagram of another embodiment of an amplifier 300 having source split LNAs 202, 204 and drain switch 260. The amplifier 300 includes a resistor that can be selectively placed in parallel across the inductor and capacitor in each output load matching circuit 220, 222. Within each output load matching circuit 220, 222, switches 302, 304 and drain resistors 306, 308 are connected at the drain terminal and V of one of the output ports 224, 226_DDAre coupled in series. In the single mode, the output impedance of the amplifier 300 drops because the input FETs 210, 214 are placed in parallel when the drain switch 260 is closed. Opening the switches 302, 304 increases the resistance by removing the parallel path through each drain resistor 306, 308.

Fig. 4 is a graph illustrating the improvement in noise figure achieved by using drain switch 260. A first curve 402 shows the signal during a single mode with the drain switch open versus the slave voltage source V_DDCurrent I per level drawn_DDAssociated Noise Figure (NF). In the case of the embodiment shown in FIG. 3, the current I_DDThe method comprises the following steps: (1) current I flowing through the first LNA 202 when the LNA1 control signal is set to turn on the output FET208 of the LNA1_DD1And any leakage current I through the second LNA204_DD2(ii) a Or (2) the current I flowing through the second LNA204 when the LNA2 control signal is set to turn on the output FET 212 of LNA2_DD2And any leakage current I flowing through the first LNA 202_DD1. A second curve 404 shows the drain switch closed in a single mode with the slave voltage source V_DDCurrent I per level drawn_DDThe associated noise figure. It can be seen that at point 406 on curve 402, at which point the current I is_DDEqual to 6 mA-with the drain switch openThe noise figure is about 1.55 dB. In contrast, at point 408, the noise figure with the drain switch 260 closed is about 1.46 dB. Improvement of noise figure with I_DDIs increased. At a current I_DDAt 16mA, the noise figure at which the drain switch 260 is open is shown at point 410 as being approximately 1.53 dB. In contrast, the noise figure when drain switch 260 is closed, shown at point 412, is about 1.23 dB. It should be noted that these curves are plotted against the amplifier 300 with the nominal values of the components and are merely meant to give the relative proportion of the amount of improvement achievable. Amplifiers that include components with particular values and characteristics may differ from these values.

FIG. 5 is a graph showing the noise figure versus current I according to the input frequency_DDGraphs and tables of relationships between. Four curves 502, 504, 506, 508 are shown plotted over a frequency range from 2GHz to 3 GHz. A first curve 502 represents a current I equal to 9.1mA at a frequency from 2GHz to 3GHz with the drain switch open_DD. A second curve 504 shows the current I for 3.9mA with the drain switch 260 closed_DDNoise figure over the entire frequency range. A third curve 506 shows the current I for 7.59mA with the drain switch 260 closed_DDNoise figure over the entire frequency range. Fourth curve 508 shows the current I for 11.0mA with drain switch 260 closed_DDNoise figure over the entire frequency range. It can be seen that with drain switch 260 closed, only 7.5mA of I is used, as compared to 9.1mA when drain switch 260 is open_DDNearly the same noise figure can be achieved.

According to some embodiments of the disclosed methods and apparatus, the switches 235, 244, 252, 254, 260, 302, 304 may be fabricated according to the techniques provided in U.S. patent No. 6,804, 502 ("the 502 patent"), which is incorporated herein by reference, and may be fabricated according to the techniques disclosed in other related patents. Additional improvements in the performance of one or more of the switches 235, 244, 252, 254, 260, 302, 304 may be achieved by implementing the techniques provided in U.S. patent No. 7,910,993 ("the 993 patent"), and by implementing the techniques disclosed in other related patents, which is incorporated herein by reference, No. 7,910,993. The use of such high performance switches reduces the non-linearity of the switches and thus reduces the adverse impact of such switches on the performance of the receiver. However, in many implementations, switches having performance characteristics (i.e., linearity, return loss, switching speed, ease of integration, etc.) that are not as good as switches manufactured according to the techniques disclosed in the '502 and' 993 patents may be used. Thus, each or some of the switches disclosed above may be implemented using any combination of one or more transistors, including FETs, Bipolar Junction Transistors (BJTs), or any other semiconductor switches. Alternatively, the switches may be implemented by electromechanical or MEM (micro electro mechanical system) technology.

Further, those skilled in the art will appreciate that each of the switches 235, 244, 252, 254, 260, 302, 304 may be controlled by a control signal generated by the LNA controller 217 or other such controller selecting the state of each switch according to the operational mode of the amplifier (i.e., whether in the single mode or the split mode). For simplicity, such control signals and inputs to the switches are not shown in the figures, but are well within the understanding of those skilled in the art.

Method of producing a composite material

Fig. 6 is a diagram of a method according to one embodiment of amplifying a signal (e.g., a CA signal) using more than one amplifier. A signal is applied to the input of the amplifier step 601. In some embodiments, the signal includes first and second non-adjacent channels. A first channel and a second channel are considered non-adjacent if there is at least a narrow frequency range between the end of the defined frequency range of the first channel and the beginning of the defined frequency range of the second channel. Typically, at least a third channel is defined in a frequency range between the end of the first channel and the start of the second channel. The frequency range of a channel is typically defined by industry standards, but in some cases may be defined by the 3dB frequency range of a filter typically used to receive signals transmitted on the channel.

The method further comprises selecting between the single mode or the split mode step 603. In one embodiment, selection between the single mode and the split mode is made by turning on the output FET208 in the first LNA 202 and turning off the second output FET 121 within the second LNA204 to select the single mode step 605. In one such embodiment, the first output FET208 is turned on by applying an LNA control signal to a first control input terminal 216 coupled to the gate of an output FET, such as FET208 shown in fig. 2-5. The second output FET 212 is turned off by applying the LNA control signal to the second control input terminal 218. Similarly, selection of the split mode is made by applying an LNA control signal to the control terminals 216, 218 to turn on both output FETs 208, 212 [ step 607 ].

The method further comprises the following steps: the source of the input FET, such as FET210, of the first LNA 202 is coupled to the source of the input FET, such as FET 212, of the second LNA204 during the single mode step 609, and the two sources are decoupled during the split mode step 611. In one such embodiment, the source switch 235 is closed in the single mode and opened in the split mode. When the source switch 235 is closed, it couples the two sources of the input FETs 210, 212. In addition, drain switch 260 is closed in the single mode [ step 613] and opened during the split mode [ step 615 ].

Fig. 7 is a diagram of another embodiment of a method that includes removing the parallel drain resistors 306, 308 during a single mode step 713. In one embodiment, the drain resistance is removed by opening the switches 302, 304. Resistors 306, 308 are added during the split mode by closing switches 302, 304 step 715. One such embodiment further includes selecting a resistance value of the drain resistance such that the output impedance is substantially the same during the single mode and the split mode.

Manufacturing techniques and options

It should be apparent to those of ordinary skill in the art that the various embodiments of the claimed invention can be implemented to meet a variety of specifications. Unless otherwise noted above, selection of appropriate component values is a matter of design choice, and various embodiments of the claimed invention may be implemented in any suitable IC technology (including but not limited to MOSFET and IGFET structures) or in hybrid or discrete circuit form. Integrated circuit embodiments may be fabricated using any suitable substrate and process, including but not limited to standard bulk silicon, silicon-on-insulator (SOI), silicon-on-sapphire (SOS), GaNHEMT, GaAs pHEMT, and MESFET technologies. However, in some cases, the claimed inventive concepts may be particularly useful for SOI-based manufacturing processes (including SOS) as well as manufacturing processes having similar features.

Various embodiments of the claimed invention have been described. It will be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be order independent, and thus may be performed in a different order than that described. Furthermore, some of the steps described above may be optional. Various activities described with respect to the methods identified above can be executed in repetitive, serial, or parallel fashion. It should be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention as claimed, which is defined by the scope of the appended claims, and that other embodiments are within the scope of the claims.