阅读说明：本技术 一种沟槽型igbt器件及其制造方法 (Groove type IGBT device and manufacturing method thereof ) 是由 许海东 于 2020-07-21 设计创作，主要内容包括：本发明公开了一种沟槽型IGBT器件及其制造方法,属于功率半导体器件技术领域,本发明的沟槽型IGBT器件设有两种不同深度的沟槽结构,两种沟槽结构按一定的优化规则排列,典型的排列规则为每两个相邻深沟槽结构之间有1~3个短沟槽结构。短沟槽内形成栅氧和多晶硅,短沟槽内多晶硅与栅极金属相连成为栅极多晶,深沟槽内同样形成栅氧和多晶硅。本发明通过短沟槽结构底部通过注入形成N型CS层,CS层分布稳定,能够获得具有很好的存储电荷效果,使得器件具有优良的正向导通特性；在深沟槽结构下进行了P型注入,有效增强了器件的耐压特性和EAS能力；制造时将高温制程移到深沟槽结构形成之前,能够有效改善晶圆翘曲,提高器件可靠性。(The invention discloses a trench type IGBT device and a manufacturing method thereof, belonging to the technical field of power semiconductor devices, wherein the trench type IGBT device is provided with two trench structures with different depths, the two trench structures are arranged according to a certain optimization rule, and the typical arrangement rule is that 1-3 short trench structures are arranged between every two adjacent deep trench structures. And forming gate oxide and polysilicon in the short trench, connecting the polysilicon in the short trench with gate metal to form gate polycrystal, and forming gate oxide and polysilicon in the deep trench. According to the invention, the N-type CS layer is formed at the bottom of the short trench structure through injection, and the CS layer is stably distributed, so that a good charge storage effect can be obtained, and the device has excellent forward conduction characteristics; p-type injection is carried out under the deep groove structure, so that the voltage withstanding property and EAS capability of the device are effectively enhanced; during manufacturing, the high-temperature process is moved to the front of the formation of the deep groove structure, so that the wafer warping can be effectively improved, and the reliability of the device is improved.)

1. A trench type IGBT device is characterized in that: the N-type drift region (1) is arranged on one surface, provided with a groove structure, of the N-type drift region (1) and is called as an upper surface;

the upper surface of the N-type drift region (1) is provided with a plurality of deep groove structures (2) and short groove structures (3), the depth of each deep groove structure (2) is greater than that of each short groove structure (3), and the deep groove structures (2) and the short groove structures (3) are distributed at preset regular intervals;

a P-type voltage-withstanding layer (5) is formed around the bottom of the deep trench structure (2), an N-type CS layer (4) is formed around the bottom of the short trench structure (3), and the lower surfaces of the P-type voltage-withstanding layer (5) and the N-type CS layer (4) are both in contact with the N-type drift region (1);

grid polysilicon (6) is filled in each deep groove structure (2) and each short groove structure (3), and a grid oxide layer (7) is filled between the grid polysilicon (6) and the inner wall of the short groove structure (3) or between the grid polysilicon (6) and the inner wall of the deep groove structure (2); the grid polysilicon (6) is used for being electrically connected with the grid metal.

2. The trench IGBT device of claim 1, wherein: a P-type body region (9) is formed on the upper surface of the N-type drift region (1), and an emitter metal hole (8) is formed on the upper surface of the P-type body region (9);

the top parts of the deep groove structure (2) and the short groove structure (3) penetrate through the upper surface of the P-type body region (9), and the bottom parts of the deep groove structure and the short groove structure extend downwards to penetrate through the lower surface of the P-type body region (9).

3. The trench IGBT device of claim 2, wherein: the distance between two adjacent deep groove structures (2) is 1-10 um, the depth of each deep groove structure (2) is 3-8 um, and the depth of the P-type body region (9) is smaller than that of the short groove structure (3).

4. The trench IGBT device of claim 2, wherein: n-type emitting regions (10) are arranged on two sides of the tops of the deep groove structures (2) and the short groove structures (3), and the lower surfaces of the N-type emitting regions (10) are connected with a P-type body region (9).

5. The trench IGBT device of claim 1, wherein: and a P-type collector region (11) is arranged below the N-type drift region (1), and an N-type FS layer (12) is arranged between the N-type drift region (1) and the P-type collector (11).

6. The trench IGBT device of claim 1, wherein: more than 1 short trench structures (3) are arranged between two adjacent deep trench structures (2).

7. The trench IGBT device of claim 1, wherein: the distance between the deep groove structure (2) and the short groove structure (3) is 0-5 um.

8. The method of manufacturing a trench IGBT device according to claim 1, characterized in that: and injecting and annealing at the bottom of the short trench structure (3) to form a CS layer (4), and injecting and annealing at the bottom of the deep trench structure (2) to form a P-type pressure-resistant layer (5).

9. The method for manufacturing a trench IGBT device according to claim 1, characterized in that it comprises the steps of:

1) selecting an N-type silicon wafer as a substrate, depositing a layer of silicon dioxide on the N-type silicon wafer of the substrate as a first hard mask, defining a pattern of a short trench structure by a photomask, and opening the first hard mask through etching;

2) injecting P-type impurities into the upper surface of the whole N-type silicon wafer;

3) defining an N-type area through photoetching, and then injecting N-type impurities;

4) etching the groove of the area opened by the first hard mask by adopting an etching process to form a short groove structure (3);

5) injecting and advancing N-type impurities in the peripheral area of the bottom of the short trench structure to form an interconnected N-type CS layer (4), and simultaneously activating the injected P-type impurities in the step 2) to form a P-type body area (9) of the minority storage layer IGBT; simultaneously activating the N-type impurities injected in the step 3) to form an N-type emitter region (10);

6) removing the residual first hard mask by wet etching;

7) after a layer of silicon dioxide is deposited on the upper surface of the N-type silicon wafer again to serve as a second hard mask, the pattern of the deep trench structure is defined by the photomask, and the second hard mask is opened through etching;

8) performing groove etching on the region opened by the second hard mask by adopting an etching process to form a deep groove structure (2) with a preset depth, forming a P-type pressure-resistant layer (5) at the bottom of the deep groove structure by P-type injection, and removing the residual second hard mask by adopting a wet etching process;

9) sequentially depositing a layer of silicon oxide and doped polycrystalline silicon on the upper surface of the N-type silicon wafer and the inner walls of the short groove and the deep groove, and etching to form a gate oxide layer (7) and gate polycrystalline silicon (6) which are used as gates;

10) depositing a layer of silicon dioxide medium on the upper surface of the N-type silicon chip, defining a metal connection area through photoetching and etching, and then leading out a grid electrode and an emitter electrode.

10. The method of manufacturing a trench IGBT device according to claim 9, further comprising the step of: 11) one or more layers of insulating dielectric films are deposited on the surface of the whole N-type silicon wafer, and then a passivation protective layer is formed through photoetching and dry etching processes.

Technical Field

The invention relates to the technical field of power semiconductor devices, in particular to a groove type IGBT device and a manufacturing method thereof.

Background

The IGBT (insulated gate bipolar transistor) is a composite full-control voltage-driven power semiconductor device formed by combining a BJT (bipolar transistor) and an MOSFET (insulated gate field effect transistor), and has high input impedance of the MOSFET and low GTR (turn-on voltage drop). At present, IGBTs have become mainstream devices of power electronic equipment, and have wide applications in the fields of switching power supplies, rectifiers, inverters, UPSs and the like.

With the progress of the process, the IGBT gradually develops from a planar gate type to a trench type with higher current density, and usually, in order to obtain a better conductance modulation effect, an N-type CS layer is added below a P-type body region, but the withstand voltage characteristic is also affected while obtaining a lower saturation voltage drop, and in order to not affect the withstand voltage as much as possible, the concentration and the depth of CS are strictly controlled, which also results in a limited effect of the CS layer.

In the chinese patent publication CN103035521B, "a process method for implementing a few-sub memory layer trench IGBT", after a layer of silicon oxide and doped polysilicon is sequentially deposited on the inner walls of a short trench and a deep trench, a gate is formed by etching (e.g., dry etching), the manufacturing method of the whole IGBT is complicated, and after the deep trench structure is formed, particularly after the silicon oxide and doped polysilicon in the deep trench are formed, a high-temperature propulsion process is performed, which is very likely to cause wafer deformation, resulting in serious consequences.

Disclosure of Invention

The technical purpose is as follows: aiming at the defects in the prior art, the invention discloses a trench type IGBT device and a manufacturing method thereof, wherein trench structures which are arranged according to a certain optimized rule and have two different depths are arranged, gate oxide and polycrystalline silicon are formed in the trench structures, the polycrystalline silicon in a short trench is connected with gate metal to form gate polycrystalline, an N-type CS layer is formed at the bottom of the short trench structure through injection, and a P-type voltage-resistant layer is formed at the bottom of the deep trench through injection, so that the device has excellent forward conduction characteristic and better forward blocking characteristic and EAS capability.

The technical scheme is as follows: in order to achieve the technical purpose, the invention adopts the following technical scheme:

a trench type IGBT device is characterized in that: the N-type drift region is arranged on one surface, provided with a groove structure, of the N-type drift region and is called as an upper surface;

the upper surface of the N-type drift region is provided with a plurality of deep groove structures and short groove structures, the depth of each deep groove structure is greater than that of each short groove structure, and the deep groove structures and the short groove structures are distributed at preset regular intervals;

a P-type pressure-resistant layer is formed around the bottom of the deep trench structure, an N-type CS layer is formed around the bottom of the short trench structure, and the lower surfaces of the P-type pressure-resistant layer and the N-type CS layer are both in contact with the N-type drift region;

grid polycrystalline silicon is filled in each deep groove structure and each short groove structure, and a grid oxide layer is filled between the grid polycrystalline silicon and the inner wall of each short groove structure or between the grid polycrystalline silicon and the inner wall of each deep groove structure; the grid polysilicon is used for being electrically connected with the grid metal.

Preferably, a P-type body region is formed on the upper surface of the N-type drift region, and an emitter metal hole is formed on the upper surface of the P-type body region;

the top parts of the deep groove structure and the short groove structure penetrate through the upper surface of the P-type body region, and the bottom parts of the deep groove structure and the short groove structure extend downwards to penetrate through the lower surface of the P-type body region.

Preferably, the distance between two adjacent deep groove structures is 1-10 um, the depth of each deep groove structure is 3-8 um, and the depth of the P-shaped body region is smaller than the depth of the short groove structure.

Preferably, two sides of the top of each deep trench structure and each short trench structure are provided with an N-type emitter region, and the lower surface of each N-type emitter region is connected with the P-type body region.

Preferably, a P-type collector region is arranged below the N-type drift region, and an N-type FS layer is arranged between the N-type drift region and the P-type collector region.

Preferably, more than 1 short trench structure is arranged between two adjacent deep trench structures.

Preferably, the distance between the deep groove structure and the short groove structure is 0-5 um.

The invention also provides a manufacturing method of the groove type IGBT device, which is characterized in that: and forming a CS layer by injecting annealing at the bottom of the short trench structure, and forming a P-type pressure-resistant layer at the bottom of the deep trench structure by injecting annealing.

The manufacturing method of the groove type IGBT device is characterized by comprising the following steps:

1) selecting an N-type silicon wafer as a substrate, depositing a layer of silicon dioxide on the N-type silicon wafer of the substrate as a first hard mask, defining a pattern of a short trench structure by a photomask, and opening the first hard mask through etching;

2) injecting P-type impurities into the upper surface of the whole N-type silicon wafer;

3) defining an N-type area through photoetching, and then injecting N-type impurities;

4) etching the groove of the area opened by the first hard mask by adopting an etching process to form a short groove structure (3);

5) injecting and advancing N-type impurities in the peripheral area of the bottom of the short trench structure to form an interconnected N-type CS layer (4), and simultaneously activating the injected P-type impurities in the step 2) to form a P-type body area (9) of the minority storage layer IGBT; simultaneously activating the N-type impurities injected in the step 3) to form an N-type emitter region (10);

6) removing the residual first hard mask by wet etching;

7) after a layer of silicon dioxide is deposited on the upper surface of the N-type silicon wafer again to serve as a second hard mask, the pattern of the deep trench structure is defined by the photomask, and the second hard mask is opened through etching;

8) performing groove etching on the region opened by the second hard mask by adopting an etching process to form a deep groove structure (2) with a preset depth, forming a P-type pressure-resistant layer (5) at the bottom of the deep groove structure by P-type injection, and removing the residual second hard mask by adopting a wet etching process;

9) sequentially depositing a layer of silicon oxide and doped polycrystalline silicon on the upper surface of the N-type silicon wafer and the inner walls of the short groove and the deep groove, and etching to form a gate oxide layer (7) and gate polycrystalline silicon (6) which are used as gates;

10) depositing a layer of silicon dioxide medium on the upper surface of the N-type silicon chip, defining a metal connection area through photoetching and etching, and then leading out a grid electrode and an emitter electrode.

Preferably, the method further comprises the steps of: 11) one or more layers of insulating dielectric films are deposited on the surface of the whole N-type silicon wafer, and then a passivation protective layer is formed through photoetching and dry etching processes.

Has the advantages that: due to the adoption of the technical scheme, the invention has the following technical effects:

1. the trench IGBT device structure provided by the invention has two trench structures with different depths, a P-type voltage-withstanding layer is formed around the bottom of the deep trench structure, an N-type CS layer is formed around the bottom of the short trench structure, and the CS layer is formed by injecting and annealing in the short trench structure.

2. The injection depth of the CS layer is easy to control and stable, namely the CS layer is formed at the bottom of the short trench by using trench structures with different depths, so that a good conductance modulation effect is achieved; the bottom of the deep groove is injected to form a P-type voltage-resistant layer which can bear a high electric field, cannot be influenced by the CS layer, is far away from a high electric field region, has good saturation voltage drop and voltage resistance, and enables a device to have excellent switching performance.

3. The method for manufacturing the IGBT device moves the high-temperature process to the front of the formation of the deep trench structure, can effectively improve the wafer warpage and improve the reliability of the device. Particularly, P-type injection is carried out under a deep trench structure, so that the voltage withstanding property and EAS capability of the device are effectively enhanced.

Drawings

Fig. 1 is a schematic structural diagram of an IGBT device according to the present invention;

the transistor comprises a 1-N type drift region, a 2-deep trench structure, a 3-short trench structure, a 4-N type CS layer, a 5-P type voltage-withstanding layer, 6-grid polycrystalline silicon, a 7-grid oxide layer, an 8-emitter metal hole, a 9-P type body region, a 10-N type emitter region, an 11-P type collector region and a 12-N type FS layer.

Detailed Description