阅读说明：本技术 升压功率因数校正转换 (Boost power factor correction conversion ) 是由 J·M·莱斯滕 S·吉姆班科 F·马里诺 R·D·斯特拉夸丹尼 于 2019-02-20 设计创作，主要内容包括：在示例中,一种系统(100)包括升压功率因数校正(PFC)转换器(98),该转换器包括耦合到公共节点(119)的热敏电阻(118)、电感器(106)和晶体管(108)。该系统(100)还包括耦合到公共节点(119)的PFC控制器(110)。PFC控制器(110)包括：比较器,其耦合到阈值电压源和晶体管(108)的非控制端子；第一触发器,其耦合到比较器和晶体管(108)的控制端子(109)；零电流检测器,其耦合到电感器(106)；计时器,其耦合到比较器和零电流检测器；第二触发器,其耦合到计时器和晶体管(108)的控制端子(109)；“与”门,其耦合到第一触发器和第二触发器；第三触发器,其耦合到第二触发器和晶体管(108)的控制端子(109)；以及第四触发器,其耦合到“与”门和晶体管(108)的控制端子(109)。(In an example, a system (100) includes a boost Power Factor Correction (PFC) converter (98) including a thermistor (118), an inductor (106), and a transistor (108) coupled to a common node (119). The system (100) also includes a PFC controller (110) coupled to the common node (119). The PFC controller (110) includes: a comparator coupled to a threshold voltage source and a non-control terminal of a transistor (108); a first flip-flop coupled to the comparator and to a control terminal (109) of a transistor (108); a zero current detector coupled to the inductor (106); a timer coupled to the comparator and the zero current detector; a second flip-flop coupled to the timer and to a control terminal (109) of the transistor (108); an AND gate coupled to the first flip-flop and the second flip-flop; a third flip-flop coupled to the second flip-flop and to a control terminal (109) of a transistor (108); and a fourth flip-flop coupled to the and gate and to a control terminal (109) of the transistor (108).)

1. A system, comprising:

a boost Power Factor Correction (PFC) converter including a thermistor, an inductor, and a transistor coupled to a common node; and

a PFC controller coupled to the common node and including:

a comparator coupled to a threshold voltage source and a non-control terminal of the transistor;

a first flip-flop coupled to the comparator and a control terminal of the transistor;

a zero current detector coupled to the inductor;

a timer coupled to the comparator and the zero current detector;

a second flip-flop coupled to the timer and the control terminal of the transistor;

an AND gate coupled to the first flip-flop and the second flip-flop;

a third flip-flop coupled to the second flip-flop and the control terminal of the transistor; and

a fourth flip-flop coupled to the AND gate and the control terminal of the transistor.

2. The system of claim 1, wherein the first flip-flop comprises an inverted clock input coupled to the control terminal of the transistor.

3. The system of claim 1, wherein the first flip-flop comprises a data input configured to receive a low signal.

4. The system of claim 1, wherein the timer comprises an inverted enable input coupled to an output of the comparator and a clear input coupled to an output of the zero current detector.

5. The system of claim 1, wherein a first input of the and gate is coupled to an output of the first flip-flop and a second input of the and gate is coupled to an inverted output of the second flip-flop.

6. The system of claim 1, wherein the third flip-flop comprises a data input coupled to an output of the first flip-flop and a clock input coupled to the control terminal of the transistor.

7. The system of claim 1, wherein the fourth flip-flop comprises a data input coupled to an output of the and gate and a clock input coupled to the control terminal of the transistor.

8. A system, comprising:

a boost Power Factor Correction (PFC) converter including a thermistor, an inductor, and a transistor coupled to a common node; and

a PFC controller coupled to the common node and configured to determine whether a current through the inductor reaches approximately zero within a predetermined amount of time after a voltage at the common node falls below a threshold.

9. The system of claim 8, wherein the PFC controller comprises a comparator, a plurality of flip-flops, an and gate, a timer, and a zero current detector.

10. The system of claim 8, wherein the PFC controller comprises:

a comparator coupled to the blanking circuit; and

a first flip-flop having a set input coupled to the blanking circuit and an inverted clock input coupled to a gate terminal of the transistor.

11. The system of claim 10, wherein the PFC controller comprises:

a timer having an enable input coupled to the comparator, a clear input coupled to a zero current detector, and an output,

wherein the zero current detector is configured to detect a current flowing through the inductor.

12. The system of claim 11, wherein the PFC controller comprises a second flip-flop having a set input coupled to the output of the timer, an inverted clock input coupled to the gate terminal of the transistor, and a data input configured to receive a low signal.

13. The system of claim 12, wherein the PFC controller comprises an and gate coupled to an output of the first flip-flop and an inverted output of the second flip-flop.

14. The system of claim 13, wherein the PFC controller comprises a third flip-flop having a data input coupled to the output of the first flip-flop and a clock input coupled to the gate terminal of the transistor.

15. The system of claim 14, wherein the PFC controller is configured to control switching of the transistor based on an output of the third flip-flop.

16. The system of claim 14, wherein the PFC controller comprises a fourth flip-flop having a data input coupled to an output of the and gate, and a clock input coupled to the gate terminal of the transistor.

17. The system of claim 16, wherein the PFC controller is configured to control switching of the transistor based on an output of the fourth flip-flop.

18. A system, comprising:

a comparator having a first input configured to receive a voltage of a non-control terminal of the transistor, a second input configured to receive a threshold voltage, and an output;

a first flip-flop having a set input coupled to the output of the comparator, a data input configured to receive a low signal, an inverted clock input coupled to a control terminal of the transistor, and an output;

a timer having an inverted enable input coupled to the output of the comparator, a clear input coupled to a zero current detector, and an output;

a second flip-flop having a set input coupled to the output of the timer, a data input configured to receive a low signal, an inverted clock input coupled to the control terminal of the transistor, and an inverted output;

an AND gate having a first input coupled to the output of the first flip-flop, a second input coupled to the inverted output of the second flip-flop, and an output;

a third flip-flop having a data input coupled to the output of the first flip-flop, a clock input coupled to the control terminal, and an output; and

a fourth flip-flop having a data input coupled to the output of the AND gate, a clock input coupled to the control terminal, and an output.

19. The system of claim 18, further comprising a boost Power Factor Correction (PFC) converter including the transistor and an inductor coupled to a common node.

20. The system of claim 18, further comprising a thermistor coupled to the common node.

21. A method, comprising:

performing a first comparison of a transistor drain voltage to a threshold voltage;

in response to the transistor drain voltage exceeding the threshold voltage in the first comparison, reducing a duty cycle of a boost Power Factor Correction (PFC) converter;

performing a second comparison of the transistor drain voltage to the threshold voltage after reducing the duty cycle;

in response to the transistor drain voltage exceeding the threshold voltage and about zero current being detected in the inductor of the boost PFC converter in the second comparison, stopping switching operation of the boost PFC converter;

in response to the threshold voltage exceeding the transistor drain voltage in the second comparison, a timer in the boost PFC converter has not expired, and about zero current is detected in the inductor, stopping the switching operation; and

in response to the threshold voltage exceeding the transistor drain voltage and the timer expiring in the second comparison, decreasing the duty cycle.

Technical Field

The disclosure relates to boost power factor correction conversion.

Disclosure of Invention

In one example, a system includes a boost Power Factor Correction (PFC) converter including a thermistor, an inductor, and a transistor coupled to a common node. The system also includes a PFC controller coupled to the common node. The PFC controller includes: a comparator coupled to a threshold voltage source and a non-control terminal of the transistor; a first flip-flop coupled to the comparator and a control terminal of the transistor; a zero current detector coupled to the inductor; a timer coupled to the comparator and the zero current detector; a second flip-flop coupled to the timer and a control terminal of the transistor; an AND gate coupled to the first flip-flop and the second flip-flop; a third flip-flop coupled to the second flip-flop and the control terminal of the transistor; and a fourth flip-flop coupled to the and gate and the control terminal of the transistor.

In one example, a system includes a boost Power Factor Correction (PFC) converter including a thermistor, an inductor, and a transistor coupled to a common node. The system also includes a PFC controller coupled to the common node and configured to determine whether a current through the inductor reaches approximately zero within a predetermined amount of time after a voltage at the common node falls below a threshold.

In one example, a system includes a comparator having a first input configured to receive a voltage of a non-control terminal of a transistor, a second input configured to receive a threshold voltage, and an output. The system also includes a first flip-flop having a set input coupled to the output of the comparator, a data input configured to receive a low signal, an inverted clock input coupled to the control terminal of the transistor, and an output. The system also includes a timer having an inverting enable input coupled to the output of the comparator, a clear input coupled to the zero current detector, and an output. The system also includes a second flip-flop having a set input coupled to the output of the timer, a data input configured to receive a low signal, an inverted clock input coupled to the control terminal of the transistor, and an inverted output. The system also includes an AND gate having a first input coupled to the output of the first flip-flop, a second input coupled to the inverted output of the second flip-flop, and an output. The system also includes a third flip-flop having a data input coupled to the output of the first flip-flop, a clock input coupled to the control terminal, and an output. The system also includes a fourth flip-flop having a data input coupled to the output of the and gate, a clock input coupled to the control terminal, and an output.

Drawings

Fig. 1 is a circuit diagram of a boost Power Factor Correction (PFC) converter system according to one example.

Fig. 2 is a circuit diagram of a boost PFC controller detector according to one example.

Fig. 3-6 are timing diagrams depicting the behavior of the boost PFC controller detector of fig. 2 according to one example.

Fig. 7 is a flow chart describing a method of operation for the boost PFC controller detector of fig. 2 according to one example.

Fig. 8 is a flow chart describing a method associated with the boost PFC controller detector of fig. 2 according to one example.

Fig. 9 is a block diagram of an electronic device including a boost PFC converter system according to one example.

Detailed Description

The power factor of an Alternating Current (AC) electrical power system is defined as the ratio of the active power absorbed by a load to the apparent power flowing in the circuit. Electrical systems with power factors less than 1.0 suffer from inefficiencies that negatively impact the performance of the electronic devices in which the power system is implemented as well as the performance of the power grid. These inefficiencies may be corrected. Certain types of power converters can be used to improve power factor. One such type of power converter is a boost Power Factor Correction (PFC) converter that includes a switch that is quickly turned on and off at a variable duty cycle to cause the input current to become sinusoidal and in phase with the input voltage. Boost PFC converters typically include an AC source, a rectifier, an inductor, one or more filtering or smoothing capacitors, a diode, and the aforementioned switches.

One problem commonly encountered in boost PFC converters occurs when the converter is first turned on. At this time, a large amount of inrush current flows from the AC source through the converter. This current is undesirable for a number of reasons, one of which is the fact that such high current levels may damage the converter. To overcome this problem, a thermistor is sometimes placed in the current path of the converter to mitigate the inrush current. The thermistor provides a high resistance when the converter is first switched on and cold, and the resistance of the thermistor decreases once the converter has warmed up and the risk of large inrush currents is low.

A disadvantage of using such a thermistor is that during initial operation of the converter the voltage across the thermistor may reach a high level. Such high voltages may for example damage the transistor switches of the converter. Therefore, it would be useful to monitor the voltage at the thermistor and take precautionary action when the voltage becomes too high. However, a high voltage at the thermistor may indicate a different condition, which requires different precautions. For example, in some cases, a high thermistor voltage may indicate an overvoltage condition that may be damaged, and such a condition should be addressed by, for example, turning off the converter and/or adjusting the duty cycle of the transistor switch. In other cases, a high thermistor voltage may represent a transient condition (referred to as a cold start condition) that occurs during initial operation of the converter, and such a condition may be addressed simply by adjusting the duty cycle of the transistor switches. The ability to distinguish between these two cases would be useful.

The present disclosure describes various examples of boost PFC converter systems configured to distinguish between a true overvoltage condition and a transient high voltage condition (also referred to as a cold start condition). Advantages provided by such a boost PFC converter system include the ability to accurately diagnose high voltage conditions and take appropriate action to mitigate damage to the boost PFC converter system, the electronic device containing the converter system, and the power grid. Other PFC converter systems do not have the ability to accurately distinguish between true overvoltage conditions and cold start conditions and therefore do not have the ability to effectively and efficiently take precautionary measures to mitigate damage to the converter system.

In some examples, a boost PFC converter system described herein includes a boost PFC converter and a PFC controller coupled to a node between an inductor and a thermistor in the boost PFC converter. The PFC controller is configured to determine whether a current through the inductor reaches approximately zero within a predetermined amount of time after a voltage at the node falls below a threshold. If the current reaches approximately zero within a predetermined amount of time, the PFC controller outputs a signal indicating that the converter is in a true overvoltage condition and takes appropriate mitigation steps, such as reducing the switching duty cycle and/or turning off the converter for an extended predetermined period of time. Otherwise, if the current does not reach approximately zero within the predetermined amount of time, the PFC controller outputs a signal indicating that the converter is in a cold start condition, and the PFC controller may decrease the duty cycle. Other scenarios are also possible, for example, where the PFC controller determines that the voltage at the node does not exceed a threshold, in which case the controller takes no mitigating action. In this way, the PFC controller described herein alleviates the above-mentioned problems.

Fig. 1 is a circuit diagram of a boost Power Factor Correction (PFC) converter system 100 according to one example. The boost PFC converter system 100 includes a boost PFC converter 98 and a PFC controller 110. The boost PFC converter 98 includes an AC source 101 coupled to a rectifier 102, a capacitor 104 coupled to the rectifier 102, an inductor 106 coupled to the capacitor 104, a thermistor 118 coupled to the inductor 106 at a node 119, a diode 120 coupled to the thermistor 118, and a capacitor 122 coupled to the diode 120. Boost PFC converter system 100 also includes a switch 108, such as a transistor (e.g., a Metal Oxide Semiconductor Field Effect Transistor (MOSFET)). For purposes of the remainder of this description, it is assumed that switch 108 is a MOSFET. The drain of MOSFET 108 is coupled to node 119. The source of MOSFET 108 is coupled to resistor 116, which resistor 116 in turn is coupled to capacitor 122. The rectifier 102, capacitor 104, and resistor 116 are coupled to ground. A diode 120 is coupled to the output node VOUT.

The boost PFC converter system 100 also includes a PFC controller 110. The input of PFC controller 110 is coupled to node 119. The output of PFC controller 110 is coupled to the gate 109 of MOSFET 108. (the gate of MOSFET 108 is sometimes referred to herein as the control terminal, and the drain and source of MOSFET 108 are sometimes referred to herein as the non-control terminals.) PFC controller 110 includes a detector 112 coupled to a node 119 and a driver 114. A driver 114 is coupled to the gate 109.

In operation, AC source 101 generates an alternating current signal that is rectified by rectifier 102 to produce a rectified signal that is smoothed by capacitor 104. The inductor 106 accumulates charge based on the current provided from the rectifier 102. When MOSFET 108 is turned on, the current in inductor 106 increases. When MOSFET 108 is turned off, current flows through thermistor 118 and diode 120, and the current in inductor 106 decreases. An output voltage is provided at an output node VOUT. The thermistor 118 mitigates large inrush currents at startup. Diode 120 prevents current flow when the voltage at the anode is low relative to the output voltage at output node VOUT. The capacitor 122 is a filter capacitor. Resistor 116 is optional and may be used, for example, to monitor the current flowing through MOSFET 108.

Detector 112 monitors the voltage at node 119. When detector 112 determines that the voltage at node 119 has dropped below the threshold voltage, detector 112 starts a timer to measure a predetermined amount of time. If the detector 112 determines that the current flowing through the inductor 106 reaches approximately zero within the predetermined amount of time from the time the voltage at node 119 falls below the threshold voltage, the detector 112 discerns a true overvoltage condition and takes appropriate action to protect the converter system 100. For example, the detector 112 outputs one or more signals to the driver 114 that cause the driver 114 to turn off the MOSFET 108 for an extended period of time and/or manipulate the MOSFET 108 to reduce the duty cycle of the converter system 100. If detector 112 determines that the current through inductor 106 reaches approximately zero after the predetermined amount of time, detector 112 recognizes a transient cold start condition and takes appropriate action. For example, the detector 112 outputs one or more signals to the driver 114 that cause the driver 114 to manipulate the MOSFET 108 to reduce the duty cycle of the converter system 100. If the voltage at node 119 does not exceed the threshold voltage, then detector 112 takes no mitigation action. If the voltage at node 119 exceeds the threshold and remains above the threshold, detector 112 causes driver 114 to turn MOSFET 108 off and/or manipulate MOSFET 108 to reduce the duty cycle of converter system 100. As used herein, about zero current may refer to the current through the inductor being at a level that will trigger the zero current detector. It may refer to a current between-5 mA and +5mA, inclusive. It may refer to a current between-lmA and + lmA, inclusive.

Fig. 2 is a circuit diagram of PFC controller detector 112 according to one example. The detector 112 comprises a comparator 201, which comparator 201 comprises inputs 202 and 203. Input 202 is an inverting input and receives a threshold voltage OVP2 TH. Input 203 is a non-inverting input and is coupled to node 119 in fig. 1. (the voltage at node 119 is the drain voltage of MOSFET 108.) the output of comparator 201 is coupled to node 206. Node 206 is coupled to an input 211 of blanking circuit 204. The inverting input 205 is coupled to the gate 109. The blanking circuit 204 has an output 222, the output 222 may be a logic high if the drain voltage is above the threshold voltage, and the output 222 may be a logic low if the drain voltage is below the threshold voltage. The output 222 is coupled to a set input 223 of the flip-flop 221. The flip-flop 221 has a data input 224 that receives a logic low signal, an inverted clock input 225 coupled to the gate 109, a clear input 226 configured to receive a reset signal, and an output 227 coupled to a node 228.

The node 206 is also coupled to an inverted enable input 210 of a timeout timer (or simply timer) 209. The timer 209 has a clear input 212 coupled to an output 213 of a Zero Current Detector (ZCD) 207. ZCD 207 in turn has an input 208 coupled to the drain of MOSFET 108. The timer 209 has an output 214 coupled to a set input 215 of a flip-flop 216. Flip-flop 216 has a data input 217 that receives a low signal. The flip-flop 216 has an inverted clock input 218 coupled to the gate 109. The flip-flop 216 has a clear input 220 configured to receive a reset signal. The flip-flop 216 includes an inverted output 219.

The detector 112 includes an and gate 229, the and gate 229 having an input 230 coupled to the inverted output 219. And gate 229 also has an input 231 coupled to node 228. Flip-flop 237 has a data input 238 coupled to node 228, a set input 243 receiving a logic low, and a clock input 239 coupled to gate 109. The clear input 240 is configured to receive a reset signal and the output 241 provides a signal reset ON TIME. The flip-flop 232 has a data input 233 coupled to the output of the and gate 229 and a clock input 234 coupled to the gate 109. The flip-flop 232 has a clear input 235 configured to receive a reset signal and an output 236 providing a signal OVP2_ FAULT. Flip-flop 232 includes a set input 242 that receives a logic low. The operation of the detector 112 is described below in conjunction with the timing diagrams of fig. 3-4.

Fig. 3 is a timing diagram 300 depicting behavior of the detector 112 of fig. 2 for a cold start condition, according to one example. Waveform 302 depicts the drain voltage of MOSFET 108. Dashed line 304 depicts the threshold voltage received by comparator 201 on input 202. Waveform 306 depicts the output of blanking circuit 204. Waveform 306 goes high when the drain voltage exceeds the threshold voltage, and waveform 306 goes low when the drain voltage is less than the threshold voltage. The exception to this behavior of waveform 306 is during the blanking time provided by blanking circuit 204. Upon expiration of the blanking time (e.g., as determined by a timer within blanking circuit 204), the output of comparator 201 is released to flip-flop 221. Waveform 308 depicts the output 213 of ZCD 207.

When MOSFET 108 is turned on, the current in inductor 106 (fig. 1) increases, and when MOSFET 108 is turned off, the current in inductor 106 (fig. 1) decreases. Because the activation and deactivation of MOSFET 108 is dependent on the signal provided to gate 109, the aforementioned increase in inductor 106 current coincides with a high gate voltage, while the decrease in inductor 106 current coincides with a low gate voltage. At time 310, gate 109 switches low, which means that inductor 106 current (and, therefore, drain voltage) begins to decrease, as depicted by waveform 302. Because the drain voltage (waveform 302) is higher than the threshold voltage (waveform 304), the signal at node 206 is high. The signal at node 206 is provided to blanking circuit 204 and blanking circuit 204 is activated when the inverting input 205 goes low as gate 109 goes low. One reason for the blanking time is to remove noise that appears in the signal at node 206 during the switching of MOSFET 108. After the appropriate blanking time has been provided, output 222 goes high, as indicated by waveform 306 at time 314.

Because output 222 is high, input 223 is high, thereby setting output 227 of flip-flop 221 high. Because input 223 is a set input, output 227 remains high regardless of the change at input 223 until the falling edge of the voltage at gate 109 is received at input 225, at which time a low signal is provided at output 227 that is provided to input 225. For purposes of timing diagram 300, after time 310, the voltage at gate 109 does not experience another falling edge.

At time 318, the drain voltage (waveform 302) drops below the threshold voltage (dashed line 304). At this point, output 222 goes low, but as described above, this has no effect on output 227 of flip-flop 221. Output 227 remains high. However, the result of the drain voltage falling below the threshold voltage is that input 210 receives a low signal, thereby enabling timer 209. An example duration of the timer 209 is 600ns, as indicated by numeral 312. If the ZCD waveform 308 goes high during the time window, a true overvoltage condition is identified. However, as described above, the timing diagram 300 depicts a cold start condition, and thus the ZCD 308 goes high at time 324 after the expiration of the 600ns time window. Referring to detector 112 in fig. 2, at time 318, output 214 is low, which has no effect on flip-flop 216. At time 320, the 600ns time window expires. Because the ZCD signal at the clear input 212 remains low and thus has no effect on the output 214, the output 214 goes high. Because input 215 is a set input, the received high signal causes inverted output 219 to go low. The inverted output 219 will remain low regardless of any further changes to the bit input 215. Thus, from time 320, node 228 is fixed high and inverted output 219 is fixed low. Thus, input 238 is high and input 233 is low. At time 324, the ZCD signal at input 212 rises, but as explained, this has no effect on the output of flip-flop 216. At time 326, the voltage at gate 109 rises and the rising edge is provided to clock inputs 239 and 234. As a result, the flip-flops 237, 232 are triggered to capture their inputs 238, 233. Thus, REDUCED _ ON _ TIME goes high and OVP2_ FAULT goes low. These outputs indicate a cold start condition, meaning that driver 114 should decrease the duty cycle of the system until REDUCED _ ON _ TIM goes low. However, there is no true overvoltage condition that should result in MOSFET 109 turning off and remaining off for an extended period of time.

Fig. 4 shows a timing diagram 400 depicting a true overvoltage condition. Timing diagram 400 is substantially the same as timing diagram 300, wherein like numerals represent like waveforms and events within detector 112. However, timing diagram 400 differs from timing diagram 300 in that the ZCD signal goes high during the 600ns period started by timer 209. Specifically, because the drain voltage is above the threshold voltage at one time, output 227 is high, and therefore node 228 is high. However, the period of time that the drain voltage remains above the threshold voltage is longer than in timing diagram 300, so timer 209 is triggered at time 418, which is later than in timing diagram 300. This triggering of timer 209 is closer to the time that ZCD 207 detects approximately zero current in inductor 106 (fig. 1). Thus, the ZCD signal provided at input 212 goes high at time 424, which is within the example 600ns time window indicated by numeral 412. Because input 212 goes high before timer 209 expires, output 214 remains low. Therefore, the set input 215 remains low, and thus the inverted output 219 remains high. Thus, node 228 is high and inverted output 219 is also high. As a result, input 238 is high and input 233 is also high. When the voltage at gate 109 goes high at TIME 426, REDUCED _ ON _ TIME goes high and OVP2_ FAULT also goes high. These signals together indicate a true overvoltage condition. In response, the driver 114 may adjust the signal provided to the gate 109 to reduce the duty cycle and/or turn off the MOSFET 108 for an extended predetermined period of time.

Fig. 5 includes a timing diagram 500 depicting various scenarios of the system 100. Timing diagram 500 includes inductor 106 current waveform 502, drain voltage waveform 504, threshold voltage dashed line 506, gate voltage waveform 508, waveform 510 depicting output 222, waveform 512 depicting output 219, and waveform 514 depicting output 213. Timing diagram 500 also includes waveform 516 depicting signal REDUCED _ ON _ TIME, waveform 518 depicting signal OVP2_ FAULT, and waveform 520 depicting the RESET signal provided to inputs 220, 226, 235, and 240.

At time 522, the drain voltage drops rapidly to zero, at which time the current of inductor 106 is approximately zero. At time 524, the voltage at gate 109 goes high (waveform 508). This causes MOSFET 108 to turn on, which in turn causes inductor 106 current to rise and the drain voltage to remain approximately zero. At time 526, the voltage at gate 109 becomes low. This causes the drain voltage and inductor 106 current to begin to decrease. At time 528 after the blanking time, output 222 (waveform 510) goes high and remains high until the drain voltage drops below the threshold voltage at time 530. Although brief, this rise of output 222 causes output 227 to go high and remain high. When the drain voltage drops below the threshold voltage at time 530, the timer 209 is triggered. Timer 209 expires at time 532, at which time output 214 (waveform 512) goes high. (if ZCD output 213 has been asserted/asserted before timer 209 expires at time 532, output 214 will not go high, but this is not the case for this case.) because output 214 goes high, set input 215 also goes high, resulting in inverted output 219 being low and remaining low. Because output 227 is high and inverted output 219 is low, input 238 is high and input 233 is low. The ZCD output 213 (waveform 514) goes high at time 534, but this does not matter because flip-flop 216 has already been set high. At time 536, the voltage at gate 109 rises (waveform 508), thus causing flip-flops 237 and 232 to capture their respective inputs. Thus, at TIME 536, the REDUCED _ ON _ TIME signal (waveform 516) goes high and the OVP2_ FAULT signal (waveform 518) remains low. Thus, the drain voltage behavior beginning at time 526 and ending at time 536 is indicative of a cold start condition. As described above, the driver 114 takes appropriate action. For example, the duty cycle of the system may be reduced, which is reflected in the duration of the decrease in the voltage at gate 109 being high in the next cycle (times 536-538). The reset signal (waveform 520) may be asserted (reset signal (waveform 520) asserted) at time 554 to clear the flip-flop.

When the voltage at gate 109 is high, the drain voltage is low and the inductor 106 current rises. At time 538, the voltage at gate 109 drops to low, thus causing the drain voltage to rise rapidly and begin to fall, and also causing inductor 106 current to begin to fall. However, unlike the previous cold start condition, the drain voltage behavior between times 538 and 544 is indicative of normal operation because the drain voltage does not exceed the threshold voltage. When the voltage at the gate 109 drops (time 538), the flip-flops 221, 216 capture their respective inputs 224, 217 (both low). Thus, output 227 is low and inverted output 219 is also low, while outputs 241 and 236 remain unchanged because they are changed by the rising edge gate signal. Since outputs 227, 219 are low, input 238 is low and input 233 is low. When the voltage of gate 109 rises at TIME 544, the signals at inputs 238, 233 are captured and output in the form of low REDUCED _ ON _ TIME and OVP2_ FAULT signals. The driver 114 receives these signals and takes appropriate action. For example, driver 114 may increase the duty cycle of the system as indicated by the increased duration of the gate pulse starting at time 544.

At time 546, the voltage at gate 109 goes low, causing outputs 227, 219 to go low and high, respectively. The drain voltage rises above the threshold voltage causing output 227 to rise. When the drain voltage drops below the voltage threshold at time 550, timer 209 is started. Because the ZCD output 213 goes high before the timer expires, the clear input 212 receives a high signal, thus causing the output 214 to remain low even after the timer 209 expires. Thus, the output 219 remains high. Because output 219 is high and node 228 is high, inputs 238, 233 are high. When the voltage at gate 109 drops at TIME 554, inputs 238, 233 are captured and both the REDUCED _ ON _ TIME and OVP2_ FAULT signals are high. This indicates that a true overvoltage condition exists and the driver 114 takes appropriate action. For example, driver 114 turns MOSFET 108 off for an extended predetermined length of time, and after restarting MOSFET 108, driver 114 decreases the duty cycle.

Fig. 6 is substantially the same as fig. 5, wherein like waveform numbers indicate like waveforms. However, the drain voltage behavior beginning at time 624 appears to drop below the voltage threshold with a timing slightly different from that already described in fig. 5. Output 227 and node 228 go high because the drain voltage exceeds the threshold voltage. At time 630, the drain voltage drops below the threshold voltage, thus triggering timer 209. Numeral 638 depicts a time window in which ZCD output 213 goes high (waveform 614) thus causing set input 215 to remain low and inverted output 219 to remain high. As a result, input 237 is high and input 233 is also high. At TIME 636, the voltage at gate 109 falls and the falling edge causes the inputs 237, 233 to be captured and output as a high REDUCED _ ON _ TIME signal and a high OVP2_ FAULT signal. The driver 114 receives these signals and takes appropriate action. For example, the driver 114 may turn off the MOSFET 108 for an extended predetermined amount of time, and after restarting the MOSFET 108, the driver 114 may decrease the duty cycle.

Fig. 7 depicts a flow diagram of a method 700 according to an example. The method 700 describes the operation of the detector 112. Method 700 begins by receiving a drain voltage and a threshold voltage at a comparator, such as comparator 201 (702). The method 700 next includes providing the comparator output to a blanking circuit (e.g., blanking circuit 204) and a timer (e.g., timer 209) (704). The method then includes waiting for a blanking time to elapse (706), and providing a comparator output to a first flip-flop (such as flip-flop 221) (708). The method 700 also includes determining whether the drain voltage is greater than a threshold voltage (710). If not, the method includes providing a low output from the first flip-flop 221 (712). Control of the method then returns to 710. Otherwise, the method 700 includes setting the output of the first flip-flop 221 high until the next falling edge of the voltage at the gate 109 (714).

Some or all of the steps 716-732 are performed in parallel with some or all of the steps 706-714, since these two sets of steps represent different paths in the detector 112. Method 700 includes determining whether a timer (e.g., timer 209) receives a low comparator input (716). If not, the method includes providing a second flip-flop (e.g., flip-flop 216) output that remains low (718), and returning control of the method to 716. Otherwise, method 700 includes starting timer 209(720), and determining whether the timer has expired (722). If not, the method 700 includes providing a low output from the second flip-flop 216 (724), and determining whether a ZCD output (e.g., output 213) is high (726). If not, control of the method returns to 722. Otherwise, if the ZCD output 213 is high (726), the method 700 includes setting the timer 209 output 214 low (728) and keeping the output of the second flip-flop 216 high until the next falling edge of the voltage at the gate 109 (730). However, if the timer has expired (722), the method 700 includes setting the output of the second flip-flop 216 low until the next falling edge of the voltage at the gate 109 (734). Method 700 describes the operation of detector 112 up to flip-flops 221 and 216. The circuitry downstream of these flip-flops (e.g., "and" gate 229 and flip-flops 232, 237) operates as follows. And gate 229 provides an output based on the outputs of flip-flops 221, 216. At the next rising edge of the voltage at gate 109, the inputs at flip-flops 237, 232 are captured and used to generate signals reset _ ON _ TIME and OVP2_ FAULT.

FIG. 8 depicts a flow diagram of a method 800 associated with the detector 112 of FIG. 2. The method 800 begins by receiving a drain voltage and a threshold voltage at a comparator (802). The method 800 includes providing the comparator output to a blanking circuit and a timer (804). The method 800 next includes waiting for a blanking time of the blanking circuit to elapse (806), and comparing the drain voltage to a threshold voltage (808). The method 800 includes determining whether a drain voltage is greater than a threshold voltage (810). If not, then 810 is repeated. However, if the drain voltage is greater than the threshold voltage, then method 800 includes setting the REDUCED _ ON _ TIME output (e.g., the output of flip-flop 237 in FIG. 2) high (812). Method 800 then includes determining whether the drain voltage is less than a threshold voltage (814). If not, method 800 includes determining if a Zero Current (ZCD) is detected in an inductor (e.g., inductor 106 in FIG. 1) (816). If not, then 814 is repeated. Otherwise, method 800 includes setting OVP2_ FAULT high (824), and then stopping the switching operation of the MOSFET (e.g., MOSFET 108) (828). If the drain voltage is less than the threshold voltage at 814, method 800 includes starting a timer (818) and determining if the timer has expired (820). If not, method 800 includes determining whether zero current has been detected in the inductor (822). If not, 820 is repeated, but if so 824 is performed. If it is determined at 820 that the timer has expired, method 800 includes performing the next switching cycle with a reduced on-time (e.g., reduced duty cycle) (826).

Fig. 9 is a block diagram of an electronic device 800 including a boost PFC converter system 100 according to one example. Specifically, an electronic device 900 (e.g., a mobile device, an automotive subsystem, or any other powered device) includes a power source 902 and a load 904, the power source 902 including the boost PFC converter system 100, and the load 904 powered by the power source 902.

In this description, a manufacturer may configure (e.g., through programming or structural design) elements or features "configured to" or "to" perform a task or function to perform a function at the time of manufacture, and/or these elements or features may be configurable (or reconfigurable) by a user after manufacture to perform the function and/or other additional or alternative functions. The configuration may be performed by firmware and/or software programming of the device, by the construction and/or layout of the hardware components and interconnections of the device, or a combination thereof. Also, in this specification, use of the phrase "ground/earth" or similar phrases includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and/or any other form of ground suitable or applicable to the teachings of this specification. Unless otherwise specified, "about," "approximately," or "substantially" preceding a value refers to +/-10% of the stated value.

Modifications in the described embodiments are possible, and other embodiments are possible, within the scope of the claims.