阅读说明：本技术 时脉数据回复电路、存储器存储装置及快闪存储器控制器 (Clock data recovery circuit, memory storage device and flash memory controller ) 是由 吴仁钜 于 2019-02-15 设计创作，主要内容包括：本发明的实施例提供一种时脉数据回复电路、存储器存储装置及快闪存储器控制器。所述时脉数据回复电路包括相位检测器、数字回路滤波器及相位内插器。相位检测器用以检测数据信号与时脉信号之间的相位差。相位内插器用以根据所述数字回路滤波器的输出产生所述时脉信号。数字回路滤波器用以在初始状态下自动根据存储于数字回路滤波器的预设值运作,以在所述数据信号与所述时脉信号被比较前建立所述时脉信号相对于所述数据信号的预设相位移或频率差。藉此,可有效改善时脉数据回复电路的工作效率。(Embodiments of the invention provide a clock data recovery circuit, a memory storage device and a flash memory controller. The clock data recovery circuit comprises a phase detector, a digital loop filter and a phase interpolator. The phase detector is used for detecting the phase difference between the data signal and the clock pulse signal. The phase interpolator is used for generating the clock pulse signal according to the output of the digital loop filter. The digital loop filter is configured to automatically operate according to a predetermined value stored in the digital loop filter in an initial state to establish a predetermined phase shift or frequency difference of the clock signal relative to the data signal before the data signal is compared with the clock signal. Therefore, the working efficiency of the clock data recovery circuit can be effectively improved.)

1. A clock data recovery circuit, comprising:

a phase detector for detecting a phase difference between the data signal and the clock signal;

a digital loop filter connected to the phase detector; and

a phase interpolator connected to the phase detector and the digital loop filter and configured to generate the clock signal according to an output of the digital loop filter,

the digital loop filter is configured to automatically operate according to a predetermined value stored in the digital loop filter in an initial state to establish a predetermined phase shift or frequency difference of the clock signal relative to the data signal before the data signal is compared with the clock signal.

2. The clock data recovery circuit of claim 1, wherein the predetermined value is not provided by the phase detector.

3. The clock data recovery circuit of claim 1, wherein the predetermined value is independent of the phase difference.

4. The clock data recovery circuit of claim 1, wherein the digital loop filter comprises:

at least one amplifier connected to the output of the phase detector; and

at least one accumulator connected to an output of the at least one amplifier and an input of the phase interpolator,

wherein the preset value is burned into the at least one accumulator.

5. The clock data recovery circuit according to claim 4, wherein the at least one amplifier comprises a first amplifier and a second amplifier, the at least one accumulator comprises a first accumulator and a second accumulator, an input of the first amplifier and an input of the second amplifier are connected to the output of the phase detector, an input of the first accumulator is connected to an output of the second amplifier, an input of the second accumulator is connected to an output of the first amplifier and an output of the first accumulator, and an output of the second accumulator is connected to the phase interpolator.

6. The clock data recovery circuit of claim 5, wherein the predetermined value is programmed into the first accumulator.

7. The clock data recovery circuit according to claim 1, wherein the predetermined value is an integer and is not zero.

8. A memory storage device, comprising:

a connection interface unit for connecting to a host system;

a rewritable non-volatile memory module;

the memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module; and

a clock data recovery circuit disposed in at least one of the connection interface unit and the memory control circuit unit,

the clock data recovery circuit is used for receiving a data signal, generating a clock signal, detecting a phase difference between the data signal and the clock signal, and

the clock data recovery circuit is further configured to automatically operate according to a predetermined value stored in the clock data recovery circuit in an initial state to establish a predetermined phase shift or frequency difference of the clock signal relative to the data signal before the data signal is compared with the clock signal.

9. The memory storage device of claim 8, wherein the preset value is not provided by a phase detector.

10. The memory storage device of claim 8, wherein the preset value is independent of the phase difference.

11. The memory storage device of claim 8, wherein the clock data recovery circuit comprises a phase detector, a digital loop filter, and a phase interpolator, and the digital loop filter comprises:

at least one amplifier connected to the output of the phase detector; and

at least one accumulator connected to an output of the at least one amplifier and an input of the phase interpolator,

wherein the preset value is burned into the at least one accumulator.

12. The memory storage device of claim 11, wherein the at least one amplifier comprises a first amplifier and a second amplifier, the at least one accumulator comprises a first accumulator and a second accumulator, an input of the first amplifier and an input of the second amplifier are connected to the output of the phase detector, an input of the first accumulator is connected to an output of the second amplifier, an input of the second accumulator is connected to an output of the first amplifier and an output of the first accumulator, and an output of the second accumulator is connected to the phase interpolator.

13. The memory storage device of claim 12, wherein the preset value is burned into the first accumulator.

14. The memory storage device of claim 8, wherein the preset value is an integer and the preset value is not zero.

15. The memory storage device of claim 8, wherein the clock data recovery circuit comprises:

a phase detector for detecting the phase difference between the data signal and the clock signal;

a digital loop filter connected to the phase detector; and

a phase interpolator connected to the phase detector and the digital loop filter and configured to generate the clock signal according to an output of the digital loop filter,

wherein the digital loop filter is configured to automatically operate according to the predetermined value stored in the digital loop filter in the initial state to establish the predetermined phase shift or the frequency difference of the clock signal relative to the data signal before the data signal and the clock signal are compared.

16. A flash memory controller for controlling a rewritable non-volatile memory module, the flash memory controller comprising:

a clock data recovery circuit for receiving a data signal, generating a clock signal, detecting a phase difference between the data signal and the clock signal, and

the clock data recovery circuit is further configured to automatically operate according to a predetermined value stored in the clock data recovery circuit in an initial state to establish a predetermined phase shift or frequency difference of the clock signal relative to the data signal before the data signal is compared with the clock signal.

17. The flash memory controller of claim 16, wherein the preset value is not provided by a phase detector.

18. The flash memory controller of claim 16, wherein the preset value is independent of the phase difference.

19. The flash memory controller of claim 16, wherein the clock data recovery circuit comprises a phase detector, a digital loop filter, and a phase interpolator, and the digital loop filter comprises:

at least one amplifier connected to the output of the phase detector; and

at least one accumulator connected to an output of the at least one amplifier and an input of the phase interpolator,

wherein the preset value is burned into the at least one accumulator.

20. The flash memory controller of claim 19, wherein the at least one amplifier comprises a first amplifier and a second amplifier, the at least one accumulator comprises a first accumulator and a second accumulator, an input of the first amplifier and an input of the second amplifier are connected to the output of the phase detector, an input of the first accumulator is connected to an output of the second amplifier, an input of the second accumulator is connected to an output of the first amplifier and an output of the first accumulator, and an output of the second accumulator is connected to the phase interpolator.

21. The flash memory controller of claim 20, wherein the preset value is burned into the first accumulator.

22. The flash memory controller of claim 16, wherein the preset value is an integer and the preset value is not zero.

23. The flash memory controller of claim 16, wherein the clock data recovery circuit comprises:

a phase detector for detecting the phase difference between the data signal and the clock signal;

a digital loop filter connected to the phase detector; and

a phase interpolator connected to the phase detector and the digital loop filter and configured to generate the clock signal according to an output of the digital loop filter,

wherein the digital loop filter is configured to automatically operate according to the predetermined value stored in the digital loop filter in the initial state to establish the predetermined phase shift or the frequency difference of the clock signal relative to the data signal before the data signal and the clock signal are compared.

Technical Field

The present invention relates to electronic circuit technologies, and in particular, to a clock data recovery circuit, a memory storage device, and a flash memory controller.

Background

Digital cameras, mobile phones and MP3 players have grown rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since a rewritable non-volatile memory module (e.g., a flash memory) has the characteristics of non-volatility, power saving, small volume, and no mechanical structure, it is very suitable for being built in various portable multimedia devices.

Most electronic devices are provided with clock data recovery circuits to provide the necessary clock correction. However, in some cases, if there is a clock skew (skew) in the clock signal, the phase detector in the clock data recovery circuit may not provide the corresponding clock adjustment signal successfully because the phase of the initially generated clock signal is in the detection dead zone. If the clock signal cannot leave the detection dead zone after a predetermined time, an error may occur in analyzing the data signal.

Disclosure of Invention

The invention provides a clock data recovery circuit, a memory storage device and a flash memory controller, which can improve the problems.

An exemplary embodiment of the present invention provides a clock data recovery circuit including a phase detector, a digital loop filter and a phase interpolator. The phase detector is used for detecting the phase difference between the data signal and the clock pulse signal. The digital loop filter is connected to the phase detector. The phase interpolator is connected to the phase detector and the digital loop filter and is used for generating the clock signal according to the output of the digital loop filter. The digital loop filter is configured to automatically operate according to a predetermined value stored in the digital loop filter in an initial state to establish a predetermined phase shift or frequency difference of the clock signal relative to the data signal before the data signal is compared with the clock signal.

An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module, a memory control circuit unit and a clock data recovery circuit. The connection interface unit is used for connecting to a host system. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module. The clock pulse data recovery circuit is arranged in at least one of the connection interface unit and the memory control circuit unit. The clock pulse data recovery circuit is used for receiving a data signal, generating a clock pulse signal and detecting a phase difference between the data signal and the clock pulse signal. The clock data recovery circuit is further configured to automatically operate according to a predetermined value stored in the clock data recovery circuit in an initial state to establish a predetermined phase shift or frequency difference of the clock signal relative to the data signal before the data signal is compared with the clock signal.

An exemplary embodiment of the present invention further provides a flash memory controller for controlling a rewritable nonvolatile memory module. The flash memory controller includes a clock data recovery circuit. The clock pulse data recovery circuit is used for receiving a data signal, generating a clock pulse signal and detecting a phase difference between the data signal and the clock pulse signal. The clock data recovery circuit is further configured to automatically operate according to a predetermined value stored in the clock data recovery circuit in an initial state to establish a predetermined phase shift or frequency difference of the clock signal relative to the data signal before the data signal is compared with the clock signal.

In an exemplary embodiment of the invention, the predetermined value is not provided by the phase detector.

In an exemplary embodiment of the invention, the predetermined value is independent of the phase difference.

In an exemplary embodiment of the present invention, the clock data recovery circuit includes a phase detector, a digital loop filter, and a phase interpolator. The digital loop filter includes at least one amplifier and at least one accumulator. The amplifier is connected to the output of the phase detector. The accumulator is connected to the output of the amplifier and the input of the phase interpolator. The preset value is burned into the accumulator.

In an exemplary embodiment of the present invention, the amplifier includes a first amplifier and a second amplifier. The accumulator includes a first accumulator and a second accumulator. An input of the first amplifier and an input of the second amplifier are connected to the output of the phase detector. The input of the first accumulator is connected to the output of the second amplifier. An input of the second accumulator is connected to an output of the first amplifier and an output of the first accumulator. The output of the second accumulator is connected to the phase interpolator.

In an exemplary embodiment of the invention, the preset value is burned into the first accumulator.

In an exemplary embodiment of the invention, the predetermined value is an integer, and the predetermined value is not zero.

Based on the above, a preset value can be pre-stored in the clock data recovery circuit, and the preset value is used to establish a preset phase shift or frequency difference of the clock signal relative to the data signal before the data signal and the clock signal are compared. In some cases, if the phase (or sampling point) of the clock signal is in the detection dead zone, the predetermined phase shift or frequency difference helps to quickly drive the clock signal away from the detection dead zone, thereby effectively improving the working efficiency of the clock data recovery circuit.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a schematic diagram of a clock data recovery circuit according to an exemplary embodiment of the present invention;

FIG. 2 is a diagram illustrating a phase relationship between signals according to an exemplary embodiment of the present invention;

FIG. 3 is a schematic diagram of a digital loop filter according to an exemplary embodiment of the present invention;

FIG. 4 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention;

FIG. 5 is a diagram illustrating a host system, a memory storage device, and an I/O device according to another example embodiment of the present invention;

FIG. 6 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention;

FIG. 7 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.

The reference numbers illustrate:

10: clock data recovery circuit

11: phase detector

12. 32: digital loop filter

13: phase interpolator

14: phase-locked loop circuit

301. 302: amplifier with a high-frequency amplifier

311. 312: accumulator

321: adder

40. 60, 70: memory storage device

41. 61: host system

410: system bus

411: processor with a memory having a plurality of memory cells

412: random access memory

413: read-only memory

414: data transmission interface

42: input/output (I/O) device

50: main machine board

501: portable disk

502: memory card

503: solid state disk

504: wireless memory storage device

505: global positioning system module

506: network interface card

507: wireless transmission device

508: keyboard with a keyboard body

509: screen

510: horn type loudspeaker

62: SD card

63: CF card

64: embedded memory device

641: embedded multimedia card

642: embedded multi-chip packaging storage device

702: connection interface unit

704: memory control circuit unit

706: rewritable nonvolatile memory module

Detailed Description

In the following, a number of embodiments are presented to illustrate the invention, however, the invention is not limited to the illustrated embodiments. Suitable combinations between the embodiments are also allowed. The term "coupled" as used throughout this specification, including the claims, may refer to any direct or indirect connection means. For example, if a first device couples to a second device, that connection should be interpreted as either being a direct connection, or a indirect connection via other devices and some means of connection. Furthermore, the term "signal" may refer to at least one current, voltage, charge, temperature, data, or any other signal or signals.

Fig. 1 is a schematic diagram of a clock data recovery circuit according to an exemplary embodiment of the invention. Referring to fig. 1, the clock data recovery circuit 10 is configured to receive a signal Din and generate a signal CDR _ CLK. The clock data recovery circuit 10 can also detect the phase difference between the Din and CDR _ CLK signals and adjust the CDR _ CLK signal according to the phase difference. For example, the clock data recovery circuit 10 can adjust the phase and/or frequency of the signal CDR _ CLK according to the phase and/or frequency of the signal Din. Thus, the clock data recovery circuit 10 can be used to lock the signals Din and CDR _ CLK in a predetermined phase relationship. For example, the phase difference between the signal Din and CDR _ CLK may be locked at 90 degrees, 180 degrees, 270 degrees, or 360 degrees. The locked signal CDR _ CLK may be used to analyze (e.g., sample) the signal Din to obtain bit data (e.g., bits 1/0) conveyed by the signal Din. In an example embodiment, the signal Din is also referred to as a data signal and/or the signal CDR _ CLK is also referred to as a clock signal.

Clock data recovery circuit 10 includes phase detector 11, digital loop filter 12, and phase interpolator 13. The phase detector 11 is configured to receive the signals Din and CDR _ CLK and detect a phase difference between the signals Din and CDR _ CLK. The phase detector 11 can output a signal UP/DN according to the phase difference. The signal UP/DN may be used to change the phase and/or frequency of the signal CDR _ CLK. For example, signal UP may be used to advance at least one rising edge and/or at least one falling edge of signal CDR _ CLK. The signal DN may be used to delay at least one rising edge and/or at least one falling edge of the signal CDR _ CLK. In an exemplary embodiment, the signal UP/DN is also referred to as a correction signal.

The digital loop filter 12 is connected to the phase detector 11. The digital loop filter 12 is used for receiving the signal UP/DN and generating a signal PI according to the signal UP/DN. The signal PI may correspond to a code (or control code). This code (or control code) may be used to control the phase and/or frequency of the signal CDR _ CLK. In an exemplary embodiment, the signal PI is also referred to as a phase control signal. The phase interpolator 13 is connected to the digital loop filter 12 and the phase detector 11. The phase interpolator 13 is used for receiving the signal PI and the signal PLL _ CLK. The phase interpolator 13 may perform phase interpolation on the signal PLL _ CLK according to the signal PI to generate the signal CDR _ CLK. For example, the phase interpolator 13 may adjust the phase and/or frequency of the signal CDR _ CLK according to the signal PI. The signal PLL _ CLK may be provided by a Phase Locked Loop (PLL) circuit 14. Phase locked loop circuit 14 may be included in clock data recovery circuit 10 or may be independent of clock data recovery circuit 10, although the invention is not limited in this respect. Through the operations of the phase detector 11, the digital loop filter 12 and the phase interpolator 13, the signals Din and CDR _ CLK can be locked in the predetermined phase relationship for the subsequent signal analysis. In addition, the signal CDR _ CLK may also be provided to other circuit elements.

In an exemplary embodiment, the phase detector 11 may be a half-rate (half-rate) phase detector or an 1/4 rate phase detector. Therefore, in operation, the phase detector 11 may not work properly, for example, it may not generate the UP/DN signal normally, for some reason (for example, the sampling point of the CDR _ CLK signal is in the detection dead zone).

Fig. 2 is a diagram illustrating a phase relationship between signals according to an exemplary embodiment of the present invention. Referring to fig. 1 and 2, it is assumed that the CDR _ CLK includes 4 signals CLK (1) to CLK (4). In an ideal state, the frequencies of the signals CLK (1) to CLK (4) are the same and the phase difference between the signals CLK (1) to CLK (4) is 90 degrees. For example, the signals CLK (1) and CLK (3) are inverted, the signals CLK (2) and CLK (4) are inverted, and the phase difference between the signals CLK (1) and CLK (2) is 90 degrees. In addition, ideally, the clock data recovery circuit 10 can lock the phase difference between the signals CKL (1) and Din to 90 degrees by adjusting the phases of the signals CLK (1) -CLK (4) to facilitate subsequent analysis (e.g., sampling) of the signal Din.

However, in an exemplary embodiment, if there is a skew (skew) between the signals CLK (1) to CLK (4), the clock data recovery circuit 10 may not be able to correct the signals CLK (1) to CLK (4) correctly. For example, if there is a clock skew between the signals CLK (1) -CLK (4), there may be a detection dead zone DZ at the boundary between any two eyes of the signal Din. If the rising edge or the falling edge of any one of the signals CLK (1) to CLK (4) is within this detection dead zone DZ, the clock data recovery circuit 10 may not be able to correct it correctly or therefore cannot generate a correction signal. For example, if at least one sampling point of the signal CLK (1) is located at the rising edge or the falling edge of the signal Din and/or at least one sampling point of the signal CLK (3) is located at the rising edge or the falling edge of the signal Din, a clock skew may occur to cause a sampling error, such that the phase detector 11 cannot generate the signal UP/DN successfully. If the UP/DN signal cannot be generated, the CDR _ CLK signal may not be corrected.

In other words, in an exemplary embodiment, if there is a clock offset between the signals CLK (1) to CLK (4), the phase detector 11 may not be able to generate the signal UP/DN successfully to assist the signals CLK (1) to CLK (4) to leave the detection dead zone DZ. In an exemplary embodiment, the detection dead zone DZ may be located at other positions in the signal Din, and the invention is not limited thereto.

In an exemplary embodiment, a predetermined value may be stored in the clock data recovery circuit 10 (e.g., the digital loop filter 12). This preset value is not provided by the phase detector 11. This preset value is also independent of the phase difference detected by the phase detector 11. In addition, the predetermined value can be a positive integer or a negative integer, and the predetermined value is not zero.

In an initial state (e.g., when the signal CDR _ CLK is just corrected), if the phase (or the sampling point) of the signal CDR _ CLK (e.g., at least one of the signals CLK (1) -CLK (4)) is in the detection dead zone DZ, the digital loop filter 12 can generate the corresponding signal PI according to the preset value. Based on this signal PI, the phase interpolator 13 can establish a predetermined phase shift or frequency difference of the signal CDR _ CLK relative to the signal Din between the signal Din and the CDR _ CLK that have not been compared by the phase detector 11. The predetermined phase shift or frequency difference is controlled by the predetermined value. By the predetermined phase shift or frequency difference, the clock data recovery circuit 10 can rapidly drive the signal CDR _ CLK away from the detection dead zone DZ. After the CDR _ CLK leaves the detection dead zone DZ, the signals Din and CDR _ CLK can be locked in the correct phase relationship by the continuous operation among the phase detector 11, the digital loop filter 12 and the phase interpolator 13.

From another perspective, by pre-storing the preset value in the clock data recovery circuit 10 (e.g., the digital loop filter 12), the problem that the clock data recovery circuit 10 cannot be disengaged (or needs a long time to be corrected to disengage) due to clock skew of the signal CDR _ CLK can be reduced, and the working efficiency of the clock data recovery circuit 10 can be further improved.

Fig. 3 is a schematic diagram of a digital loop filter according to an exemplary embodiment of the invention. Referring to fig. 1 and 3, digital loop filter 32 may be the same as or similar to digital loop filter 12. The digital loop filter 32 includes an amplifier (also referred to as a first amplifier) 301, an amplifier (also referred to as a second amplifier) 302, an accumulator (also referred to as a first accumulator) 311, an accumulator (also referred to as a second accumulator) 312, and an adder 321.

In the present exemplary embodiment, the inputs of amplifiers 301 and 302 may be connected to the output of phase detector 11 for receiving signal UP/DN. An input of the accumulator 311 may be connected to an output of the amplifier 302. The output of the accumulator 311 and amplifier 301 may be connected to the input of the adder 321. An input of the accumulator 312 may be connected to an output of the adder 321. The output of accumulator 312 may be connected to the input of phase interpolator 13 to provide signal PI to phase interpolator 13.

In the present exemplary embodiment, amplifier 301 is also referred to as a proportional gain amplifier, and amplifier 302 is also referred to as an integral gain amplifier. For example, the amplifier 301 may amplify the value corresponding to the signal UP/DN by N times, and the amplifier 302 may amplify the value corresponding to the signal UP/DN by M times. N is greater than M. For example, N may be 6 and/or M may be 4, and the values of N and M are not limited thereto. The value amplified by M times by amplifier 302 may be used to update the value stored by accumulator 311. The adder 321 adds the value stored in the accumulator 311 to the value output from the amplifier 301 and updates the value stored in the accumulator 312 according to the operation result. The signal PI may then be generated based on the value stored in the accumulator 312.

In the present exemplary embodiment, the aforementioned preset values can be pre-stored in the accumulator 311. For example, the preset value can be burned into the accumulator 311 as an initial value of the accumulator 311. The predetermined value is a non-zero integer (which may be a positive integer or a negative integer), so the initial value of the accumulator 311 is also a non-zero integer (which may be a positive integer or a negative integer).

In an exemplary embodiment, assume that the default value is "1" (i.e., the initial value of the accumulator 311 is "1"), N is 6, and M is 4. After the clock data recovery circuit 10 is activated, the value stored in the accumulator 311 may be updated to "5" (e.g., 4+1 ═ 5) and the value stored in the accumulator 312 may be updated to "11" (e.g., 6+5 ═ 11) in response to an UP signal (e.g., corresponding to the value "1"). Accordingly, corresponding to the value (e.g., "11") stored by the accumulator 312, a corresponding signal PI may be output. Then, in response to a DN signal (corresponding to the value "-1"), the value stored by accumulator 311 may be updated to "1" (5+ (-4) ═ 1), and the value stored by accumulator 312 may be updated to "6" (((-6) +1+ 11) ═ 6). Accordingly, corresponding to the value (e.g., "6") stored by the accumulator 312, a corresponding signal PI may be output. By analogy, in response to the input signal UP/DN, the values stored in the accumulators 311 and 312 may be continuously updated and the corresponding signal PI may be continuously output.

Conventionally, the initial value of the accumulator 311 may not be preset and/or the initial value of the accumulator 311 is set to zero. Therefore, the phase detector 11 may not be able to provide the signal UP/DN due to the detection dead zone DZ, so that the signal CDR _ CLK cannot escape (or needs a long time to be corrected to escape) the detection dead zone DZ. However, in the present exemplary embodiment, the initial value of the accumulator 311 is an integer that is set to be non-zero in advance. Therefore, even if the phase detector 11 cannot provide the signal UP/DN due to the detection dead zone DZ, an initial signal PI can be generated in response to the initial value of the accumulator 311 to assist the signal CDR _ CLK to leave the detection dead zone DZ.

It should be noted that the initial signal PI may affect the phase and/or frequency of the signal CDR _ CLK and is used to pre-establish a predetermined phase shift or frequency difference of the signal CDR _ CLK relative to the signal Din before the initial comparison of the signals Din and CDR _ CLK. After the predetermined phase shift or frequency difference is generated, the signal CDR _ CLK can be quickly shifted out of the detection dead zone DZ by the continuous operation among the phase detector 11, the digital loop filter 12 and the phase interpolator 13, and the signals Din and CDR _ CLK can be locked in the correct phase relationship.

It should be noted that the digital loop filter 32 shown in the exemplary embodiment of fig. 3 is only an example and is not intended to limit the present invention. In another exemplary embodiment, the number of amplifiers, the number of accumulators, and the connection relationship between the electronic components in the digital loop filter 32 can be adjusted according to the practical requirements. In addition, other types of electronic components may be included in digital loop filter 32 to provide additional functionality, and the invention is not limited in this respect. Alternatively, in an exemplary embodiment, the predetermined value may be stored or programmed in other types of electronic components in the clock data recovery circuit (or the digital loop filter), as long as the predetermined phase shift or frequency difference between the Din signal and the CDR _ CLK in fig. 1 is generated.

In an exemplary embodiment, the clock data recovery circuit 10 of fig. 1 may be disposed in a memory storage device or a memory control circuit unit. Alternatively, in an exemplary embodiment, the clock data recovery circuit 10 of fig. 1 may be disposed in any type of electronic device, and the present invention is not limited thereto.

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). Typically, memory storage devices are used with a host system so that the host system can write data to or read data from the memory storage devices.

FIG. 4 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention. FIG. 5 is a diagram illustrating a host system, a memory storage device and an I/O device according to another example embodiment of the invention.

Referring to fig. 4 and 5, the host system 41 generally includes a processor 411, a Random Access Memory (RAM) 412, a Read Only Memory (ROM) 413 and a data transmission interface 414. The processor 411, the RAM 412, the ROM 413, and the data transmission interface 414 are all connected to a system bus 410.

In the exemplary embodiment, the host system 41 is connected to the memory storage device 40 through the data transmission interface 414. For example, host system 41 may store data to memory storage device 40 or read data from memory storage device 40 via data transfer interface 414. The host system 41 is connected to the I/O device 42 via the system bus 410. For example, the host system 41 may transmit output signals to the I/O device 42 or receive input signals from the I/O device 42 via the system bus 410.

In the present exemplary embodiment, the processor 411, the ram 412, the rom 413 and the data transmission interface 414 can be disposed on the motherboard 50 of the host system 41. The number of data transfer interfaces 414 may be one or more. Through the data transmission interface 414, the motherboard 50 can be connected to the memory storage device 40 in a wired or wireless manner. The memory storage device 40 may be, for example, a personal disk 501, a memory card 502, a Solid State Drive (SSD) 503, or a wireless memory storage device 504. The wireless memory storage 504 can be, for example, a Near Field Communication (NFC) memory storage, a wireless facsimile (WiFi) memory storage, a Bluetooth (Bluetooth) memory storage, or a low power Bluetooth (iBeacon) memory storage based on various wireless communication technologies. In addition, the main board 50 may be connected to various I/O devices such as a Global Positioning System (GPS) module 505, a network interface card 506, a wireless transmission device 507, a keyboard 508, a screen 509, and a speaker 510 through the System bus 410. For example, in an exemplary embodiment, the motherboard 50 may access the wireless memory storage device 504 via the wireless transmission device 507.

In an exemplary embodiment, the host system referred to is substantially any system that can cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, fig. 6 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention. Referring to fig. 6, in another exemplary embodiment, the host system 61 may also be a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 60 may be various non-volatile memory storage devices such as a Secure Digital (SD) card 62, a Compact Flash (CF) card 63, or an embedded storage device 64. The embedded storage 64 includes embedded Multi media card (eMMC) 641 and/or embedded Multi Chip Package (eMCP) storage 642, which connect the memory module directly to the host system substrate.

FIG. 7 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention. Referring to fig. 7, the memory storage device 70 includes a connection interface unit 702, a memory control circuit unit 704 and a rewritable nonvolatile memory module 706.

The connection interface unit 702 is used to connect the memory storage device 70 to the host system 61. The memory storage device 70 may communicate with the host system 61 through the connection interface unit 702. In the present exemplary embodiment, connection interface unit 702 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 702 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the High-Speed Peripheral Component connection interface (PCI Express) standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the memory stick (memory stick, MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash memory (Flash ) interface standard, the CF interface standard, the Device interface (Electronic drive interface), IDE) standard or other suitable standard. The connection interface unit 702 may be packaged with the memory control circuit unit 704 in one chip, or the connection interface unit 702 may be disposed outside a chip including the memory control circuit unit 704.

The memory control circuit unit 704 is used for executing a plurality of logic gates or control commands implemented in hardware or firmware and performing data writing, reading, and erasing operations in the rewritable nonvolatile memory module 706 according to the commands of the host system 61.

The rewritable nonvolatile memory module 706 is connected to the memory control circuit unit 704 and is used for storing data written by the host system 61. The rewritable nonvolatile memory module 706 may be a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a Multi-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a Triple Level Cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a Quad Level Cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.

Each memory cell in the rewritable nonvolatile memory module 706 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, each memory cell has a charge trapping layer between the control gate (control gate) and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be varied, thereby varying the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. Each memory cell in the rewritable nonvolatile memory module 706 has multiple memory states as the threshold voltage changes. The read voltage is applied to determine which memory state a memory cell belongs to, thereby obtaining one or more bits stored by the memory cell.

In the present exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 706 may constitute a plurality of physical program cells, and the physical program cells may constitute a plurality of physical erase cells. Specifically, the memory cells on the same word line may constitute one or more physical programming cells. If each memory cell can store more than 2 bits, the physical program cells on the same word line can be classified into at least a lower physical program cell and an upper physical program cell. For example, the Least Significant Bit (LSB) of a cell belongs to the lower physical program cell, and the Most Significant Bit (MSB) of a cell belongs to the upper physical program cell. Generally, in the MLC NAND flash memory, the writing speed of the lower physical program cell is faster than that of the upper physical program cell, and/or the reliability of the lower physical program cell is higher than that of the upper physical program cell.

In the exemplary embodiment, the physical program cell is a minimum cell to be programmed. That is, the physical programming unit is the smallest unit for writing data. For example, a physical programming unit can be a physical page (page) or a physical fan (sector). If the physical program units are physical pages, the physical program units may include a data bit region and a redundancy (redundancy) bit region. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area stores system data (e.g., management data such as error correction codes). In the present exemplary embodiment, the data bit area includes 32 physical fans, and the size of one physical fan is 512-bit group (B). However, in other example embodiments, 8, 16, or a greater or lesser number of physical fans may be included in the data bit region, and the size of each physical fan may also be greater or lesser. On the other hand, the physical erase cell is the minimum unit of erase. That is, each physical erase cell contains the minimum number of memory cells that are erased together. For example, a physical erase unit is a physical block (block).

In an example embodiment, the rewritable nonvolatile memory module 706 of FIG. 7 is also referred to as a flash memory module. In an example embodiment, the memory control circuit unit 704 of fig. 7 is also referred to as a flash memory controller for controlling a flash memory module. In an exemplary embodiment, the clock data recovery circuit 10 of fig. 1 may be disposed in the connection interface unit 702 or the memory control circuit unit 704 of fig. 7. For example, clock data recovery circuit 10 may be used to process data signals from a host system.

In summary, the exemplary embodiments of the invention can pre-store a preset value in the clock data recovery circuit. The predetermined value is used to establish a predetermined phase or frequency difference of the clock signal relative to the data signal before the data signal and the clock signal are compared. In some cases, if the phase (or sampling point) of the clock signal is in the detection dead zone, the predetermined phase shift or frequency difference helps to quickly drive the clock signal away from the detection dead zone, thereby effectively improving the working efficiency of the clock data recovery circuit.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.