阅读说明：本技术 RapidIO通信阻塞修复方法及系统 (RapidIO communication blockage repair method and system ) 是由 龚锐 任巨 石伟 刘威 张剑锋 王蕾 潘国腾 王永文 于 2020-05-22 设计创作，主要内容包括：本发明公开了一种RapidIO通信阻塞修复方法及系统,本发明RapidIO通信阻塞修复方法包括向与第一节点进行RapidIO通信的第二节点发送复位控制符号,并监测端口初始化过程,当端口初始化过程完成后跳转执行下一步；令第一节点的系统复位信号在预设数量的时钟内有效,并在所述预设数量的时钟内,与所述第二节点重新建立连接并复位第一节点的状态机；控制第一节点中所有与RapidIO通信相关的模块进行复位。本发明能有效解决RapidIO通信阻塞问题,当通信双方在通信过程中出现RapidIO通信中断场景时,自动恢复双方通信。(The invention discloses a RapidIO communication blockage repairing method and a system, wherein the RapidIO communication blockage repairing method comprises the steps of sending a reset control symbol to a second node which carries out RapidIO communication with a first node, monitoring a port initialization process, and jumping to execute the next step after the port initialization process is completed; enabling a system reset signal of the first node to be effective in a preset number of clocks, reestablishing connection with the second node in the preset number of clocks, and resetting a state machine of the first node; and controlling all modules related to RapidIO communication in the first node to reset. The method can effectively solve the problem of RapidIO communication blockage, and when RapidIO communication interruption scenes occur in the communication process of two communication parties, the communication of the two parties is automatically recovered.)

1. A RapidIO communication blockage repairing method is characterized by comprising the following detailed implementation steps:

1) sending a reset control symbol to a second node which carries out RapidIO communication with the first node, monitoring a port initialization process, and skipping to execute the next step after the port initialization process is completed;

2) enabling a system reset signal of the first node to be effective in a preset number of clocks, reestablishing connection with the second node in the preset number of clocks, and resetting a state machine of the first node;

3) and controlling all modules related to RapidIO communication in the first node to reset.

2. The RapidIO communication congestion repair method according to claim 1, further comprising a step of monitoring a status signal indicating a RapidIO communication interruption before the step 1), and skipping to execute the step 1) if the status signal indicating the RapidIO communication interruption is monitored to be valid; and step 3) continuing to execute the step of monitoring the status signal for indicating RapidIO communication interruption after the execution is finished.

3. The RapidIO communication congestion repair method according to claim 2, wherein the status signal for indicating the RapidIO communication interruption is a port error signal or a single channel mode signal.

4. The RapidIO communication congestion repair method according to claim 1, further comprising the step of skipping to execute the step 1) after the first node is powered on and reset before the step 1).

5. The RapidIO communication congestion repair method according to claim 1, wherein step 1) is preceded by monitoring an enable terminal of a logic circuit in the first node, the logic circuit being configured to control triggering of RapidIO communication congestion repair, and skipping execution of step 1) if the enable terminal of the logic circuit transitions from an enabled state to a disabled state.

6. The RapidIO communication congestion repair method according to claim 1, further comprising the following processing steps of the second node after the reset control symbol is sent in step 1):

s1) the second node detects the reset control symbol received by the physical layer, if the physical layer receives the effective reset control symbol, the next step is executed;

s2) making the system reset signal of the second node valid within a preset number of clocks, reestablishing a connection with the first node within the preset number of clocks, and resetting the state machine of the second node;

s3) controls all modules related to RapidIO communication in the second node to reset.

7. The RapidIO communication blockage repair method according to claim 1, wherein the first node and the second node are both FPGA chips.

8. A RapidIO communication congestion repair system comprising a first node and a second node which perform RapidIO communication, characterised in that the first node and the second node are programmed or configured to perform the steps of the RapidIO communication congestion repair method of any one of claims 1 to 7.

9. A RapidIO communication congestion repair system comprising a first node and a second node which perform RapidIO communication, wherein a memory of the first node and the second node stores program firmware programmed or configured to execute the RapidIO communication congestion repair method according to any one of claims 1 to 7.

10. A computer readable storage medium having stored thereon a computer program programmed or configured to perform the RapidIO communication congestion recovery method of any one of claims 1 to 7.

Technical Field

The invention relates to the technical field of communication, in particular to a RapidIO communication blockage repairing method and system.

Background

RapidIO is a high performance, low pin count, packet switch based interconnect architecture, and is an open interconnect technology standard designed to meet and meet future high performance embedded system requirements. With the development of communication technology, RapidIO optical fiber communication technology has been widely applied to distributed embedded systems. However, in the RapidIO optical fiber communication technology, RapidIO blocking due to a communication link problem is easily caused in the communication process, so that important communication data is lost, and loss is caused. And the communication interruption is difficult to automatically recover, and communication needs to be reestablished by powering off both communication parties.

As shown in fig. 1, in a process of using a Field-Programmable Gate Array (FPGA) to communicate via RapidIO optical fiber, there are some situations that easily cause RapidIO blocking, such as suspending communication between a transmitting end and a receiving end during RapidIO communication, restarting communication after a while, and subjecting an optical fiber line to strong shock during RapidIO communication. In the communication process, the sending end and the receiving end generally do not detect that the communication process is damaged or interrupted. Even if the receiving end detects that there is a problem in data transmission, the receiving end cannot inform the sending end of corresponding remedial operation. Once the above RapidIO communication interruption scenario occurs, the communication will be difficult to recover and continue with the wrong data stream or interrupt the transmission completely.

Disclosure of Invention

The technical problems to be solved by the invention are as follows: aiming at the problems in the prior art, the invention provides a RapidIO communication blockage repairing method and system, which can solve the problems that communication is difficult to recover and communication parties continue to transmit with wrong data streams or completely interrupt transmission when a RapidIO communication interruption scene occurs in the communication process.

In order to solve the technical problems, the invention adopts the technical scheme that:

a RapidIO communication blockage repairing method comprises the following detailed implementation steps:

1) sending a reset control symbol to a second node which carries out RapidIO communication with the first node, monitoring a port initialization process, and skipping to execute the next step after the port initialization process is completed;

2) enabling a system reset signal of the first node to be effective in a preset number of clocks, reestablishing connection with the second node in the preset number of clocks, and resetting a state machine of the first node;

3) and controlling all modules related to RapidIO communication in the first node to reset.

Optionally, step 1) is preceded by a step of monitoring a status signal for indicating an interruption of RapidIO communication, and if the status signal for indicating an interruption of RapidIO communication is monitored to be valid, the step 1) is skipped to be executed; and step 3) continuing to execute the step of monitoring the status signal for indicating RapidIO communication interruption after the execution is finished.

Optionally, the status signal for indicating RapidIO communication interruption is a port error signal or a single channel mode signal.

Optionally, step 1) is preceded by a step of performing step 1) by jumping after power-on reset of the first node.

Optionally, step 1) is preceded by monitoring an enable terminal of a logic circuit in the first node, the logic circuit being configured to control triggering of RapidIO communication blocking repair, and skipping execution of step 1) if the enable terminal of the logic circuit transitions from an enabled state to a disabled state.

Optionally, the following processing steps of the second node are further included after the reset control symbol is sent in step 1):

s1) the second node detects the reset control symbol received by the physical layer, if the physical layer receives the effective reset control symbol, the next step is executed;

s2) making the system reset signal of the second node valid within a preset number of clocks, reestablishing a connection with the first node within the preset number of clocks, and resetting the state machine of the second node;

s3) controls all modules related to RapidIO communication in the second node to reset.

Optionally, the first node and the second node are both FPGA chips.

In addition, the invention also provides a RapidIO communication blockage repair system which comprises a first node and a second node for RapidIO communication, wherein the first node and the second node are programmed or configured to execute the steps of the RapidIO communication blockage repair method.

In addition, the invention also provides a RapidIO communication blockage repair system which comprises a first node and a second node for RapidIO communication, wherein the memories of the first node and the second node are stored with program firmware which is programmed or configured to execute the RapidIO communication blockage repair method.

Furthermore, the present invention also provides a computer-readable storage medium having stored therein a computer program programmed or configured to execute the RapidIO communication congestion repair method.

Compared with the prior art, the scheme of the invention has at least the following beneficial effects: when an FPGA chip serving as a transmitting end of RapidIO communication monitors that a state signal for indicating RapidIO communication interruption is effective, the state signal indicates that the FPGA chip and a RapidIO communication interruption of a communication opposite end of the FPGA chip are interrupted, at the moment, the FPGA chip enables the opposite end to execute a reset process by sending a reset control symbol to the opposite end, and meanwhile, when the initialization process of a port of the FPGA chip is monitored to be completed, a system reset signal is enabled to be effective in a preset number of clocks, connection is reestablished with the opposite end, a state machine of the FPGA chip and other modules related to RapidIO communication are reset, and the reset process of the FPGA chip is completed. After the FPGA chip and the opposite end of the FPGA chip are reset, the communication process of the two parties can be restarted, and the communication of the two parties can be recovered, so that the effect of effectively solving the RapidIO communication blocking problem is achieved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.

Fig. 1 is a basic block diagram of a system currently using RapidIO communication.

Fig. 2 is a basic flow diagram of a method of an embodiment of the present invention.

Fig. 3 is a complete flow chart of a method of an embodiment of the present invention.

Detailed Description

The following will further describe in detail the RapidIO communication congestion repair method and system of the present invention, taking two FPGA chips (both the first node and the second node) performing RapidIO communication as an example. It should be noted that the RapidIO communication blockage repair method and system of the present invention are not limited to the FPGA chip, but may also be applied to other chips for RapidIO communication, and are not described herein again. The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

As shown in fig. 1, the detailed implementation steps of the RapidIO communication congestion recovery method in this embodiment include:

1) sending a reset control symbol to a second node which carries out RapidIO communication with the first node, monitoring a port initialization process, and skipping to execute the next step after the port initialization process is completed; it should be noted that the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. From the perspective of sending the reset control symbol, the first node may be called a sending end, and the second node may be called a receiving end; each node can be used as a first node to actively send a reset control symbol to a second node and finish the RapidIO communication blockage repair of the node, and each node can also finish the RapidIO communication blockage repair of the node passively according to the received reset control symbol;

2) enabling a system reset signal of the first node to be effective in a preset number of clocks, reestablishing connection with the second node in the preset number of clocks, and resetting a state machine of the first node;

3) and controlling all modules related to RapidIO communication in the first node to reset.

In step 1) of this embodiment, since some control signals exist in the IP core interface of the RapidIO controller, the system may be notified to perform RapidIO communication reset, for example, a physical layer link reset signal (phy _ link _ reset). Thus, the specific implementation manner of the step 1) may be as follows: and sending a reset control symbol to an opposite end which carries out RapidIO communication with the FPGA chip by enabling a physical layer link reset signal of the FPGA chip to be effective, and monitoring a port initialization process. Wherein, the phy _ link _ reset is an input port of the IP core of the RapidIO controller. As an example, a reset control symbol may be sent by a controller physical layer of the FPGA chip to an opposite end in RapidIO communication with the FPGA chip using an optical fiber, and a port initialization process may be monitored. It should be noted that the FPGA chip may be understood as a transmitting end of RapidIO communication, and an opposite end (which may also be an FPGA chip) thereof is a receiving end of RapidIO communication. The reason why the FPGA chip sends the reset control symbol to the opposite terminal here is to notify the opposite terminal to start the reset process, so that both communication parties start the reset process at the same time, and recovery of communication is ensured.

In step 2) of this embodiment, when the port initialization process is completed, the system reset signal of the FPGA chip is enabled in a preset number of clocks, and in the preset number of clocks, the connection with the opposite terminal is reestablished and the state machine of the FPGA chip is reset. After the port initialization process is completed (for example, after the port initialization completion signal port _ initialized is pulled low), the FPGA chip enables a system reset (sys _ rst) signal to be valid in a preset number of clocks, the preset number can be set according to actual needs, and the system reset (sys _ rst) is an input port of the RapidIO controller IP core. Because the IP core of the RapidIO controller is provided with a plurality of clock domains, a plurality of reset signals can be generated and output through the reset submodule when a system reset (sys _ rst) signal is effective so as to meet the time sequence requirement of each clock domain and ensure that the whole FPGA chip can be reset normally. Wherein, the port _ initialized is an output port of the IP core of the RapidIO controller.

In step 3) of this embodiment, the modules related to RapidIO communication include an encoding module, a decoding module, a First-In First-Out data storage, a buffer (FIFO), and the like, so as to ensure that no error occurs In subsequent two-party communication transmission logic.

Referring to fig. 2, the embodiment further includes, before step 1), a step of monitoring a status signal indicating an RapidIO communication interrupt, and if the status signal indicating the RapidIO communication interrupt is monitored to be valid, step 1) is skipped to be executed; and step 3) continuing to execute the step of monitoring the status signal for indicating RapidIO communication interruption after the execution is finished.

As shown in fig. 3, step 1) is preceded by the step of performing step 1) by jumping after the power-on reset of the first node. As can be seen from fig. 3, after the first node is powered on and reset, steps 1) to 3) need to be executed once to repair RapidIO communication blocking; then, a status signal for indicating RapidIO communication interruption is continuously monitored, and once the status signal for indicating RapidIO communication interruption is monitored to be effective, the steps 1) to 3) are skipped to be executed to repair RapidIO communication blockage; and after the step 3) is finished, the step of monitoring the status signal for indicating the RapidIO communication interruption is continuously executed to ensure that possible RapidIO communication blockage can be continuously repaired.

In this embodiment, the status signal for indicating the interruption of RapidIO communication is a port error signal (port _ error) or a single channel mode signal (mode _1 x), and may be other signals capable of indicating an abnormality of RapidIO communication. Because the Intellectual Property (IP) core interface of the RapidIO controller has corresponding error prompt when RapidIO communication is interrupted. Such as the port _ error port, is active indicating that the RapidIO communication interface has entered an uncorrectable error state. Or in a system using multi-fiber high-speed communication, mode _1x indicates that the link enters a single-channel communication (1 x) state for some reason, and the transmission speed is reduced to the carrying capacity of one fiber, obviously, the link enters an error state. The IP core interface is an interface of a digital circuit function module with modifiable parameters, both the port _ error and the mode _1x are output ports of an IP core of the RapidIO controller, and the IP core is preferably an IP core of Xilinx company.

In the embodiment of the invention, in an actual use scene, except that the communication is suspended in the communication process, the communication is restarted after a period of time; besides the conditions that the optical fiber line is subjected to strong vibration in the RapidIO communication process, RapidIO blockage caused by other conditions also exists. For example, in the process of RapidIO communication, a single end of a sending end and a receiving end is powered off or restarted, and communication cannot be established when all devices of RapidIO are powered on, that is, an FPGA chip participating in RapidIO communication needs to be powered on. In view of this situation, the same logic circuit (which may adopt an existing logic circuit structure) needs to be arranged at the transmitting end and the receiving end, so that both of them can be used as an active transmitting end for resetting the control symbol when powered on, and can be used as a passive end for responding to the reset handshake operation (i.e., a response message for indicating that the reset control symbol is received is fed back to the active transmitting end). In this embodiment, step 1) is preceded by monitoring an enable terminal of a logic circuit in the first node, where the logic circuit is configured to control triggering of RapidIO communication blocking repair, and if the enable terminal of the logic circuit is changed from an enable state to a disable state, the step 1) is executed by jumping.

It should be noted that, in the embodiment of the present invention, when the FPGA chip serving as the sending end of RapidIO communication monitors that the status signal for indicating RapidIO communication interruption is valid, it indicates that the RapidIO communication interruption between the FPGA chip and the opposite end of the communication is performed, at this time, the FPGA chip enables the opposite end to execute the reset process by sending the reset control symbol to the opposite end, and when it is monitored that the initialization process of the port of the FPGA chip is completed, the system reset signal is enabled to be valid in a preset number of clocks, and the connection is reestablished with the opposite end and the state machine of the FPGA chip and other modules related to RapidIO communication are reset, so that the reset process of the FPGA chip is completed. After the FPGA chip and the opposite end of the FPGA chip are reset, the communication process of the two parties can be restarted, and the communication of the two parties can be recovered, so that the effect of effectively solving the RapidIO communication blocking problem is achieved. It should be noted that, in a case where communication is suspended during RapidIO communication and communication is resumed after a lapse of time, the sender needs to start a reset mechanism by using internal logic at the time when the communication is just suspended. Aiming at the condition that the optical fiber line is subjected to strong vibration and cannot communicate in the RapidIO communication process, the sending end monitors that a status signal for indicating the interruption of RapidIO communication is effective.

In this embodiment, the opposite end serves as the receiving end of the FPGA chip, and after receiving the reset control symbol, the receiving end detects that the physical layer of the receiving end receives the reset control symbol effectively, and then starts to execute the reset process in synchronization with the FPGA chip of the transmitting end. It should be noted that the reset process of the receiving end is the same as that of the FPGA chip at the transmitting end. That is, the receiving end makes the system reset signal of the receiving end valid in a preset number of clocks, and in the preset number of clocks, reestablishes a connection with the sending end and resets the state machine of the receiving end and all other modules (such as a decoding module, a FIFO and the like) related to RapidIO communication in the receiving end, thereby ensuring that no error occurs in the subsequent communication transmission logic of both parties. Wherein, phy _ rcvd _ link _ reset is an output port of the RapidIO controller IP core. In this embodiment, after the reset control symbol is sent in step 1), the following processing steps of the second node are also included:

s1) the second node detects the reset control symbol received by the physical layer, if the physical layer receives the effective reset control symbol, the next step is executed;

s2) making the system reset signal of the second node valid within a preset number of clocks, reestablishing a connection with the first node within the preset number of clocks, and resetting the state machine of the second node;

s3) controls all modules related to RapidIO communication in the second node to reset.

In addition, the present embodiment also provides a RapidIO communication blockage repair system, which includes a first node and a second node that perform RapidIO communication, where the first node and the second node are programmed or configured to execute the steps of the foregoing RapidIO communication blockage repair method.

In addition, the present embodiment also provides a RapidIO communication blockage repair system, which includes a first node and a second node that perform RapidIO communication, and a memory of the first node and the second node stores program firmware that is programmed or configured to execute the foregoing RapidIO communication blockage repair method.

Furthermore, the present embodiment also provides a computer-readable storage medium having stored therein a computer program programmed or configured to execute the RapidIO communication congestion repair method.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein. The present application is directed to methods, apparatus (systems), and computer program products according to embodiments of the application wherein instructions, which execute via a flowchart and/or a processor of the computer program product, create means for implementing functions specified in the flowchart and/or block diagram block or blocks. These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.