Relaxation oscillator with aging effect reduction technique
阅读说明：本技术 具有老化效应降低技术的张弛振荡器 (Relaxation oscillator with aging effect reduction technique ) 是由 大仓铁郎 于 2018-11-27 设计创作，主要内容包括：一种具有老化效应降低技术的张弛振荡器,其包括：比较器(CP),其中其输入侧(CP1、CP2)耦接到包括至少一个电容器(C、C1、C2)的网络；多个晶体管(M1、M2、M3、M4)；以及多个可控开关(SW11、…、SW8、SW111、…、SW180)。张弛振荡器使用一种切换方法,使得电流/电压发生器的晶体管和电流镜晶体管的作用通过张弛振荡器的输出信号而周期性地交换。对电流/电压发生器与电流镜晶体管之间的工作点的失配的降低实现了由老化效应所引起的频率退化的减少。(A relaxation oscillator with aging effect reduction techniques, comprising: a Comparator (CP) with its input side (CP1, CP2) coupled to a network comprising at least one capacitor (C, C1, C2); a plurality of transistors (M1, M2, M3, M4); and a plurality of controllable switches (SW11, …, SW8, SW111, …, SW 180). The relaxation oscillator uses a switching method such that the roles of the transistors of the current/voltage generator and the current mirror transistors are periodically exchanged by the output signal of the relaxation oscillator. The reduction of the mismatch of the operating point between the current/voltage generator and the current mirror transistor achieves a reduction of the frequency degradation caused by aging effects.)
1. A relaxation oscillator with aging effect reduction technique, comprising:
-a Comparator (CP) having a first input node (CP1) and a second input node (CP2), wherein a reference signal (VRP, VRN, Vap, Van, Vdp, Vdn) is applied to at least one of the first and second input nodes (CP1, CP2) of the Comparator (CP),
-at least one capacitor (C, C1, C2) connected to at least one of the first and second input nodes (CP1, CP2) of the Comparator (CP),
a plurality of transistors (M1, M2, M3, M4) and a plurality of controllable switches (SW11, …, SW8, SW111, …, SW180),
-wherein the plurality of controllable switches (SW11, …, SW8, SW111, …, SW180) are controlled during an operation period (OC2) of the relaxation oscillator such that a charging current is generated that charges the at least one capacitor (C, C1, C2) and flows through at least a first transistor (M1) of the plurality of transistors; and causing generation of a reference current for providing a reference signal (VRP, VRN, Vap, Van, Vdp, Vdn), and the reference current flows through at least a second transistor (M2) of the plurality of transistors,
-wherein the plurality of controllable switches (SW11, …, SW8, SW111, …, SW180) are controlled during a subsequent operating period (OC3) of the relaxation oscillator such that a discharge current discharging the at least one capacitor (C, C1, C2) is generated and flows through at least a third transistor (M3) of the plurality of transistors; and causing generation of a reference current for providing a reference signal (VRP, VRN, Vap, Van, Vdp, Vdn), and the reference current flowing through at least a fourth transistor (M4) of the plurality of transistors.
2. Relaxation oscillator according to claim 1,
-wherein the Comparator (CP) comprises an output node (CP3) for providing an output signal (clk, clkn, clkp),
-wherein the controllable switches (SW11,.. cndot., SW8, SW111,.. cndot., SW180) are controlled by the output signals (clk, clkn, clkp) of the Comparators (CP).
3. A relaxation oscillator as claimed in claim 1 or 2, comprising:
a plurality of activatable reference current paths arranged between a supply potential (Vdd) and a reference potential (Vss),
-wherein the controllable switch (SW11,.. multidot.SW 8, SW111,.. multidot.SW 180) is configured to activate one of the activatable reference current paths such that a supply potential (Vdd) and a reference potential (Vss) are conductively connected through the activated reference current path and a reference current flows in the activated reference current path,
-wherein the controllable switch (SW11,.. multidot.SW 8, SW111,.. multidot.SW 180) is configured to deactivate the remaining part of the activatable reference current path such that a conductive connection between a supply potential (Vdd) and a reference potential (Vss) through the remaining part of the activatable reference current path is blocked,
-wherein the level of the reference signal depends on a reference current.
4. A relaxation oscillator as claimed in claim 3, comprising:
-a resistor (R),
-wherein the activatable reference current paths are arranged such that the resistor (R) is arranged in each of the activatable reference current paths,
-wherein the level of the reference signal depends on the voltage drop at the resistor (R).
5. A relaxation oscillator as claimed in claims 1 to 4, comprising:
a plurality of activatable charging current paths,
-wherein each of the activatable charging current paths is configured to conductively connect a supply potential (Vdd) to the at least one capacitor (C, C1, C2) to provide a charging current to charge the at least one capacitor (C, C1, C2) when a respective one of the activatable charging current paths is operating in an activated state,
-wherein each of the activatable charging current paths is configured to isolate a supply potential (Vdd) from the at least one capacitor (C, C1, C2) when the respective one of the activatable charging current paths is operating in a deactivated state.
6. A relaxation oscillator as claimed in claims 1 to 5, comprising:
a plurality of activatable discharge current paths,
-wherein each of the activatable discharge current paths is configured to conductively connect a reference potential (Vss) to the at least one capacitor (C, C1, C2) to provide a discharge current that discharges the at least one capacitor (C, C1, C2) when a respective one of the activatable discharge current paths is operating in an activated state,
-wherein each of the activatable discharge current paths is configured to isolate a reference potential (Vss) from the at least one capacitor (C, C1, C2) when a respective one of the activatable discharge current paths is operating in a deactivated state.
7. Relaxation oscillator of claims 1 to 6,
-wherein a second input node (CP2) of the Comparator (CP) is connectable to a first one of the reference signals (VRP) via a first one of the controllable switches (SW7),
-wherein a second input node (CP2) of the Comparator (CP) is connectable to a second one of the reference signals (VRN) via a second one of the controllable switches (SW 8).
8. A relaxation oscillator as claimed in claims 3 to 7,
-wherein a first of the plurality of activatable reference current paths comprises the at least one first transistor (M1), a third of the controllable switches (SW11), a fourth of the controllable switches (SW31) and the at least one third transistor (M3),
-wherein in an activated state of the first activatable reference current path the at least one first transistor (M1) is connected to a supply potential (Vdd) and to a resistor (R) through the third controllable switch (SW11),
-wherein, in an activated state of the first activatable reference current path, the at least one third transistor (M3) is connected to a reference potential (Vss) and to a resistor (R) through the fourth controllable switch (SW 31).
9. Relaxation oscillator of claims 6 to 8,
-wherein a first activatable discharge current path of the plurality of activatable discharge current paths comprises the at least one fourth transistor (M4) and a fifth controllable switch (SW42),
-wherein in an activated state of the first discharging current path the at least one fourth transistor (M4) is connected to a reference potential (Vss) and to the at least one capacitor (C) through the fifth controllable switch (SW 42).
10. Relaxation oscillator of claims 3 to 9,
-wherein a second one of the plurality of activatable reference current paths comprises the at least one second transistor (M2), the fourth controllable switch (SW31), a sixth one of the controllable switches (SW21) and the at least one third transistor (M3),
-wherein in an activated state of the second activatable reference current path the at least one second transistor (M2) is connected to a supply potential (Vdd) and to a resistor (R) through the sixth controllable switch (SW21),
-wherein, in an activated state of the second activatable reference current path, the at least one third transistor (M3) is connected to a reference potential (Vss) and to a resistor (R) through the fourth controllable switch (SW 31).
11. Relaxation oscillator according to claims 5 to 10,
-wherein a first activatable charging current path of the plurality of activatable charging current paths comprises the at least one first transistor (M1) and a seventh controllable switch (SW12),
-wherein, in an activated state of the first activatable charging current path, the at least one first transistor (M1) is connected to a supply potential (Vdd) and to the at least one capacitor (C) through the seventh controllable switch (SW 12).
12. Relaxation oscillator of claims 3 to 11,
-wherein a third one of the plurality of activatable reference current paths comprises the at least one second transistor (M2), the sixth controllable switch (SW21), an eighth one of the controllable switches (SW41) and the at least one fourth transistor (M4),
-wherein in an activated state of the third activatable reference current path the at least one second transistor (M2) is connected to a supply potential (Vdd) and to a resistor (R) through the sixth controllable switch (SW21),
-wherein, in an activated state of the third activatable reference current path, the at least one fourth transistor (M4) is connected to a reference potential (Vss) and to a resistor (R) through the eighth controllable switch (SW 41).
13. Relaxation oscillator according to claims 6 to 12,
-wherein a second one of the plurality of activatable discharge current paths comprises the at least one third transistor (M3) and a ninth one of the controllable switches (SW32),
-wherein, in an activated state of the second activatable discharging current path, the at least one third transistor (M3) is connected to a reference potential (Vss) and is connected to the at least one capacitor (C) through the ninth controllable switch (SW 32).
14. Relaxation oscillator according to claims 3 to 12,
-wherein a fourth activatable reference current path of the plurality of activatable reference current paths comprises the at least one first transistor (M1), the third controllable switch (SW11), the eighth controllable switch (SW41) and the at least one fourth transistor (M4),
-wherein in an activated state of the fourth activatable reference current path the at least one first transistor (M1) is connected to a supply potential (Vdd) and through the third controllable switch (SW11) to a resistor (R),
-wherein, in an activated state of the fourth activatable reference current path, the at least one fourth transistor (M4) is connected to a reference potential (Vss) and to a resistor (R) through the eighth controllable switch (SW 41).
15. Relaxation oscillator according to claims 5 to 14,
-wherein a second one of the plurality of activatable charging current paths comprises the at least one second transistor (M2) and a tenth one of the controllable switches (SW22),
-wherein in an activated state of the second activatable charging current path the at least one second transistor (M2) is connected to a supply potential (Vdd) and to the at least one capacitor (C) through the tenth controllable switch (SW 22).
Technical Field
The present disclosure relates to a relaxation oscillator having aging effect reduction technique by reducing Channel Hot Carrier (CHC) effect.
Background
The performance of relaxation oscillators typically degrades during the operation time of the oscillator due to frequency degradation caused by aging effects, in particular by hot channel carrier injection (HCI) and Negative Bias Temperature Instability (NBTI). The relaxation oscillator comprises a comparator, the input side of which is coupled to the network of transistors. The transistors implement a reference current/voltage generator and a current mirror. In a very small area of technology, channel hot carrier injection causes threshold voltage shifts in the oscillator circuit. This aging effect leads to frequency degradation in the relaxation oscillator circuit.
Frequency changes caused by comparator offset degradation can be eliminated by periodically switching the positive and negative input node connections of the comparator from the ramp signal to the reference voltage.
The use of auto-zero comparators to achieve reduction of aging effects on comparators in Relaxation oscillators is described by k.chord, o.bernal, d.nuttman and m.je in "a Precision release Oscillator with aspect-locked Offset-Cancellation Scheme for displayable biological SoCs," IEEEISSCC dig. Auto-zeroing is used to eliminate degradation pertaining to comparator offsets.
A further cause of frequency degradation is related to the mismatch of the operating point between the transistors of the reference current/voltage generator and the current mirror transistors. However, the degradation caused by the mismatch of the operating point between the transistors of the reference current/voltage generator and the current mirror transistors cannot be eliminated.
It is desirable to provide a relaxation oscillator with aging effect reduction technique that is capable of reducing the mismatch of the operating point between the current/voltage generator and the current mirror transistor to achieve a reduction of frequency degradation caused by aging effects, in particular by channel hot carrier injection.
An embodiment of a relaxation oscillator with aging effect reduction technique to reduce the mismatch of the operating point between the current/voltage generator and the current mirror transistor of the relaxation oscillator is described in claim 1.
The relaxation oscillator comprises a comparator having a first input node and a second input node, wherein a reference signal is applied to at least one of the first input node and the second input node. The relaxation oscillator includes: at least one capacitor connected to at least one of the first input node and the second input node of the comparator; as well as a plurality of transistors and a plurality of controllable switches.
Controlling the plurality of controllable switches during an operational period of the relaxation oscillator such that a charging current is generated that charges the at least one capacitor and flows through at least a first transistor of the plurality of transistors; and causing a reference current to be generated for providing the reference signal and to flow through at least a second one of the transistors.
Controlling the plurality of controllable switches during a subsequent operational period of the relaxation oscillator such that a discharge current discharging the at least one capacitor is generated and flows through at least a third transistor of the plurality of transistors; and causing a reference current to be generated that provides the reference signal and to flow through at least a fourth one of the transistors.
According to an embodiment of the relaxation oscillator, the comparator comprises an output node for providing an output signal, e.g. a clock signal. The controllable switch of the relaxation oscillator is controlled by the output signal/clock signal of the comparator.
The relaxation oscillator uses a switching method to improve the frequency accuracy of the relaxation oscillator by reducing channel hot carrier effects. In the switching method, the roles of the transistors of the current/voltage generator and the current mirror transistors are periodically exchanged by relaxation of the output/clock signal of the oscillator itself.
The accompanying drawings are included to provide a further understanding, and are incorporated in and constitute a part of this specification. The drawings illustrate several embodiments of relaxation oscillators and, together with the description, serve to explain the principles and operations of the various embodiments.
Drawings
Figure 1 shows an embodiment of a relaxation oscillator with frequency degradation caused by a mismatch of the operating point between the transistors of the reference current/voltage generator and the current mirror transistors;
figure 2 shows another embodiment of a relaxation oscillator with frequency degradation caused by a mismatch of the operating point between the transistors of the reference current/voltage generator and the current mirror transistors;
figure 3A illustrates an embodiment of a relaxation oscillator with improved frequency accuracy by reducing channel hot carrier effects;
figure 3B shows a timing diagram illustrating the operation of the relaxation oscillator of figure 3A;
figure 4A illustrates another embodiment of a relaxation oscillator with improved frequency accuracy by reducing channel hot carrier effects;
figure 4B shows a timing diagram illustrating the operation of the relaxation oscillator of figure 4A;
figure 5A illustrates an embodiment of a relaxation oscillator with improved frequency accuracy by reducing channel hot carrier effects; and
fig. 5B shows a timing diagram illustrating the operation of the relaxation oscillator of fig. 5B.
Detailed Description
Fig. 1 shows an embodiment of a relaxation oscillator 1, which generates output/clock signals clk, clkb. The relaxation oscillator 1 comprises a comparator circuit CP having an input node CP1 for applying an input signal VIP and an input node CP2 for applying an input signal VIM. The first reference signal VRP and the second reference signal VRN can be applied to the input node CP2 through controllable switches SW7 and SW8 controlled by the output/clock signals clk, clkb. The input node CP1 of the comparator circuit CP is connected to the capacitor C.
The first reference signal VRP and the second reference signal VRN are generated by a current/voltage generator including transistors M1 and M3 and a resistor R. The reference signal VRP is provided at the control/gate terminal of transistor M1. The reference signal VRN is provided at the control/gate terminal of transistor M3. The capacitor C may be charged by connecting the capacitor C to the transistor M2 via the
Fig. 2 shows another embodiment of a
The ramp signal Vap may be applied to the input node CP1 of the comparator circuit by coupling the input node CP1 to a potential Vcp via a controllable switch SW 150. The reference signal VR may be applied to the input node CP1 of the comparator circuit by coupling the input node CP1 to a potential VR via a controllable switch SW 170. The ramp signal Van may be applied to the input node CP2 of the comparator circuit by coupling the input node CP2 to the potential Vcn via the controllable switch SW160, or by coupling the input node CP2 to the potential VR via the controllable switch SW 180.
In nanoscale processes, Channel Hot Carriers (CHC) cause degradation of the threshold voltages of NMOS and PMOS transistors. The effect of CHC is shown as
Wherein Vgs、Vds、VdsatAnd L is the gate-source voltage, drain-source saturation voltage and channel length. The embodiments of relaxation oscillators of figures 1 and 2 show the difference between the average drain-source voltage of the transistors of the reference generator and the current source. Therefore, degradation of the oscillation frequency occurs in the embodiments of fig. 1 and 2.
With respect to the oscillator circuit 1 shown in fig. 1, the reference voltage is represented as:
VRP-VRN＝[Id+Δ(t)]·R，
wherein IdAnd Δ (t) are the initial drain current of transistor M1/M3 and the drain current degradation caused by the CHC effect, respectively.
The drain-source currents of transistors M2 and M4 are represented as:
IdM2＝Id+Δ(t)+Δ2(t) and
IdM4＝Id+Δ(t)+Δ4(t)，
wherein Δ2(t) and. DELTA.4(t) is the drain current degradation of transistor M2 and transistor M4, respectively.
The clock cycle is:
therefore, the oscillation frequency is expressed by the following equation:
with respect to the
VR＝[IdMR+ΔR(t)]·R，
wherein IdMRAnd ΔR(t) is the initial drain current of transistor MR and the drain current degradation caused by the CHC effect, respectively.
The drain-source currents of transistors M1 and M2 are represented as:
IdM1＝IdMR+Δ(t)+Δ1(t) and
IdM2＝IdMR+Δ(t)+Δ2(t)，
wherein Δ1(t) and. DELTA.2(t) is the drain current degradation of transistors M1 and M2, respectively.
The clock cycle is:
thus, the oscillation frequency of the oscillator circuit of fig. 2 is represented by the following equation:
for both embodiments of
Fig. 3A, 4A and 5A show different embodiments of
According to the embodiments of the relaxation oscillator shown in fig. 3A, 4A and 5A, the relaxation oscillator comprises a comparator CP having a first input node CP1 and a second
Referring to fig. 3A, a relaxation oscillator includes a plurality of transistors M1, M2, M3, M4 and a plurality of controllable switches SW 11. The plurality of controllable switches are controlled during an operating period of the relaxation oscillator, e.g. the operating period OC2 shown in fig. 3B, such that the charging current charging the capacitor C flows through the transistor M1 and the controllable switch SW5, and the charging current and the reference signals/voltages VRP and VRN are generated by the transistors M2 and M3 and the resistor R.
The plurality of controllable switches are controlled during a subsequent operating period of the relaxation oscillator, e.g. the operating period OC3 shown in fig. 3B, such that a discharge current discharging the capacitor C flows through the transistor M3 and the controllable switch SW6, and the discharge current and the reference signals/voltages VRP, VRN are generated by the transistors M2 and M4 and the resistor R.
Referring to fig. 4A and 5A, the relaxation oscillator includes a plurality of transistors M1, M2 and a plurality of controllable switches SW111, the. During the operating period of the relaxation oscillator, e.g. the operating period clkp 1 shown in fig. 4B/5B, the plurality of controllable switches are controlled such that the charging current charging the capacitor C2 flows through the transistor M2 and the controllable switch SW112 and the reference current and the reference signal/voltage VR are generated by the transistor M1 and the resistor R. On the other hand, the capacitor C1 is discharged by the controllable switch SW 130.
During a subsequent operating cycle of the relaxation oscillator, e.g. the operating cycle clkn-1 shown in fig. 4B/5B, the plurality of controllable switches are controlled such that the charging current charging the capacitor C1 flows through the transistor M1 and the controllable switch SW112 and the reference current and the reference signal/voltage VR are generated by the transistor M2 and the resistor R. On the other hand, the capacitor C2 is discharged by the controllable switch SW 140.
The comparator CP includes output nodes CP3 (fig. 3A) or CP3A, CP3b (fig. 4A and 5A) to provide output signals clk (fig. 3A) or clkn, clkp (fig. 4A and 5A). The controllable switches of the relaxation oscillators of fig. 3A, 4A and 5A are controlled by the output signals clk or clkn, clkp of the comparator CP. The respective output signals controlling the controllable switches are written directly into the respective controllable switches in fig. 3A, 4A and 5A.
The output/clock signals clk, clkhn, and clkhp may have a high/1 level or a low/0 level. When one of the controllable switches is controlled by the associated output/clock signal having a high/1 level, the respective controllable switch transitions to a closed state, i.e. to a conductive state. When one of the controllable switches is controlled by the associated output/clock signal having a low/0 level, the respective controllable switch is switched to the off-state, i.e. to the non-conductive state.
The relaxation oscillator shown in fig. 3A, 4A and 5A comprises a plurality of activatable reference current paths arranged between a supply potential Vdd and a ground potential Vss. The controllable switch is configured to activate one of the activatable reference current paths such that the supply potential Vdd and the ground potential Vss are conductively connected through the activated reference current path and a reference current flows in the activated reference current path.
The controllable switch is configured to deactivate the remaining part of the activatable reference current path such that a conductive connection between the supply potential (Vdd) and the ground potential (Vss) through the remaining part of the activatable reference current path is blocked. The level of the reference signal depends on the reference current, which flows in the activated reference current path.
The relaxation oscillator in figures 3A, 4A and 5A comprises a resistor R. The activatable reference current paths are arranged such that a resistor R is arranged in each of the activatable reference current paths. The level of the reference signal depends on the voltage drop at the resistor R.
The relaxation oscillator shown in figures 3A, 4A and 5A comprises a plurality of activatable charging current paths. Each of the activatable charging current paths is configured to conductively connect the supply potential Vdd to at least one capacitor C (fig. 3A) or C1, C2 (fig. 4A and 5A) to provide a charging current to charge the at least one capacitor C or C1, C2 when the respective one of the activatable charging current paths is operating in an activated state. Each of the activatable charging current paths is configured to isolate the supply potential Vdd from the at least one capacitor C or C1, C2 when the respective one of the activatable charging current paths is operating in the deactivated state.
The relaxation oscillator shown in fig. 3A, 4A and 5A comprises a plurality of activatable discharge current paths. Each of the activatable discharge current paths is configured to conductively connect a ground potential Vss to at least one capacitor C (fig. 3A) or C1, C2 (fig. 4A and 5A) to provide a discharge current to discharge the at least one capacitor C or C1, C2 when a respective one of the activatable discharge current paths is operating in an activated state. In the embodiment of fig. 4A/5A, the capacitor C1 or C2 is directly reset to ground potential Vss by the controllable switch SW130 or SW 140. Each of the activatable discharge current paths is configured to isolate the ground potential Vss from the at least one capacitor C or C1, C2 when the respective one of the activatable discharge current paths is operating in the deactivated state.
Fig. 3A shows a first embodiment of a relaxation oscillator 3 with improved frequency accuracy by reducing channel hot carrier effects. According to an embodiment of the relaxation oscillator 3, the second input node CP2 of the comparator CP is connectable to the first one of the reference signals VRP via a
A first activatable reference current path of the plurality of activatable reference current paths includes at least one first transistor M1, a controllable switch SW11, a controllable switch SW31, and at least one third transistor M3. In the activated state of the first activatable reference current path, the at least one first transistor M1 is connected to the supply potential Vdd and via the controllable switch SW11 to the resistor R. In the activated state of the first activatable reference current path, the at least one third transistor M3 is connected to ground potential Vss and, via the controllable switch SW31, to the resistor R.
A first of the plurality of activatable discharge current paths comprises at least one fourth transistor M4 and a controllable switch SW 42. In the activated state of the first discharge current path, the at least one fourth transistor M4 is connected to ground potential Vss and to the at least one capacitor C via the controllable switch SW 42.
A second of the plurality of activatable reference current paths comprises at least one second transistor M2, a controllable switch SW31, a controllable switch SW21 and at least one third transistor M3. In the activated state of the second activatable reference current path, the at least one second transistor M2 is connected to the supply potential Vdd and via the controllable switch SW21 to the resistor R. In the activated state of the second activatable current path, the at least one third transistor M3 is connected to ground potential Vss and, via the controllable switch SW31, to the resistor R.
A first activatable charging current path of the plurality of activatable charging current paths comprises at least one first transistor M1 and a controllable switch SW 12. In the activated state of the first activatable charging current path, the at least one first transistor M1 is connected to the supply potential Vdd and via the controllable switch SW12 to the at least one capacitor C.
A third activatable reference current path of the plurality of activatable reference current paths comprises at least one second transistor M2, a controllable switch SW21, a controllable switch SW41 and at least one fourth transistor M4. In the activated state of the third activatable reference current path, the at least one second transistor M2 is connected to the supply potential Vdd and via the controllable switch SW21 to the resistor R. In the activated state of the third activatable reference current path, the at least one fourth transistor M4 is connected to ground potential Vss and, via the controllable switch SW41, to the resistor R.
A second of the plurality of activatable discharge current paths comprises at least one third transistor M3 and a controllable switch SW 32. In the activated state of the second activatable discharge current path, the at least one third transistor M3 is connected to ground potential Vss and via the controllable switch SW32 to the at least one capacitor C.
A fourth reference current path of the plurality of activatable reference current paths comprises at least one first transistor M1, a controllable switch SW11, a controllable switch SW41 and at least one fourth transistor M4. In the activated state of the fourth activatable reference current path, the at least one first transistor M1 is connected to the supply potential Vdd and via the controllable switch SW11 to the resistor R. In the activated state of the fourth activatable reference current path, the at least one fourth transistor M4 is connected to the ground potential Vss and, via the controllable switch SW41, to the resistor R.
A second activatable charging current path of the plurality of activatable charging current paths includes at least one second transistor M2 and a controllable switch SW 22. In the second activatable charging current path activation state, the at least one second transistor M2 is connected to the supply potential Vdd and via the controllable switch SW22 to the at least one capacitor C.
The operation of the relaxation oscillator of figure 3A is described below with reference to the timing diagram of figure 3B.
As shown in fig. 3B, during the operation period OC1, the output/clock signals clk, clkhn, and clkhp have a high/1 level. Since the controllable switches SW42 and SW6 are switched to a conducting state, the drain node of the transistor M4 is connected to the capacitor C and the positive input node CP1 of the comparator CP. The capacitor C is discharged by the drain current of the transistor M4. The reference voltages VRP, VRN and the reference current are generated by transistors M1, M3 and resistor R. During the operating period OC1, the reference current path is activated by switching the controllable switches SW11 and SW31 to a conducting state by the high levels of the output signals clkhp and clkp.
Once the voltage of the positive input node CP1 of the comparator CP becomes lower than VRN, the output/clock signals clk and clkhp transition to a low/0 level during the
After the potential VIP at the input node CP1 of the comparator becomes greater than the potential VRP, the output/clock signals clk and clkhn transition to high/1 and low/0 levels, respectively, during the operation period OC 3. Thus, the controllable switches SW32 and SW6 switch to a conducting state and the drain current of transistor M3 discharges the capacitor C. The potential/reference signal VRN and the reference current are generated by operating the reference current path including the transistors M2, M4 and the resistor R in an active state by switching the controllable switches SW21 and SW41 to a conductive state.
During the operation period OC4, when the potential VIP at the input node CP1 of the comparator CP reaches the potential VRN applied to the input node CP2 of the comparator CP, the clock/output signals clk and clkhp transition to a low/0 level and a high/1 level, respectively. At this stage, the reference voltage and current are generated by operating the reference current path including transistor M1M4 and resistor R in the active state. To this end, the controllable switches SW11 and SW41 are switched to the conducting state. The capacitor C is charged by an activated charging path comprising a transistor M2 connected to the capacitor C through closed controllable switches SW22 and
The relaxation oscillator uses the number of charges and discharges of the capacitor to generate the output/clock signal. Controllable switches SW11, SW12, SW21 and SW22 periodically swap the roles of transistors M1 and M2. In a similar manner, the roles of transistors M3 and M4 are swapped by controllable switches SW31, SW32, SW41 and SW 42.
By the above behavior, each average drain-source voltage of the transistors M1 and M2(M3 and M4) becomes the same. The degradation of the drain current of a transistor caused by CHC depends on the drain-source voltage. Therefore, the drain current of the transistor M1(M3) degrades by aging as in the transistor M2 (M4). The frequency degradation of the relaxation oscillator caused by the mismatch between each of the average drain-source voltages of the transistors M1(M3) and M2(M4) can be eliminated.
Fig. 4A shows another embodiment of a relaxation oscillator 4 with improved frequency accuracy by reducing channel hot carrier effects. Relaxation oscillator 4 generates output/clock signals clkn, clkp. The oscillator 4 comprises a comparator CP having input nodes CP1 and
Relaxation oscillator 4 comprises a current/voltage generator comprising transistors M1 and M2 and a resistor R. The capacitor C1 may be charged through a charging current path comprising a transistor M1 and a controllable switch SW112, which is controlled by an output/clock signal clkn. The capacitor C1 is discharged through a controllable switch SW130 controlled by the output/clock signal clkp. The capacitor C2 may be charged through a charging current path comprising a transistor M2 and a controllable switch SW122, which is controlled by the output/clock signal clkp. The capacitor C2 can be discharged through a controllable switch SW140 controlled by the output/clock signal clkn.
The reference potential VR is generated by the voltage drop at the resistor R. The reference current through resistor R can be generated by a reference current path comprising a transistor M1 and a controllable switch SW111 controlled by the output/clock signal clkp. Furthermore, the reference current through the resistor R may be generated by a further reference current path comprising a transistor M2 and a controllable switch SW121 controlled by the output/clock signal clkn.
The reference signal VR can be applied to one of the input nodes CP1, CP2 of the comparator CP via controllable switches SW170 and SW 180. The input node CP1 of the comparator CP can be coupled to a capacitor C1 to apply an input signal/potential Vcp by means of a controllable switch SW150 controlled by an output/clock signal clkn. The input node CP2 of the comparator CP may be coupled to a capacitor C2 to apply an input signal/potential Vcn by means of a controllable switch SW160 controlled by an output/clock signal clkp. The signal Vcp will be compared with the signal VR by the comparator CP.
Fig. 4B shows a timing diagram of the potentials and output/clock signals for controlling the controllable switches of the relaxation oscillator 4 to illustrate the operation of the relaxation oscillator.
Fig. 4A shows the configuration of relaxation oscillator 4 when output/clock signal clkp has a low/0 level and output/clock signal clkn has a high/1 level. The reference current path, including transistor M2 and resistor R activation, generates a reference current and a reference voltage VR. The drain-source current of the transistor M1 charges the capacitor C until the potential Vcp becomes greater than the potential VR. Capacitor C2 is discharged by the closed controllable switch SW 140.
Once the potential Vcp becomes larger than the potential VR, the output/clock signals clkp and clkn change their levels so that the output/clock signal clkp has a high/1 level and the output/clock signal clkn has a low/0 level. In this phase of operation, the reference current path including transistor M1 and resistor R is activated to generate the reference current and voltage VR, and the drain-source current of transistor M2 charges capacitor C2. Capacitor C1 is discharged by the closed controllable switch SW 130.
With regard to relaxation oscillator 4, reference voltage VR is represented as:
VRclkp＝0＝ldM2.R(@clkp＝0)，
VRclkp＝1＝IdM1·R(@clkp＝1)。
because the switches are switched, the CHC effect of transistors M1 and M2 is identical. Thus, I after agingdM1And IdM2The relationship between them is:
IdM1＝IdM2。
the clock period and oscillation frequency are expressed as:
f≈1/2CR。
the oscillation frequency does not include the CHC effect. Each average voltage of the positive input node and the negative node of the comparator becomes the same voltage by the periodic exchange of the switches SW150, SW160, SW170, and SW 180. Furthermore, the average drain-source voltage of transistor M1 becomes the same as the average drain-source voltage of transistor M2 through controllable switches SW111 and SW 121.
Fig. 5A shows another embodiment of a
The embodiment of
Reference numerals
1. .., 5 relaxation oscillator embodiments
CP comparator
Input node of CP1 and CP2 comparators
Output nodes of CP3, CP3a, CP3b comparators
CD clock frequency divider
C. C1, C2 capacitor
SWxx controllable switch
M1, … and M4 transistors
R resistor
clk output/clock signal
clkb inverted output/clock signal
- 上一篇：一种医用注射器针头装配设备
- 下一篇：用于生成随机比特样本的方法和系统