阅读说明：本技术 半导体存储装置及其控制方法 (Semiconductor memory device and control method thereof ) 是由 木村啓太 滋贺秀裕 于 2019-08-05 设计创作，主要内容包括：本发明涉及一种半导体存储装置及其控制方法。根据一实施方式,半导体存储装置具备：存储器晶体管；第1布线,连接在存储器晶体管的栅极电极；以及控制装置,进行从存储器晶体管读出数据的读出动作及将数据写入存储器晶体管的写入动作。控制装置从读出动作或写入动作的第1时序至第2时序,使第1布线的电压增大至第1电压为止,并对应于从第1时序至第2时序为止的第1布线的电压、电流及电荷量的至少一者,调整从第1时序至第2时序为止的长度。(The present invention relates to a semiconductor memory device and a control method thereof. According to one embodiment, a semiconductor memory device includes: a memory transistor; a 1 st wiring connected to a gate electrode of the memory transistor; and a control device for performing a read operation for reading data from the memory transistor and a write operation for writing data into the memory transistor. The control device increases the voltage of the 1 st wiring to the 1 st voltage from the 1 st timing to the 2 nd timing of the read operation or the write operation, and adjusts the length from the 1 st timing to the 2 nd timing in accordance with at least one of the voltage, the current, and the charge amount of the 1 st wiring from the 1 st timing to the 2 nd timing.)

1. A semiconductor memory device includes:

a memory transistor;

a 1 st wiring connected to a gate electrode of the memory transistor; and

a control device for performing a read operation for reading data from the memory transistor and a write operation for writing data into the memory transistor;

the control device increases the voltage of the 1 st wiring to the 1 st voltage from the 1 st timing to the 2 nd timing of the read operation or the write operation,

and adjusting a length from the 1 st timing to the 2 nd timing in accordance with at least one of a voltage, a current, and a charge amount of the 1 st wiring from the 1 st timing to the 2 nd timing.

2. The semiconductor memory device according to claim 1, wherein the read operation is a write verification operation performed at the time of the write operation or an erase verification operation performed at the time of an erase operation.

3. The semiconductor memory device according to claim 1, wherein the control means, in the read operation:

increasing the voltage of the 1 st wiring to the 1 st voltage from the 1 st timing to the 2 nd timing;

reducing the voltage of the 1 st wiring from the 2 nd timing to the 3 rd timing to a 2 nd voltage; and is

Setting a length from the 1 st sequence to the 2 nd sequence to a 1 st length when the voltage of the 1 st wiring in the 1 st sequence is a 1 st initial voltage, and

setting a length from the 1 st sequence to the 2 nd sequence to a 2 nd length when the voltage of the 1 st wiring in the 1 st sequence is a 2 nd initial voltage smaller than the 1 st initial voltage,

the control means sets the 2 nd length to be larger than the 1 st length.

4. The semiconductor memory device according to claim 1, wherein the control means, in the read operation:

increasing the voltage of the 1 st wiring to the 1 st voltage from the 1 st timing to the 2 nd timing;

reducing the voltage of the 1 st wiring from the 2 nd timing to the 3 rd timing to a 2 nd voltage; and is

The length from the 1 st sequence to the 2 nd sequence is set as the 1 st length when the maximum value of the speed of the voltage increase of the 1 st wiring from the 1 st sequence to the 2 nd sequence is the 1 st speed, and

when the length from the 1 st sequence to the 2 nd sequence when the maximum value of the speed of voltage increase of the 1 st wiring from the 1 st sequence to the 2 nd sequence is the 2 nd speed smaller than the 1 st speed is set as the 2 nd length,

the control means sets the 2 nd length to be larger than the 1 st length.

5. The semiconductor memory device according to claim 1, wherein the control means, in the write operation:

increasing the voltage of the 1 st wiring to the 1 st voltage from the 1 st timing to the 2 nd timing;

increasing the voltage of the 1 st wiring to the 2 nd voltage from the 2 nd timing to the 3 rd timing; and is

Setting a length from the 1 st sequence to the 2 nd sequence to a 1 st length when the voltage of the 1 st wiring in the 1 st sequence is a 1 st initial voltage, and

setting a length from the 1 st sequence to the 2 nd sequence to a 2 nd length when the voltage of the 1 st wiring in the 1 st sequence is a 2 nd initial voltage smaller than the 1 st initial voltage,

the control means sets the 2 nd length to be larger than the 1 st length.

6. The semiconductor memory device according to claim 1, wherein the control means increases the voltage of the 1 st wiring to the 1 st voltage in the 1 st timing to the 2 nd timing of the write operation,

the length from the 1 st sequence to the 2 nd sequence is set as the 1 st length when the maximum value of the speed of the voltage increase of the 1 st wiring from the 1 st sequence to the 2 nd sequence is the 1 st speed, and

when the length from the 1 st sequence to the 2 nd sequence when the maximum value of the speed of voltage increase of the 1 st wiring from the 1 st sequence to the 2 nd sequence is the 2 nd speed smaller than the 1 st speed is set as the 2 nd length,

the control means sets the 2 nd length to be larger than the 1 st length.

7. The semiconductor memory device according to claim 6, wherein the control means increases the voltage of the 1 st wiring to the 2 nd voltage in the sequence from the 2 nd sequence to the 3 rd sequence of the write operation,

the length from the 2 nd sequence to the 3 rd sequence is set as the 3 rd length when the maximum value of the speed of the voltage increase of the 1 st wiring from the 2 nd sequence to the 3 rd sequence is the 3 rd speed, and

when the length from the 2 nd sequence to the 3 rd sequence when the maximum value of the speed of voltage increase of the 1 st wiring from the 2 nd sequence to the 3 rd sequence is the 4 th speed smaller than the 3 rd speed is set as the 4 th length,

the control means sets the 3 rd length to be larger than the 4 th length.

8. The semiconductor memory device according to claim 1, comprising:

a peripheral circuit connected to the 1 st wiring; and

a pad electrode connected to the peripheral circuit and capable of supplying a power supply voltage to the peripheral circuit; and is

The peripheral circuit includes:

a voltage output circuit including an output terminal connected to the 1 st wiring, the voltage output circuit being capable of outputting a voltage greater than the power supply voltage to the output terminal;

a voltage divider circuit connected to an output terminal of the voltage output circuit; and

and the comparison circuit is connected with the voltage division circuit.

9. The semiconductor memory device according to claim 1, comprising:

a peripheral circuit connected to the 1 st wiring; and

a pad electrode connected to the peripheral circuit and capable of supplying a power supply voltage to the peripheral circuit; and is

The peripheral circuit includes:

a voltage output circuit including an output terminal connected to the 1 st wiring, the voltage output circuit being capable of outputting a voltage greater than the power supply voltage to the output terminal;

a current mirror circuit connected to an output terminal of the voltage output circuit;

a 1 st switching circuit connected to the current mirror circuit; and

and the comparison circuit is connected to the 1 st switching circuit.

10. The semiconductor memory device according to claim 8, comprising:

a substrate having a 1 st region and a 2 nd region;

a plurality of memory blocks provided in a 1 st region of the substrate, arranged in a 1 st direction, and including the memory transistors and the 1 st wiring;

a 2 nd switch circuit provided in a 1 st region of the substrate and aligned with the plurality of memory blocks in a 2 nd direction intersecting the 1 st direction;

the voltage output circuit is arranged in the 2 nd area of the substrate and is connected with the plurality of storage blocks through the 2 nd switch circuit; and

the comparison circuit is arranged in the No. 2 area of the substrate.

11. The semiconductor memory device according to claim 9, comprising:

a substrate having a 1 st region and a 2 nd region;

a plurality of memory blocks provided in a 1 st region of the substrate, arranged in a 1 st direction, and including the memory transistors and the 1 st wiring;

a 2 nd switch circuit provided in a 1 st region of the substrate and aligned with the plurality of memory blocks in a 2 nd direction intersecting the 1 st direction;

the voltage output circuit is arranged in the 2 nd area of the substrate and is connected with the plurality of storage blocks through the 2 nd switch circuit; and

the comparison circuit is arranged in the No. 2 area of the substrate.

12. A method for controlling a semiconductor memory device, the semiconductor memory device comprising:

a memory transistor;

a 1 st wiring connected to a gate electrode of the memory transistor; and

a control device for performing a read operation for reading data from the memory transistor and a write operation for writing data into the memory transistor; and is

The control device is used for controlling the operation of the motor,

increasing the voltage of the 1 st wiring to the 1 st voltage at the 1 st timing from the 1 st timing to the 2 nd timing of the read operation or the write operation

Adjusting a length from the 1 st timing to the 2 nd timing in accordance with at least one of a voltage, a current, and a charge amount of the 1 st wiring from the 1 st timing to the 2 nd timing.

13. The method of controlling a semiconductor memory device according to claim 12, wherein the read operation is a write verification operation performed at the time of the write operation or an erase verification operation performed at the time of an erase operation.

14. The method of controlling a semiconductor memory device according to claim 12, wherein the control means, in the read operation:

increasing the voltage of the 1 st wiring to the 1 st voltage from the 1 st timing to the 2 nd timing;

reducing the voltage of the 1 st wiring from the 2 nd timing to the 3 rd timing to a 2 nd voltage; and is

Setting a length from the 1 st sequence to the 2 nd sequence to a 1 st length when the voltage of the 1 st wiring in the 1 st sequence is a 1 st initial voltage, and

setting a length from the 1 st sequence to the 2 nd sequence to a 2 nd length when the voltage of the 1 st wiring in the 1 st sequence is a 2 nd initial voltage smaller than the 1 st initial voltage,

the control means sets the 2 nd length to be larger than the 1 st length.

15. The method of controlling a semiconductor memory device according to claim 12, wherein the control means, in the read operation:

increasing the voltage of the 1 st wiring to the 1 st voltage from the 1 st timing to the 2 nd timing;

reducing the voltage of the 1 st wiring from the 2 nd timing to the 3 rd timing to a 2 nd voltage,

the length from the 1 st sequence to the 2 nd sequence is set as the 1 st length when the maximum value of the speed of the voltage increase of the 1 st wiring from the 1 st sequence to the 2 nd sequence is the 1 st speed, and

when the length from the 1 st sequence to the 2 nd sequence when the maximum value of the speed of voltage increase of the 1 st wiring from the 1 st sequence to the 2 nd sequence is the 2 nd speed smaller than the 1 st speed is set as the 2 nd length,

the control means sets the 2 nd length to be larger than the 1 st length.

16. The method of controlling a semiconductor storage device according to claim 12, wherein the control device, in the write operation:

increasing the voltage of the 1 st wiring to the 1 st voltage from the 1 st timing to the 2 nd timing;

increasing the voltage of the 1 st wiring to the 2 nd voltage from the 2 nd timing to the 3 rd timing; and is

Setting a length from the 1 st sequence to the 2 nd sequence to a 1 st length when the voltage of the 1 st wiring in the 1 st sequence is a 1 st initial voltage, and

setting a length from the 1 st sequence to the 2 nd sequence to a 2 nd length when the voltage of the 1 st wiring in the 1 st sequence is a 2 nd initial voltage smaller than the 1 st initial voltage,

the control means sets the 2 nd length to be larger than the 1 st length.

17. The method for controlling a semiconductor memory device according to claim 12, wherein the control device increases the voltage of the 1 st wiring to the 1 st voltage in the 1 st timing to the 2 nd timing of the write operation, and

the length from the 1 st sequence to the 2 nd sequence is set as the 1 st length when the maximum value of the speed of the voltage increase of the 1 st wiring from the 1 st sequence to the 2 nd sequence is the 1 st speed, and

when the length from the 1 st sequence to the 2 nd sequence when the maximum value of the speed of voltage increase of the 1 st wiring from the 1 st sequence to the 2 nd sequence is the 2 nd speed smaller than the 1 st speed is set as the 2 nd length,

the control means sets the 2 nd length to be larger than the 1 st length.

18. The method for controlling a semiconductor memory device according to claim 17, wherein the control device increases the voltage of the 1 st wiring to the 2 nd voltage in the 2 nd to 3 rd timings of the write operation, and

setting a length from the 2 nd timing to the 3 rd timing as a 3 rd length when a maximum value of a speed at which the voltage of the 1 st wiring increases from the 2 nd timing to the 3 rd timing is a 3 rd speed,

when the maximum value of the speed of voltage increase of the 1 st wiring from the 2 nd timing to the 3 rd timing is the 4 th speed which is smaller than the 3 rd speed, the length from the 2 nd timing to the 3 rd timing is set as the 4 th length,

the control means sets the 3 rd length to be larger than the 4 th length.

Technical Field

Embodiments described below relate to a semiconductor memory device and a control method thereof.

Background

Semiconductor memory devices including memory transistors and methods of controlling the same are known.

Disclosure of Invention

A semiconductor memory device according to one embodiment includes: a memory transistor; a 1 st wiring connected to a gate electrode of the memory transistor; and a control device for performing a read operation for reading data from the memory transistor and a write operation for writing data into the memory transistor. The control device increases the voltage of the 1 st wiring to the 1 st voltage from the 1 st timing to the 2 nd timing of the read operation or the write operation, and adjusts the length from the 1 st timing to the 2 nd timing in accordance with at least one of the voltage, the current, and the charge amount of the 1 st wiring from the 1 st timing to the 2 nd timing.

A method for controlling a semiconductor memory device according to one embodiment includes a memory transistor, a 1 st wiring connected to a gate electrode of the memory transistor, and a control device for performing a read operation for reading data from the memory transistor and a write operation for writing data to the memory transistor. In the control method, the control device increases the voltage of the 1 st wiring to the 1 st voltage from the 1 st timing to the 2 nd timing of the read operation or the write operation, and adjusts the length from the 1 st timing to the 2 nd timing in accordance with at least one of the voltage, the current, and the charge amount of the 1 st wiring from the 1 st timing to the 2 nd timing.

Drawings

Fig. 1 is a schematic block diagram showing the structure of a semiconductor memory device MD according to embodiment 1.

Fig. 2 is a schematic circuit diagram showing a configuration of a part of the semiconductor memory device MD.

Fig. 3 is a schematic circuit diagram showing a configuration of a part of the semiconductor memory device MD.

Fig. 4 is a schematic plan view showing the structure of the semiconductor memory device MD.

Fig. 5 is an enlarged view of a portion of fig. 4.

Fig. 6 is a cross-sectional view of the construction shown in fig. 5, taken along the line a-a' and viewed in the direction of the arrows.

Fig. 7 is an enlarged view of a portion of fig. 6.

Fig. 8 is a schematic flowchart for explaining the reading operation in embodiment 1.

Fig. 9 is a schematic timing chart for explaining the read operation.

Fig. 10 is a schematic cross-sectional view for explaining the readout operation.

Fig. 11 is a schematic cross-sectional view for explaining the readout operation.

Fig. 12 is a schematic cross-sectional view for explaining the readout operation.

Fig. 13 is a schematic flowchart for explaining the reading operation of the comparative example.

Fig. 14 is a schematic timing chart for explaining the read operation.

Fig. 15 is a schematic cross-sectional view for explaining the readout operation.

Fig. 16 is a schematic timing chart for explaining the above-described reading operation.

Fig. 17 is a schematic timing chart for explaining the read operation.

Fig. 18A is a schematic timing chart for explaining the read operation in embodiment 1.

Fig. 18B is a schematic timing chart for explaining the read operation in embodiment 1.

Fig. 19 is a schematic flowchart for explaining the reading operation according to embodiment 2.

Fig. 20 is a schematic circuit diagram showing a configuration of a part of the semiconductor memory device according to embodiment 3.

Fig. 21 is a schematic flowchart for explaining the reading operation according to embodiment 3.

Fig. 22 is a schematic graph for explaining the above-described reading operation.

Fig. 23 is a schematic graph for explaining the reading operation according to embodiment 4.

Fig. 24 is a schematic graph for explaining a write operation according to another embodiment.

Fig. 25 is a schematic graph for explaining a writing operation according to another embodiment.

Fig. 26 is a schematic graph for explaining a write operation according to another embodiment.

Fig. 27 is a schematic graph for explaining a write operation according to another embodiment.

Fig. 28 is a schematic graph for explaining a writing operation according to another embodiment.

Detailed Description

Next, the semiconductor memory device according to the embodiment will be described in detail with reference to the drawings. The following embodiments are merely examples, and are not intended to limit the present invention.

In the present specification, the term "semiconductor memory device" may mean a memory die, and may mean a memory system including a control chip, such as a memory chip, a memory card, or an SSD (SOLID state drive) STATE DRIVE. Further, the term "configuration" may also mean a configuration including a host computer, such as a smartphone, a tablet terminal, or a personal computer.

In the present specification, when the 1 st configuration is referred to as the "electrically connected" 2 nd configuration, the 1 st configuration may be directly connected to the 2 nd configuration, or the 1 st configuration may be connected to the 2 nd configuration via a wiring, a semiconductor element, a transistor, or the like. For example, when 3 transistors are connected in series, the transistor No. 1 is electrically connected to the transistor No. 3 even when the transistor No. 2 is in an OFF state.

In the present specification, when it is referred to that the 1 st configuration is "connected" between the 2 nd configuration and the 3 rd configuration, the 1 st configuration, the 2 nd configuration, and the 3 rd configuration are connected in series, and the 1 st configuration is provided in the current path of the 2 nd configuration and the 3 rd configuration.

In addition, in this specification, when a circuit or the like turns "ON" 2 wirings or the like, for example, the circuit or the like may include a transistor or the like which is provided in a current path between the 2 wirings and which is in an ON (ON) state.

[ embodiment 1 ]

[ constitution ]

Fig. 1 is a schematic block diagram showing the structure of a semiconductor memory device MD according to embodiment 1. Fig. 2 and 3 are schematic circuit diagrams showing a configuration of a part of the semiconductor memory device MD.

As shown in fig. 1, the semiconductor memory device MD includes a memory cell array MCA for storing data and a peripheral circuit PC connected to the memory cell array MCA.

[ memory cell array MCA ]

The memory cell array MCA includes a plurality of memory blocks MB. As shown in fig. 2, each of the plurality of memory blocks MB includes a plurality of sub blocks SB. Each of the plurality of subblocks SB includes a plurality of memory strings MS. One end of each of the plurality of memory strings MS is connected to the peripheral circuit PC via a bit line BL. The other ends of the memory strings MS are connected to the peripheral circuit PC via common source lines SL.

The memory string MS includes a drain select transistor STD, a plurality of memory cells MC, and a source select transistor STS connected in series between a bit line BL and a source line SL. Hereinafter, the drain selection transistor STD and the source selection transistor STS may be simply referred to as selection transistors (STD, STS).

The memory cell MC of the present embodiment is a field effect transistor (memory transistor) including a semiconductor layer functioning as a channel region, a gate insulating film including a charge storage film, and a gate electrode. The threshold voltage of the memory cell MC varies according to the amount of charge in the charge storage film. The memory cell MC stores 1-bit or multi-bit data. Further, word lines WL are connected to the gate electrodes of the plurality of memory cells MC corresponding to one memory string MS. These word lines WL are connected in common to all memory strings MS in one memory block MB, respectively.

The selection transistors (STD, STS) are field effect transistors having a semiconductor layer functioning as a channel region, a gate insulating film, and a gate electrode. The gate electrodes of the select transistors (STD, STS) are connected to select gate lines (SGD, SGS), respectively. The drain select lines SGD are disposed corresponding to the subblocks SB, and commonly connect all the memory strings MS in one subblock SB. The source selection lines SGS are commonly connected to a plurality of memory strings MS in one memory block MB.

[ peripheral Circuit PC ]

As shown in fig. 1, the peripheral circuit PC as a control device includes a sense amplifier module SAM, a row decoder RD, a voltage generation circuit VG, and a sequencer SQC. The peripheral circuit PC includes an address register ADR, an instruction register CMR, and a status register STR. The peripheral circuit PC includes an input/output control circuit I/O and a logic circuit CTR.

The sense amplifier module SAM includes a plurality of sense amplifier units corresponding to the plurality of bit lines BL. Each of the sense amplifier units includes a sense amplifier connected to the bit line BL, a plurality of data latches, a logic circuit, and a data transmission line connected to these components. The sense amplifier includes a sense transistor for discharging or holding the charge of the data line according to the voltage or current of the bit line BL. The data latch is used for data transmission, data operation, and the like. The sense amplifier module includes a decoding circuit and a switching circuit, which are not shown. The decoding circuit decodes the column address CA held in the address register ADR (fig. 2). The switching circuit turns on the data latch XDL corresponding to the column address CA and the bus DB in accordance with an output signal of the decoding circuit.

The row decoder RD includes, for example, a decoding circuit that decodes a row address RA stored in the address register ADR. As shown in fig. 3, for example, the row decoder RD includes a switch circuit SW1 for selectively connecting the plurality of word lines WL to the plurality of wirings CGi, a switch circuit SW2 for selectively connecting the plurality of wirings CGi to the plurality of wirings CGp, and a driver circuit DRV for connecting the plurality of wirings CGp to the voltage generation circuit VG.

The switch circuit SW1 includes a plurality of voltage transfer transistors 10. The plurality of voltage transfer transistors 10 are provided corresponding to a plurality of word lines WL and select gate lines (SGD, SGS) included in each memory block MB, and are connected to the corresponding word lines WL or select gate lines (SGD, SGS), respectively. In the illustrated example, a common wiring 11 is connected to the gate electrodes of all the voltage transfer transistors 10 corresponding to the memory blocks MBA and MBB. Similarly, a common wiring 12 is connected to the gate electrodes of all the voltage transfer transistors 10 corresponding to the memory blocks MBC and MBD.

The wirings CGi are provided corresponding to the plurality of word lines WL and the select gate lines (SGD, SGS) simultaneously selected by the switch circuit SW 1.

The switch circuit SW2 includes a plurality of voltage transfer transistors 20. These voltage transfer transistors 20 are provided corresponding to the wirings CGi, and are connected to the corresponding wirings CGi, respectively. In the illustrated example, a common wiring 21 is connected to the gate electrodes of all the voltage transfer transistors 20 corresponding to the memory blocks MBA and MBC. Similarly, a common wiring 22 is connected to the gate electrodes of all the voltage transfer transistors 20 corresponding to the memory blocks MBB and MBD.

The wirings CGp are provided corresponding to a plurality of word lines WL and select gate lines (SGD, SGS) included in one memory block MB.

The driver circuit DRV is provided with a plurality of voltage transfer transistors 30. A plurality of these voltage transfer transistors 30 are provided corresponding to a plurality of word lines WL and select gate lines (SGD, SGS). One ends of the plurality of voltage transfer transistors 30 are connected to the wirings CGp, respectively. The other ends are connected to voltage supply lines 41 of the charge pump circuit 40 included in the voltage generation circuit VG, respectively. The gate electrodes of the voltage transfer transistors 30 are configured to be independently controllable.

The voltage generation circuit VG includes, for example, a voltage generation circuit VG connected to a power supply terminal (V)_CC) And a ground terminal (V)_SS) A charge pump circuit 40 and a step-down circuit not shown. The voltage generation circuit VG generates a plurality of operation voltages to be supplied to the bit line BL, the source line SL, the word line WL, and the select gate line (SGD, SGS) in the read operation, the write operation, and the erase operation of the memory cell array MCA in accordance with an internal control signal from the sequencer SQC, and outputs the plurality of operation voltages simultaneously from the plurality of voltage supply lines 41.

In addition, a voltage detection circuit 42 is connected to at least one of the voltage supply lines 41 of the plurality of charge pump circuits 40. The voltage detection circuit 42 includes a voltage divider circuit 43 connected to the voltage supply line 41, and a comparator circuit 44 connected to an output terminal of the voltage divider circuit 43.

The voltage divider circuit 43 includes a voltage supply line 41 and a ground terminal (V) connected in series_SS) A variable resistance element 43a and a resistance element 43b in between. The resistance value of the variable resistance element 43a can be adjusted by parameters or the like. The variable resistive element 43a and the resistive element 43b are connected to the output terminal 43 c. In the following description, the voltage divider circuit 43 multiplies the voltage at the input terminal by 1/k and outputs the multiplied voltage to the output terminal 43 c.

An input terminal of the comparator circuit 44 is connected to the output terminal of the voltage divider circuit 43. The other input terminal of the comparison circuit 44 is supplied with a reference voltage V_REF. The output terminal is connected to the sequencer SQC. In the illustrated example, the reference voltage V is set to_REFSet to be lower than 1/kV_READ。

The sequencer SQC (fig. 1) sequentially decodes the command data CMD saved in the command register CMR and outputs internal control signals to the row decoder RD, the sense amplifier module SAM, and the voltage generation circuit VG. In addition, the sequencer SQR outputs state data indicating its own state to the state register STR as appropriate. For example, when the write operation or the erase operation is executed, information indicating whether the write operation or the erase operation has ended normally is output as the status data.

The input/output control circuit I/O includes data input/output terminals I/O0 to I/O7, a shift register connected to the data input/output terminals I/O0 to I/O7, and a FIFO buffer connected to the shift register. The input/output control circuit I/O outputs data input from the data input/output terminals I/O0 to I/O7 to the data latch XDL, the address register ADR, or the command register CMR in the sense amplifier module SAM, in accordance with an internal control signal from the logic circuit CTR. In addition, data input from the data latch XDL or the status register STR is output to the data input/output terminals I/O0 to I/O7.

The logic circuit CTR receives an external control signal from the control chip CD via the external control terminals/Cen, CLE, ALE,/WE,/RE, and outputs an internal control signal to the input/output control circuit I/O in response to the external control signal.

Next, a configuration example of the semiconductor memory device of the present embodiment will be described with reference to fig. 4 to 7. Fig. 4 is a schematic plan view of the semiconductor memory device of this embodiment. Fig. 5 is an enlarged view of a portion of fig. 4. FIG. 6 is a cross-sectional view of the construction shown in FIG. 5, taken along the line A-A' and viewed in the direction of the arrows. Fig. 7 is an enlarged view of a portion of fig. 6. Fig. 4 to 7 show schematic configurations, and the specific configuration can be modified as appropriate. In fig. 4 to 7, a part of the structure is omitted.

As shown in fig. 4, the semiconductor memory device of the present embodiment includes a semiconductor substrate 100. In the illustrated example, 2 memory cell arrays MCA arranged along the X direction are provided on the semiconductor substrate 100. In addition, switch circuits SW1 (fig. 3) in the row decoder RD are provided in regions extending in the Y direction along both ends of the memory cell array MCA in the X direction. Although not shown, the wirings CGi are provided in this region, and these wirings CGi extend in the Y direction. In addition, a sense amplifier module SAM is provided in a region extending in the X direction along the end portion of the memory cell array MCA in the Y direction. The switch circuits SW2 (fig. 3) in the row decoder RD are provided in regions near both ends in the X direction of the region in which the sense amplifier module SAM is provided. In the outer region of these regions, a driver circuit DRV, a voltage generation circuit VG, a voltage detection circuit 42, a sequencer SQC, an input/output control circuit I/O, and a logic circuit CTR are provided.

The memory cell array MCA includes a plurality of memory blocks MB arranged in the Y direction. As shown in fig. 5, the memory block MB includes 2 block structures BS arranged along the Y direction. Further, an inter-block insulating layer ST extending in the X direction is provided between 2 block structures BS adjacent in the Y direction.

The block structure BS includes 2 sub-blocks SB arranged in the Y direction and an inter-sub-block insulating layer SHE provided between the 2 sub-blocks SB.

As illustrated in fig. 6, the sub-block SB includes a plurality of conductive layers 110 and a plurality of semiconductor layers 120 provided above the semiconductor substrate 100, and a plurality of gate insulating films 130 provided between the plurality of conductive layers 110 and the plurality of semiconductor layers 120, respectively.

The semiconductor substrate 100 is, for example, a semiconductor substrate such as single crystal silicon (Si) containing a P-type impurity. An N-type well containing an N-type impurity such as phosphorus (P) is provided in a part of the surface of the semiconductor substrate 100. In addition, a P-type well containing a P-type impurity such as boron (B) is provided in a part of the surface of the N-type well.

The conductive layer 110 is a substantially plate-shaped conductive layer extending in the X direction, and a plurality of conductive layers are arranged in the Z direction. The conductive layer 110 may include a multilayer film of titanium nitride (TiN) and tungsten (W), or may include polysilicon containing an impurity such as phosphorus or boron. In addition, silicon oxide (SiO) is provided between the conductive layers 110₂) Etc. insulating layer 111.

One or more conductive layers 110 positioned at the lowermost layer among the plurality of conductive layers 110 function as a source selection line SGS (fig. 2) and a gate electrode of a plurality of source selection transistors STS connected to the source selection line SGS. The conductive layers 110 located above the word lines WL (fig. 2) function as gate electrodes of the word lines WL and the memory cells MC (fig. 2) connected to the word lines WL. The one or more conductive layers 110 located above the drain selection line SGD function as gate electrodes of the drain selection transistors STD (fig. 2) connected to the drain selection line SGD.

As illustrated in fig. 5, a plurality of semiconductor layers 120 are arranged in the X direction and the Y direction. The semiconductor layer 120 is a semiconductor film such as undoped polysilicon (Si), for example. The semiconductor layer 120 has a substantially cylindrical shape, for example, as illustrated in fig. 6, and an insulating film 121 such as silicon oxide is provided in the center portion. The outer peripheral surfaces of the semiconductor layers 120 are surrounded by the conductive layers 110. The lower end of the semiconductor layer 120 is connected to the P-well of the semiconductor substrate 100 via a semiconductor layer 122 made of undoped silicon or the like. The semiconductor layer 122 faces the conductive layer 110 through an insulating layer 123 such as silicon oxide. The upper end of the semiconductor layer 120 is connected to the bit line BL via a semiconductor layer 124 containing an N-type impurity such as phosphorus (P), and contacts Ch and Cb. The semiconductor layer 120 functions as a channel region of each of the plurality of memory cells MC and the drain select transistor STD included in one memory string MS (fig. 3). The semiconductor layer 122 functions as a channel region of a part of the source selection transistor STS.

The gate insulating film 130 includes, for example, as shown in fig. 7, a tunnel insulating film 131, a charge storage film 132, and a barrier insulating film 133, which are stacked between the semiconductor layer 120 and the conductive layer 110. The tunnel insulating film 131 and the barrier insulating film 133 are insulating films such as silicon oxide. The charge storage film 132 is a film capable of storing charges, such as silicon nitride (SiN). The tunnel insulating film 131, the charge storage film 132, and the barrier insulating film 133 have a substantially cylindrical shape, and extend in the Z direction along the outer peripheral surface of the semiconductor layer 120.

In fig. 7, an example is shown in which the gate insulating film 130 includes a charge storage film 132 such as silicon nitride, but the gate insulating film 130 may include a floating gate such as polysilicon containing N-type or P-type impurities.

[ reading action ]

Next, a reading operation of the semiconductor memory device according to the present embodiment will be described with reference to fig. 8 to 12. Fig. 8 is a schematic flowchart for explaining a read operation of the semiconductor memory device according to the present embodiment. Fig. 9 is a schematic timing chart for explaining the read operation. Fig. 10 to 12 are schematic cross-sectional views for explaining the readout operation.

Fig. 9 shows the voltage of the output terminal 43c of the voltage divider circuit 43, the voltage of the word line WL, the voltage of the drain select line SGD, the voltage of the source select line SGS, and the voltage of the bit line BL, which are described with reference to fig. 3.

In the examples of fig. 10 to 12, the memory block MB includes 4 sub-blocks SB. Hereinafter, the memory strings MS (fig. 1) included in the 4 sub blocks SB may be referred to as a string StrA, a string StrB, a string StrC, and a string StrD, respectively.

In the following example, an example in which the read operation is performed on the selected page P corresponding to the string StrA will be described. In some cases, the word line WL connected to the selected page P is referred to as a selected word line sWL, and the other word lines WL are referred to as unselected word lines uWL. In addition, the drain selection line SGD connected to the string StrA may be referred to as a selected drain selection line SGD, and the drain selection lines SGD connected to the strings StrB, StrC, and StrD may be referred to as a non-selected drain selection line uggd. In addition, the source selection line SGS connected to the strings StrA and StrB may be referred to as a selected source selection line SGS, and the source selection line SGS connected to the strings strac and StrD may be referred to as a non-selected source selection line uggs.

In step S101 (fig. 8), voltage supply to the word line WL and the like is started. For example, at timing T of FIG. 9₁₀₁Supplying a voltage V to the word line WL_READA voltage V is supplied to the selection gate lines (SGD, SGS)_SGSupplying a voltage V to the bit line BL_CELSRC. Voltage V_READThe size is such that the memory cell MC is turned on regardless of the data recorded in the memory cell MC. Voltage V_SGThe selection transistors (STD, STS) are of such a size that they are in an ON state. Voltage V_CELSRCCan be connected with the grounding voltage V_SSTo the same extent.

At this time, the voltage V is supplied_READThe charges of the voltage supply line 41 of the charge pump circuit 40 are supplied to the word line WL, and the voltage of the voltage supply line 41 temporarily decreases. Accordingly, as shown in fig. 9, for example, the voltage of the output terminal 43c of the voltage detection circuit 42 connected to the voltage supply line 41 also temporarily decreases.

In step S102, it is determined whether or not the output voltage of the comparison circuit 44 (fig. 3) is "H". If not "H", the process proceeds to step S102. If "H" is the case, the process proceeds to step S103.

At this time, the positive charge is supplied to the voltage supply line 41 by the charge pump circuit 40, and the voltages of the word line WL and the voltage supply line 41 gradually approach the voltage V_READ. As a result, for example, as illustrated in fig. 10, all memory strings MS in the memory block MB including the selected memory cell MC are turned on, and all the memory cells MC are electrically connected to the bit line BL and the source line SL. Further, the voltage at the output terminal 43c of the voltage divider circuit 43 is also close to 1/kV_READBecomes larger than the reference voltage V at a certain timing_REFAnd the output voltage of the comparator circuit 44 (fig. 3) becomes "H". At this time, the voltages of the selected word line sWL and the unselected word line uWLBecomes V_READ。

In step S103 (fig. 8), supply of a voltage to the selected word line sWL or the like is started. For example, at timing T of FIG. 9₁₀₂The ground voltage V is supplied to the selected word line sWL_SSA voltage V is supplied to the non-selected selection gate lines (uSGD, uSGS)_DD. Voltage V_DDFor example, the gate lines (SGD, SGS) are set to be in an off state. Subsequently, the unselected word line uWL is maintained at the voltage V, as shown in FIG. 9 for example_READTo the extent that the voltage of the select word line sWL is towards the ground voltage V_SSThe decrease is started. The voltage of the non-selected select gate lines (uSGD, uSGS) is directed to a voltage V_DDStarting to decrease, the voltage of the selected selection gate line (sSGD, sSGS) is maintained at a voltage V_SGDegree of the disease.

In step S104, it is determined whether or not a specific time has elapsed since execution of step S103, with reference to a timer or the like, not shown. If the specific time has not elapsed, the process proceeds to step S104. If the specific time has elapsed, the process proceeds to step S105.

Thus, for example, as illustrated in fig. 11, the memory cells MC included in the strings StrB, StrC, StrD are cut off from the bit lines BL. Further, the memory cells MC included in the strings StrC and StrD are disconnected from the source lines SL. In addition, all the memory cells MC connected to the selected word line WL are turned off.

In step S105 (fig. 8), supply of voltage to the selected word line WL and the like is started. For example, at timing T of FIG. 9₁₀₃A read voltage V is supplied to the selected word line WL_CGRSupplying a read bit line voltage V to the bit line BL_BL. Read out voltage V_CGRThe size of the memory cell MC is such that the memory cell MC is turned on or off according to the data recorded in the memory cell MC.

In step S106, it is determined whether or not a specific time has elapsed since execution of step S105, with reference to a timer or the like, not shown. If the specific time has not elapsed, the process proceeds to step S106. If the specific time has elapsed, the process proceeds to step S107.

As a result, for example, as illustrated in fig. 12, a current flows through the bit line BL according to the data recorded in the selected memory cell MC.

In step S107 (fig. 8), the current or voltage of the bit line BL is detected by the sense amplifier.

In step S108, for example, at timing T of FIG. 9₁₀₄The voltages of the word line WL, the select gate lines (SGD, SGS), and the bit line BL are lowered. For example, the voltage of the word line WL is lowered to V_DD-V_thLeft and right, the voltages of the select gate lines (SGD, SGS) and the bit lines BL are lowered to the ground voltage V_SSLeft and right. V_thFor example, the threshold voltage of the voltage transfer transistor having the maximum threshold voltage among the plurality of voltage transfer transistors connected between the voltage supply line 41 (fig. 3) and the word line WL. Furthermore, because at time T₁₀₄Since the word line WL and the select gate line (SGD, SGS) drop at substantially the same time, the semiconductor layer 120 is electrically disconnected from the bit line BL and the source line, and electrons remain in the semiconductor layer 120. The voltage of the semiconductor layer 120 becomes a negative voltage by capacitive coupling with the word line WL.

In step S109 (FIG. 8), for example, at timing T of FIG. 9₁₀₅The switch circuits SW1, SW2 (fig. 3), and the like are turned off. Furthermore, at the time sequence T₁₀₅Thereafter, the charges remaining in the semiconductor layer 120 are gradually transferred to the bit line BL and the source line SL via the selection transistors (STD, STS), and the voltage of the semiconductor layer 120 is gradually increased. Accordingly, the voltage of the word line WL is increased to the voltage V by the capacitive coupling with the semiconductor layer 120₁Left and right. Hereinafter, this phenomenon may be referred to as "creep.

[ comparative example ]

Next, a semiconductor memory device and a read operation of a comparative example will be described with reference to fig. 13 to 17. Fig. 13 is a schematic flowchart for explaining the reading operation of the comparative example. Fig. 14, 16, and 17 are schematic timing charts for explaining the above-described read operation. Fig. 15 is a schematic cross-sectional view for explaining the readout operation.

The semiconductor memory device of the comparative example does not include the voltage detection circuit 42 as illustrated in fig. 3. As shown in fig. 13, in step S002 of the reading operation of the comparative example, it is determined whether or not a specific time has elapsed since execution of step S101 by referring to a timer or the like, which is not shown.

Here, when the waiting time in step S002 of the read operation is set by a timer or the like, for example, as shown in fig. 14, the sequence T is started from₁₀₁To time sequence T₁₀₂Waiting time t of₁Becomes a fixed time. As a result, as shown in the figure, the voltage on the word line WL reaches the read pass voltage V_READBefore start timing T₁₀₂The case of (3). This case will be explained.

At a time sequence T₁₀₂，

The voltage of the select source line SGS (source select line SGS connected to the source select transistors STS of the strings StrA and StrB) is selected to go toward V_SGTherefore, the strings StrA and StrB are conducted to the source line SL.

The voltage of the select drain select line SGD (drain select line SGD connected to the drain select transistor STD of the string StrA) tends toward V_SGThus, the selected string StrA is electrically connected to the bit line BL.

The voltage of the non-selected drain select line uSGD connected to the drain select transistor STD of the string StrB tends toward V_DDAnd thus the string StrB is electrically disconnected from the bit line BL.

The voltage of the unselected source select line uSGS (source select line SGS connected to the source select transistors STS of strings StrC and StrD) tends to V_DDTherefore, the strings StrC and StrD are electrically disconnected from the source line SL.

The voltage of the non-selected drain select line uSGD connected to the drain select transistors STD of the strings StrC and StrD tends towards V_DDThus, strings StrC and StrD are electrically disconnected from bit line BL.

Here, in the string StrB, the voltage of the memory cell MC on the drain side of the selected word line sWL in the unselected word line uWL becomes V_READPreviously electrically disconnected from the bit line BL.

Because the select word line sWL goes to V_SSTherefore, the memory cell MC connected to the selected word line sWL is turned off. At this time, the memory cell MC closer to the drain side than the memory cell MC connected to the selected word line WL in the string StrBThe channel of the element MC becomes floating. Therefore, if it is desired to raise the unselected word line sWL on the drain side of the selected word line sWL to V_READThen the channel is boosted and the potential is raised.

On the other hand, the potential of the channel of the memory cell MC on the source side of the memory cell MC connected to the selected word line sWL becomes the potential of the source line SL (ground voltage V)_SS) Are equal. Therefore, even if the unselected word line uWL on the source side of the selected word line sWL rises to V_READAnd boosting of the channel does not occur.

As described above, in the string StrB, a potential difference is generated across the memory cell MC connected to the selected word line sWL. Thus, as shown in fig. 15, hot electrons are generated. In addition, the hot electrons are injected into the charge storage film 132 (fig. 7) of the unselected memory cell MC located on the drain side of the memory cell MC connected to the selected word line WLs, and the threshold voltage of the unselected memory cell MC may increase.

In the strings StrC and StrD, the above-described problem is not easily generated. This is because the strings are electrically disconnected from the source lines SL and the bit lines BL, and therefore, even if the channel is boosted, a potential difference is not generated across the memory cells MC connected to the selected word line sWL as in the case of the string StrB.

This phenomenon can be caused by a slave sequence T as shown in fig. 16, for example₁₀₁To time sequence T₁₀₂Waiting time to₁Sufficiently long to be avoided. This is because the voltage of the word line WL has risen to V before the string is disconnected from the bit line BL and the source line SL to be in a floating state_READSo no channel boosting occurs.

However, as shown in fig. 17, for example, there is a waiting time t even when the word line WL is creeping up₁If the condition is short, the waiting time t is set for all read operations₁If the length is set to be long, the operation is not preferable in view of speeding up the operation.

[ Effect ]

In the read operation of the present embodiment, as described with reference to fig. 8 and the like, the step S101 waits until the step S1 starts to supply the voltageIn step S02, the output voltage of the comparator circuit 44 (fig. 3) is "H", and then the supply of the next voltage is started in step S103. According to this method, the timing T can be adjusted₁₀₁To time sequence T₁₀₂Waiting time t of₁Shortening to the necessary minimum length. For example, it is possible to wait for time t as illustrated in fig. 9₁The waiting time t can be shortened under the condition of shorter time₁Can wait for a time t as illustrated in FIG. 18A₁Making the waiting time t relatively long₁Is longer. Thus, a semiconductor memory device which operates at high speed without losing reliability can be provided.

[ modified example of embodiment 1 ]

Preferred waiting time t₁The length of (d) can be varied depending on various conditions, and according to embodiment 1, as illustrated in fig. 18A and 18B, the waiting time t can be adjusted in accordance with various conditions₁And (6) adjusting.

For example, as described above, when the read operation of the present embodiment is performed, a creep occurs, and the voltage of the word line WL is higher than the ground voltage V_SSThe state of (c). When the initial voltage of the word line WL is large as described above, for example, as illustrated in fig. 9, there is a waiting time t₁A relatively shortened condition. On the other hand, the voltage of the word line WL may be the ground voltage V when the semiconductor memory device MD is started, for example_SSLeft and right. When the initial voltage of the word line WL is small as described above, for example, as illustrated in fig. 18A, there is a waiting time t₁Relatively long.

In addition, for example, a time constant (RC time constant) of the word line WL or the like may vary due to a manufacturing error or the like, and a difference in boosting rate may occur. For example, when the outer diameter of the semiconductor layer 120 is large, the inner diameter of a through hole provided in the conductive layer 110 may be increased, and the resistance value of the conductive layer 110 may be increased. In this case, for example, as illustrated in fig. 18B, there is a case where the average value, the maximum value, and the like of the boosting rate (the speed at which the word line WL is charged) are reduced and the waiting time t is reduced₁Relatively long. The other partyWhen the outer diameter of the semiconductor layer 120 and the inner diameter of the through hole provided in the conductive layer 110 are small, the average value, the maximum value, and the like of the boosting rate (the rate at which the word line WL is charged) increase and the waiting time t may be increased as illustrated in fig. 9, for example₁A relatively shortened condition.

In addition, for example, when 4 or more memory cell arrays MCA are provided on the semiconductor substrate 100, distances to the driver circuit DRV may be different depending on the memory cell arrays MCA. In this case, there is also a case where wiring resistance and the like in the peripheral circuit PC differ depending on the memory cell array MCA, resulting in a difference in the boosting rate. For example, in the memory cell array MCA remote from the driver circuit DRV, for example, as illustrated in fig. 18B, the average value, the maximum value, or the like of the boosting rate (the speed at which the word line WL is charged) is reduced while the waiting time t is decreased₁Relatively long. On the other hand, in the memory cell array MCA near the driver circuit DRV, for example, as illustrated in fig. 9, the average value, the maximum value, and the like of the boosting rate (the speed at which the word line WL is charged) increase and the waiting time t₁A relatively shortened condition.

[ 2 nd embodiment ]

[ constitution ]

Next, a semiconductor memory device according to embodiment 2 will be described with reference to fig. 19. Fig. 19 is a schematic flowchart for explaining the reading operation of the present embodiment.

The semiconductor memory device of the present embodiment is configured in the same manner as the semiconductor memory device of embodiment 1.

The reading operation of the present embodiment is almost the same as that of embodiment 1. In step S102 of the present embodiment, if the output voltage of the comparator circuit 44 (fig. 3) is not "H", the process proceeds to step S201.

In step S201, it is determined whether or not a specific time has elapsed since execution of step S101, with reference to a timer or the like, not shown. If the specific time has not elapsed, the process proceeds to step S102. If the specific time has elapsed, the process proceeds to step S103.

Here, for example, it is considered that the voltage of the output terminal 43c of the voltage divider circuit 43 does not become larger than the reference voltage V when a leakage current is generated in a current path from the charge pump circuit 40 to the source line SL through the word line WL_REF. According to the method of the present embodiment, in this case, the reading operation can be forcibly terminated. In this case, for example, a signal indicating an error can be output.

[ embodiment 3 ]

[ constitution ]

Next, the semiconductor memory device according to embodiment 3 will be described with reference to fig. 20. Fig. 20 is a schematic circuit diagram showing a configuration of a part of the semiconductor memory device of the present embodiment.

The semiconductor memory device of the present embodiment is basically configured in the same manner as the semiconductor memory device MD of embodiment 1, but does not include the voltage detection circuit 42. As shown in fig. 20, the semiconductor memory device of the present embodiment includes a current detection circuit 50.

The current detection circuit 50 of the present embodiment includes: a current mirror circuit 51 connected to at least one of the voltage supply lines 41 of the plurality of charge pump circuits 40; a sampling circuit 52 connected to the current mirror circuit 51; and a comparator 53 connected to the sampling circuit 52.

The current mirror circuit 51 includes: a PMOS (P-channel metal oxide semiconductor) transistor 51a connected between the voltage supply line 41 and the driver circuit DRV; and a PMOS transistor 51 b; the source terminal is commonly connected to the source terminal of the PMOS transistor 51a, and the gate terminal is commonly connected to the gate terminal and the drain terminal of the PMOS transistor 51 a. The current flowing through the PMOS transistor 51b may be, for example, about one tenth of the current flowing through the PMOS transistor 51 a.

The sampling circuit 52 includes: a switch circuit 52a selectively connecting the node N3 to one of the nodes N4 and N5; and a capacitor 52b connected to the node N3 and the ground terminal (V)_SS) In the meantime. Node N4 of switch circuit 52a is connectedAt the drain terminal of the PMOS transistor 51 b. Node N5 of switch circuit 52a is connected to ground terminal (V)_SS)。

An input terminal of the comparison circuit 53 is connected to the node N3 of the switch circuit 52 a. A reference voltage V is supplied to the other input terminal of the comparison circuit 53_REF. The output terminal is connected to the sequencer SQC.

[ reading action ]

Next, a reading operation of the semiconductor memory device according to the present embodiment will be described with reference to fig. 21 and 22. Fig. 21 is a schematic flowchart for explaining a read operation of the semiconductor memory device according to the present embodiment. Fig. 22 is a schematic graph for explaining the above-described reading operation.

In step S301, the flag is set to "0". The flag is recorded in a register or the like.

In step S101, the same operation as that in step S101 described with reference to fig. 8 and the like is performed.

In step S302, the current I of the voltage supply line 41 is detected_CCDetermining whether the current is greater than a specific threshold current I_TH. For example, the node N3 of the switch circuit 52a in fig. 20 is brought into contact with the node N4 for a certain sampling time, and it is determined whether or not the voltage of the node N3 becomes larger than the reference voltage V during this period_REF. The process proceeds to step S303 when the size is increased, and proceeds to step S304 when the size is not increased. Further, in step S302, the node N3 of the switch circuit 52a is then brought into contact with the node N5, releasing the charge of the node N3.

In step S303, the flag is set to "1".

In step S304, it is determined whether or not a specific time has elapsed since execution of step S101, with reference to a timer or the like, not shown. If the specific time has not elapsed, the process proceeds to step S302. If the specific time has elapsed, the process proceeds to step S305.

In step S305, it is determined whether the flag is "1". If "1", the process proceeds to step S306. If not "1", the process proceeds to step S103.

In step S306, it is determined whether or not a specific time has elapsed since execution of step S305, with reference to a timer or the like, not shown. If the specific time has not elapsed, the process proceeds to step S306. If the specific time has elapsed, the process proceeds to step S103.

In step S103 to step S109, the same operations as those in step S103 to step S109 described with reference to fig. 8 and the like are performed.

Here, for example, as illustrated in fig. 9, when the voltage of the word line WL has a certain level due to a creep or the like, the voltage of the word line WL is set from the voltage V₁Increase to a voltage V_READDuring the period (2), a current I flowing through the voltage supply line 41₁Is relatively small. On the other hand, as illustrated in fig. 18A, for example, the voltage on the word line WL is the ground voltage V_SSIn the case of left and right sides, the voltage of the word line WL is from the ground voltage V_SSIncrease to a voltage V_READDuring the period (2), a current I flowing through the voltage supply line 41₂Is relatively large. Therefore, for example, as illustrated in fig. 22, the current I flowing through the voltage supply line 41 can be used_CCIs greater than a certain threshold current I_THTo adjust the timing T₁₀₁To time sequence T₁₀₂Waiting time t of₁. Thus, a semiconductor memory device which operates at high speed without losing reliability can be provided.

In addition, depending on conditions and the like, the current detection circuit 50 according to the present embodiment may be able to detect the state of the word line WL and the like more accurately than the voltage detection circuit 42 according to embodiment 1.

As described above, the boosting rate of the word line WL or the like may vary depending on manufacturing errors, layout, and the like. Even in this case, the reading operation of the present embodiment can be executed. In this case, for example, it is considered that the waiting time t is set when the average value, the maximum value, and the like of the boosting rate are small (when the average value, the maximum value, and the like of the current are small)₁If the average value, the maximum value, and the like of the boosting rate are set to be large (if the average value, the maximum value, and the like of the current are large), the standby time is set to be longTime t₁Set to be smaller. In this case, for example, in step S305 in fig. 21, it is determined whether or not the flag is "0". If "0", the process proceeds to step S306. If not "0", the process proceeds to step S103.

[ 4 th embodiment ]

Next, embodiment 4 will be described with reference to fig. 23. Fig. 23 is a schematic graph for explaining the reading operation of the present embodiment.

The semiconductor memory device of the present embodiment is configured in the same manner as the semiconductor memory device of embodiment 3.

The reading operation of the present embodiment is almost the same as that of embodiment 3. However, in the present embodiment, in step S302 (fig. 21), the current I of the voltage supply line 41 is not detected_CCInstead, the amount of charge supplied from the voltage supply line 41 is detected, and it is determined whether the amount of charge is larger than a specific threshold value. For example, the node N4 is brought into contact with the node N3 of the switch circuit 52a in fig. 20, and it is determined whether or not the voltage of the node N3 becomes larger than the reference voltage V_REF. The process proceeds to step S303 when the size is increased, and proceeds to step S304 when the size is not increased. In the present embodiment, unlike embodiment 3, the node N3 of the switch circuit 52a is kept in contact with the node N4 until the flag is set to "1" or until step S304 is completed.

As described above, the boosting rate of the word line WL or the like may vary depending on manufacturing errors, layout, and the like. Even in this case, the reading operation of the present embodiment can be executed.

[ other embodiments ]

In the above description, the timing T for adjusting the read operation is adjusted₁₀₁～T₁₀₂The example of the waiting time t1 is explained. However, other latencies can also be adjusted by utilizing the method as described.

In the above description, an example of adjusting the waiting time of the specific timing in the normal read operation is described. However, the waiting time in other actions can also be adjusted by using the method as described above.

For example, the write action includes a program action and a write verify action.

In the programming operation, for example, as shown in fig. 24, at a timing T₂₀₁For bit line BL connected to memory cell MC for threshold voltage adjustment_WSupply ground voltage V_SSFor bit line BL connected to memory cell MC not subjected to threshold voltage adjustment_ISupply inhibit voltage V_DDSA. Inhibit voltage V_DDSAGreater than ground voltage V_SS。

In addition, in the programming operation, for example, at the timing T₂₀₂Supply voltage V to selected drain select line sSGD_SGDA voltage V is supplied to a non-selected drain selection line uSGD and a source selection line SGS_SGSSupplying a voltage V to the word line WL_DD-V_th. Voltage V_SGDE.g. less than the voltage V of fig. 10_SGHaving a bit line BL_WThe corresponding drain select transistor STD is turned on and connected to the bit line BL_IThe corresponding drain select transistor STD is in an off state.

In addition, in the programming operation, for example, at the timing T₂₀₃Supplying a write pass voltage V to the word line WL_PASS. Write pass voltage V_PASSFor example, may be greater than the read pass voltage V of fig. 7_READ。

In the programming operation, at the timing T₂₀₄A program voltage V is supplied to the selected word line sWL_PGM. Programming voltage V_PGMCan be larger than the write pass voltage V_PASS. Thereby, electrons are stored in the charge storage film 132 (fig. 7) of the desired memory cell MC, and the threshold voltage of the memory cell MC increases.

Thereafter, e.g. at time T₂₀₅The voltage of the selected word line sWL is lowered to the write pass voltage V_PASSUntil now. In addition, for example, at the timing T₂₀₆Make the bit line BL_IIs lowered to the ground voltage V_SSUntil now. In addition, for example, at the timing T₂₀₇Energizing word line WLThe pressure is reduced to V_DD-V_thUntil that time, the voltage of the selection gate line (SGD, SGS) is lowered to the grounding voltage V_SSUntil now.

Here, as illustrated in fig. 25, for example, the initial voltage of the word line WL in the programming operation may be relatively increased by the creep or the like. On the other hand, as illustrated in fig. 26, the initial voltage of the word line WL in the program operation is the ground voltage V_SSEtc. become relatively small. In this case, as illustrated in fig. 25 and 26, the same method as that of embodiments 1 to 4 may be used. To adjust the supply of a write pass voltage V to the word line WL_PASSTime sequence T of₂₀₃And timing T₂₀₄Waiting time t in between₂。

Further, as illustrated in fig. 27 and 28, for example, the voltage of the word line WL may rise relatively early or relatively late due to a difference in RC time constant or the like. In this case, the timing T can be corrected by the same method as in embodiments 1 to 4₂₀₃And timing T₂₀₄Waiting time t in between₂The adjustment can be made to the time sequence T₂₀₄And timing T₂₀₅Waiting time t in between₃And (6) adjusting.

The write verify action is performed after the program action is performed. The write verify operation is an operation of confirming whether or not the threshold voltage of the memory cell MC is increased to a desired level by the program operation. The write verify action is performed in much the same way as the normal read action. In this case, the waiting time t can be performed in the same manner as in the normal read operation₁And (4) adjusting.

In addition, the waiting time in various operations can be adjusted by the same method as in embodiments 1 to 4, such as the deletion verification operation performed in the deletion operation.

In the present specification, the term "read operation" may mean a case including not only a normal read operation but also a write verify operation, an erase verify operation, and the like.

In the above description, an example of detecting an increase in voltage, current, or the like is described. However, for example, a drop in voltage, current, or the like can also be detected. In this case, for example, only the reference voltage V is used_REFThe target value is set higher, and it is sufficient to detect whether the output signal of the comparison circuit 44 or 53 becomes "L" instead of detecting whether the output signal of the comparison circuit 44 or 53 becomes "H".

[ others ]

Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in other various ways, and various omissions, substitutions, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.