阅读说明：本技术 栅极路径中具有扼流圈的并联功率半导体 (Parallel power semiconductor with choke in gate path ) 是由 徐帆 陈礼华 于 2020-03-10 设计创作，主要内容包括：本公开提供“栅极路径中具有扼流圈的并联功率半导体”。功率电子电路具有：一对并联功率半导体,其各自包括栅极和电流传感器；第一差模扼流圈,其限定连接栅极的栅极路径的一部分；第二差模扼流圈,其限定连接电流传感器的传感器路径的一部分；和栅极驱动器,其分接栅极路径和电流传感器路径。(The present disclosure provides a "parallel power semiconductor with a choke in the gate path". The power electronic circuit has: a pair of parallel power semiconductors each including a gate and a current sensor; a first differential mode choke defining a portion of a gate path connecting the gates; a second differential mode choke defining a portion of a sensor path connecting the current sensor; and a gate driver that taps the gate path and the current sensor path.)

1. A power electronic circuit, comprising:

a pair of parallel power semiconductors including gates connected via a gate path and a current sensor connected via a sensor path;

a gate driver that taps the gate path and the sensor path;

a first differential mode choke comprising a pair of windings defining a portion of the gate path and sharing a positive terminal with the gate driver; and

a second differential mode choke comprising a pair of windings defining a portion of the sensor path and sharing a negative terminal with the gate driver.

2. The power electronic circuit of claim 1, wherein an impedance of the winding of the second differential mode choke is greater than a junction capacitance of the current sensor and an equivalent impedance of the parallel power semiconductors.

3. The power electronic circuit of claim 1, wherein each of the first and second differential mode chokes comprises a magnetic core, and wherein the winding of each of the first and second differential mode chokes is wound on one of the magnetic cores.

4. The power electronic circuit of claim 1, further comprising a printed circuit board, wherein the windings of the first and second differential mode chokes are mounted directly on the printed circuit board.

5. The power electronic circuit of claim 1, further comprising a printed circuit board, wherein the windings of the first and second differential mode chokes are traces in different layers of the printed circuit board.

6. A power electronic circuit, comprising:

a pair of parallel power semiconductors each including a gate and a current sensor;

a first differential mode choke defining a portion of a gate path connecting the gates;

a second differential mode choke defining a portion of a sensor path connecting the current sensor; and

a gate driver that taps the gate path and the current sensor path.

7. The power electronic circuit of claim 6, wherein the first differential mode choke comprises a pair of windings sharing a positive terminal of the gate driver.

8. The power electronic circuit of claim 7, wherein the first differential mode choke further comprises a magnetic core, and wherein the winding is wound on the magnetic core.

9. A power electronic circuit according to claim 8, wherein the impedance of the winding is greater than the junction capacitance of the current sensor and the equivalent impedance of the parallel power semiconductors.

10. The power electronic circuit of claim 6, wherein the second differential mode choke comprises a pair of windings sharing a negative terminal of the gate driver.

11. The power electronic circuit of claim 6, further comprising a printed circuit board, wherein each of the first differential mode choke and the second differential mode choke comprises a winding that is mounted directly on the printed circuit board.

12. The power electronic circuit of claim 6, further comprising a printed circuit board, wherein each of the first and second differential mode chokes comprises a winding implemented as a trace in a different layer of the printed circuit board.

13. A power electronic circuit, comprising:

parallel power semiconductors associated with a printed circuit board, each of the parallel power semiconductors including a gate and a current sensor;

a first differential mode choke comprising a first core and a first pair of traces in different layers of the printed circuit board surrounding the first core and defining windings of the first differential mode choke, wherein the first differential mode choke is located in a gate path connecting the gates;

a second differential mode choke comprising a second magnetic core and a second pair of traces in a different layer of the printed circuit board, the second pair of traces surrounding the second magnetic core and defining windings of the second differential mode choke, wherein the second differential mode choke is located in a sensor path connecting the current sensor; and

a gate driver including a positive terminal tapping the gate path and a negative terminal tapping the sensor path.

14. The power electronic circuit of claim 13, wherein the winding of the first differential mode choke shares a terminal with the positive terminal.

15. The power electronic circuit of claim 13, wherein the winding of the second differential mode choke shares a terminal with the negative terminal.

Technical Field

The present disclosure relates to power semiconductor devices.

Background

Power semiconductors are used as switches or rectifiers in certain power electronic devices, such as switched mode power supplies. Power semiconductors are also referred to as power devices or, when used in integrated circuits, as power Integrated Circuits (ICs). Power semiconductors are typically used in commutation mode (which is on or off) and have a design optimized for such use. Power semiconductors are used in systems that deliver tens of milliwatts (e.g., headphone amplifiers) and systems that deliver gigawatts (e.g., high voltage direct current (hvdc) power lines).

Some Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are a type of power semiconductor, a depletion channel device: establishing a conduction path from drain to source may require a voltage rather than a current. At low frequencies, this may reduce the gate current, as it only needs to charge the gate capacitance during switching. The switching time ranges from tens of nanoseconds to hundreds of microseconds. Generally, MOSFET devices are not bi-directional and are not reverse voltage blocking.

Insulated Gate Bipolar Transistors (IGBTs) are another type of power semiconductor, typically having characteristics common to Bipolar Junction Transistors (BJTs) and MOSFETs. It may have a high gate impedance and therefore a low gate current requirement, such as a MOSFET. It may also have a low on-state voltage drop in the operating mode, such as a BJT. Some IGBTs can be used to block both positive and negative voltages and have reduced input capacitance compared to MOSFET devices.

Disclosure of Invention

The power electronic circuit has: a pair of parallel power semiconductors including gates connected via a gate path and a current sensor connected via a sensor path; a gate driver that taps the gate path and the sensor path; a first differential mode choke comprising a pair of windings defining a portion of the gate path and sharing a positive terminal with the gate driver; and a second differential mode choke comprising a pair of windings defining a portion of the sensor path and sharing a negative terminal with the gate driver.

The power electronic circuit has: a pair of parallel power semiconductors each including a gate and a current sensor; a first differential mode choke defining a portion of a gate path connecting the gates; a second differential mode choke defining a portion of a sensor path connecting the current sensor; and a gate driver that taps the gate path and the current sensor path.

The power electronic circuit has parallel power semiconductors associated with the printed circuit board. Each of the parallel power semiconductors includes a gate and a current sensor. The circuit also has a first differential mode choke that includes a first core and a first pair of traces in different layers of the printed circuit board that surround the first core and define windings of the first differential mode choke. The first differential mode choke is located in a gate path connecting the gates. The circuit also has a second differential mode choke that includes a second core and a second pair of traces in a different layer of the printed circuit board that surround the second core and define windings of the second differential mode choke. A second differential mode choke is located in the sensor path connecting the current sensor. The circuit also has a gate driver that includes a positive terminal of the tapped gate path and a negative terminal of the tapped sensor path.

Drawings

Fig. 1 is a circuit diagram of a parallel power semiconductor.

Fig. 2 is a graph of gate voltage oscillation associated with the circuit diagram of fig. 1.

Fig. 3 is a circuit diagram of two parallel power devices with an on-chip current sensor cell.

Fig. 4 is a circuit diagram of the proposed choke in two parallel power devices.

Fig. 5 is a schematic diagram of a Differential Mode (DM) choke mounted/soldered on a gate drive PCB.

Fig. 6 is a schematic diagram of a DM choke based on a PCB winding.

Fig. 7 is a schematic diagram of a DM choke proposed based on a Printed Circuit Board (PCB) winding integrated with a gate driving PCB.

Fig. 8 is a schematic diagram of a DM choke proposed based on PCB windings inside a power supply module.

Detailed Description

Various embodiments of the present disclosure are described herein. However, the disclosed embodiments are merely exemplary, and other embodiments may take various and alternative forms not explicitly shown or described. The figures are not necessarily to scale; some features may be exaggerated or minimized to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the present invention. As one of ordinary skill in the art will appreciate, various features illustrated and described with reference to any one of the figures may be combined with features illustrated in one or more other figures to produce embodiments that are not explicitly illustrated or described. The combination of features shown provides a representative embodiment of a typical application. However, various combinations and modifications of the features consistent with the teachings of the present disclosure may be desired for particular applications or implementations.

For high power applications, such as traction inverters in electric vehicles, power semiconductors are often used in parallel to achieve higher power capacity. Fig. 1 shows a circuit 10 with parallel power switching elements 12, 14. The switching elements 12, 14 include active power semiconductors 16, 18 (e.g., IGBTs, MOSFETs, etc.), respectively, with or without antiparallel power diodes 20, 22. The power switching elements 12, 14 have two power terminals, the drain D₁、D₂And source S₁、S₂And two control terminals, a gate G₁、G₂And Kelvin source KS₁、KS₂. (in the context of IGBT technology, the power supply terminals will be replaced by collectors and emitters, whereas the control terminals will comprise Kelvin emitters instead of Kelvin sources.) respective gates G₁、G₂And Kelvin source KS₁、KS₂Corresponding gate loops are included to control the power switching elements 12, 14. The circuit 10 further includes a gate driver integrated circuit 24 common to the gate loops and electrically connected to the gate G₁And a resistor R between the gate driver integrated circuit 24_G1And electrically connected to the gate G₂And a resistor R between the gate driver integrated circuit 24_G2. In addition, a gate path 26 electrically connects the gate G₁、G₂(ii) a Kelvin path 28 electrically connects Kelvin sources KS₁、KS₂(ii) a And the source path 30 electrically connects the source S₁、S₂。

During power semiconductor switching transients, the switching on/off transient currents of the power semiconductors 12, 14 are typically unbalanced for the following reasons: associated parameterPiece-to-piece variation, non-uniform bus bar layout, and/or unbalanced junction capacitance and circuit stray inductance. These unbalanced currents may result in a potential difference (V) on the emitter/source side_KS1-V_KS2≠0、V_S1-V_S2Not equal to 0). Ideally, the voltage difference should be kept at zero. Voltage difference (V)_KS1-V_KS2) The semiconductor junction capacitance and the circuit stray inductance induce oscillations in the gate loop. The oscillation is not controllable and may result in the gate voltage on the power semiconductors 12, 14 oscillating with a high amplitude (V)_G1-V_KS1，V_G2-V_KS2). Fig. 2 shows a simulated oscillating gate voltage waveform. Voltages in excess of the nominal gate voltage can be problematic. In addition, the switching speed of the parallel silicon carbide MOSFET is much faster than that of the silicon MOSFET, and thus gate voltage oscillation is easily generated.

Some power semiconductors have on-chip current sensors, which are semiconductor units. The current flowing through the current sensor unit is 1/n of the current flowing through the main semiconductor unit n. The current sensed by the sensor unit is used to measure the main supply current and fed back to the low power control circuit for applications such as overcurrent protection. In each power semiconductor chip, the current sensor cell gate G and drain D terminals are connected to the main cell, but its terminal SS is separated from the main cell kelvin terminal KS.

Fig. 3 shows a circuit 32 of parallel power semiconductors 33, 34 with on-chip current sensors 36, 38 (e.g., IGBTs, MOSFETs) and a gate driver integrated circuit 40. The current sensors 36, 38 share common drain, gate and kelvin sources with the power semiconductors 32, 34, respectively. That is, the power semiconductor 33 and the current sensor 36 share the drain terminal D₁And a gate terminal G₁And Kelvin source KS₁. In addition, the power semiconductor 34 and the current sensor 38 share the drain terminal D₂And a gate terminal G₂And Kelvin source KS₂. KS as described above₁And KS₂Will also result in a current sensor gate voltage V_G1-SS1、V_G2-SS2And (6) oscillating. Because of the current transmissionThe inductors 36, 38 have a small junction capacitance so they may experience problems before the power semiconductors 33, 34 experience problems.

In order to eliminate or reduce gate voltage oscillations of the parallel power semiconductors, the gate path impedance should be large enough to suppress the oscillation current. However, the larger impedance in the gate path reduces the power device switching speed and increases the switching losses. Here, Differential Mode (DM) chokes in both the gate path and the current sensor path are proposed to avoid gate oscillations and potential breakdowns of both the main cell and the current sensor cell of the power device.

Fig. 4 shows the proposed circuit 42 for parallel power semiconductors 44, 46 with on-chip current sensors 48, 50, a gate driver integrated circuit 52 and DM chokes 54, 56. Gate path 58 is electrically connected to gate G₁、G₂(ii) a Kelvin path 60 connects Kelvin sources KS₁、KS₂(ii) a The source path 62 connects the source S₁、S₂(ii) a And a sensor path 64 connects the sensors 48, 50. The DM choke 54 is located in the gate path 58 and includes windings 66, 68 that share a positive terminal 69 of the gate driver integrated circuit 52. Similarly, the DM choke 56 is located in the sensor path 64 and includes windings 70, 72 that share a negative terminal 73 of the gate driver integrated circuit 52. The negative terminal 73 also taps the kelvin path 60. If there is no gate path oscillating current during a switching transient in the gate path 58, the equivalent impedance of the windings 66, 68 is zero because the gate currents in the gate paths are equal and opposite in direction and the magnetic fluxes in the windings 66, 68 cancel each other out. At the same time, in order to oscillate the current from one power device to another through its gate path, each winding will have the equivalent impedance L of the magnetizing inductance_DM1For two parallel power devices 44, 46, the oscillating current path (gate path 58) will have 2 × L_DM1The equivalent impedance of (2).

Similarly, the impedance L of the windings 70, 72_DM2Should be much larger than the equivalent impedance of the power device main cell and sensor cell junction capacitances. Therefore, has a high amplitude and an oscillating potential difference (V)_KS1-V_KS2) Will be at L_DM2Up and down instead of the main cell or sensor cell gates to prevent them from degrading.

Fig. 4 shows two parallel power devices 44, 46. However, the arrangement contemplated herein may be extended to applications with N power devices in parallel (N > 2). In this case, chokes should be used in the gate path and sensor path of each corresponding two devices, which means that there will be an N-1 choke in the gate path and an N-1 choke in the sensor path. Furthermore, several implementations of the schematic arrangement of fig. 4 are presented below. Only chokes for two parallel devices are shown, but all implementations, as well as other implementations contemplated herein, may also be applied to N parallel power device systems.

Referring to fig. 5, the DM chokes 54, 56 include magnetic cores 55, 57, respectively. If wires are used to implement the windings 66, 68, 70, 72, they may be mounted/soldered directly to a Printed Circuit Board (PCB)74 of the gate driver integrated circuit 52. The windings 66, 68, 70, 72 are then connected to the power semiconductor module terminals G in a suitable manner by means of PCB tracks₁、G₂、SS₁、SS₂。

The windings 66, 68, 70, 72 may be implemented as PCB traces in different layers. Referring to fig. 6, given the orientation shown, the windings 66 are implemented in layers above the windings 68 of the PCB 74. The windings 70, 72 may be similarly arranged. The windings 66, 68, 70, 72 may then be connected to the power semiconductor modules 44, 46, as shown in fig. 7.

Referring to fig. 8, the proposed DM choke 54, 56 with PCB windings can also be integrated inside the power module that encapsulates the parallel power semiconductors 44, 46. Different ones of the windings 66, 68, 70, 72 may be implemented in different PCB layers. As described above, the windings 66, 68, 70, 72 may be connected to the power semiconductor control terminals/pads and power module external terminals (leads) 76, 78 by direct soldering or wire bonding.

The described embodiments include DM chokes in the power semiconductor gate path and the on-chip current sensor source path operating in parallel. And theseSome associated possible advantages of the arrangement are summarized below. The proposed choke can prevent gate breakdown of both the main cell and the current sensor cell during parallel operation of the power semiconductors. The additional elements required to implement a DM choke are passive: this is a simpler and cheaper option than an active element. The proposed choke is added to the gate drive loop, which is a low power control loop, so that the extra losses generated by the choke are negligible. The DM choke can be implemented inside the power supply module or on the gate drive PCB (outside the power supply module) and does not take up much extra space. Due to the coupling of the windings, the power semiconductor main cell and the on-chip current sensor cell gate loop inductance do not increase after the addition of the proposed choke. Thus, the power semiconductor switching transient time and switching losses do not increase. Choke winding impedance value (e.g., L)_DM1，L_DM2The required value can be adjusted for different power semiconductor parallel conditions. The proposed method of increasing the choke and its implementation are not limited by the number of power semiconductors in the traction inverter. The choke can be applied to any type of power semiconductor, such as MOSFET, IGBT, etc.

The words used in the specification are words of description rather than limitation, and it is understood that various changes may be made without departing from the spirit and scope of the disclosure and claims. As previously mentioned, features of the various embodiments may be combined to form further embodiments that may not be explicitly described or illustrated. While various embodiments may have been described as providing advantages over or being preferred over other embodiments or prior art implementations in terms of one or more desired characteristics, one of ordinary skill in the art will recognize that one or more features or characteristics may be compromised to achieve desired overall system attributes, which depend on the particular application and implementation. These attributes include, but are not limited to, cost, strength, durability, life cycle cost, marketability, appearance, packaging, size, serviceability, weight, manufacturability, ease of assembly, and the like. Accordingly, embodiments described as having one or more characteristics that are less desirable than other embodiments or prior art implementations are outside the scope of this disclosure and may be desirable for particular applications.

According to the invention, there is provided a power electronic circuit having: a pair of parallel power semiconductors including gates connected via a gate path and a current sensor connected via a sensor path; a gate driver that taps the gate path and the sensor path; a first differential mode choke comprising a pair of windings defining a portion of the gate path and sharing a positive terminal with the gate driver; and a second differential mode choke comprising a pair of windings defining a portion of the sensor path and sharing a negative terminal with the gate driver.

According to an embodiment, the impedance of the winding of the second differential mode choke is larger than the junction capacitance of the current sensor and the equivalent impedance of the parallel power semiconductors.

According to an embodiment, each of the first and second differential mode chokes comprises a magnetic core.

According to an embodiment, the winding of each of the first and second differential mode chokes is wound on one of the magnetic cores.

According to an embodiment, the invention also features a printed circuit board, wherein the windings of the first differential mode choke and the second differential mode choke are mounted directly on the printed circuit board.

According to an embodiment, the invention also features a printed circuit board, wherein the windings of the first differential mode choke and the second differential mode choke are traces in different layers of the printed circuit board.

According to an embodiment, the parallel power semiconductors are metal oxide semiconductor field effect transistors, each comprising a kelvin source connected via a kelvin path, and wherein the gate driver further taps the kelvin path.

According to an embodiment, the parallel power semiconductors are insulated gate bipolar transistors, each comprising a kelvin emitter connected via a kelvin path, and wherein the gate driver further taps the kelvin path.

According to the invention, there is provided a power electronic circuit having: a pair of parallel power semiconductors each including a gate and a current sensor; a first differential mode choke defining a portion of a gate path connecting the gates; a second differential mode choke defining a portion of a sensor path connecting the current sensor; and a gate driver that taps the gate path and the current sensor path.

According to an embodiment, the first differential mode choke comprises a pair of windings sharing a positive terminal of the gate driver.

According to an embodiment, the first differential mode choke further comprises a magnetic core, and wherein the winding is wound on the magnetic core.

According to an embodiment, the impedance of the winding is larger than the junction capacitance of the current sensor and the equivalent impedance of the parallel power semiconductors.

According to an embodiment, the second differential mode choke comprises a pair of windings sharing a negative terminal of the gate driver.

According to an embodiment, each of the first and second differential mode chokes comprises a magnetic core.

According to an embodiment, each of the first and second differential mode chokes comprises a winding wound on one of the magnetic cores.

According to an embodiment, the invention also features a printed circuit board, wherein each of the first differential mode choke and the second differential mode choke includes a winding that is directly mounted on the printed circuit board.

According to an embodiment, the invention also features a printed circuit board, wherein each of the first differential mode choke and the second differential mode choke includes a winding that is a trace in a different layer of the printed circuit board.

According to the invention, a power electronic circuit is provided, having: parallel power semiconductors associated with the printed circuit board, each of the parallel power semiconductors including a gate and a current sensor; a first differential mode choke comprising a first core and a first pair of traces in different layers of the printed circuit board, the first pair of traces surrounding the first core and defining a winding of the first differential mode choke, wherein the first differential mode choke is located in a gate path connecting the gates; a second differential mode choke comprising a second magnetic core and a second pair of traces in a different layer of the printed circuit board, the second pair of traces surrounding the second magnetic core and defining a winding of the second differential mode choke, wherein the second differential mode choke is located in a sensor path connecting the current sensor; and a gate driver including a positive terminal of the tapped gate path and a negative terminal of the tapped sensor path.

According to an embodiment, the winding of the first differential mode choke shares a terminal with the positive terminal.

According to an embodiment, the winding of the second differential mode choke shares a terminal with the negative terminal.