阅读说明：本技术 限制由多个处理器产生的总热量的基于目标意图的时钟速度确定和调整 (Targeted intent based clock speed determination and adjustment to limit total heat generated by multiple processors ) 是由 G·M·林克 于 2020-02-06 设计创作，主要内容包括：功率配置文件库包括多个功率配置文件,其中,每个功率配置文件具有用于相应的处理器的多个最大时钟速度。选择每个功率配置文件中的最大时钟速度以限制处理器共同产生的每单位时间最大热量。开发者计算机系统针对消费者设备选择最终应用程序的各段,并针对每个段选择目标意图。功率配置文件查找使用目标意图来确定用于每个段的功率配置文件。(The library of power profiles includes a plurality of power profiles, wherein each power profile has a plurality of maximum clock speeds for a respective processor. The maximum clock speed in each power profile is selected to limit the maximum amount of heat per unit time that the processors collectively generate. The developer computer system selects segments of the final application for the consumer device and selects a target intent for each segment. The power profile lookup uses the target intent to determine a power profile for each segment.)

1. A host computer system, comprising:

a host computer processor;

a computer readable medium connected to the host computer processor; and

a set of instructions on the computer readable medium readable by the host computer processor and comprising:

a structured application development system having:

a power profile database on the computer readable medium comprising:

a first reference intent;

a first power profile associated with the first intent to reference and having a respective first maximum clock speed for a first processor and a respective second maximum clock speed for a second processor;

a second reference intent; and

a second power profile associated with the second intent to reference and having a respective first maximum clock speed for the first processor and a respective second maximum clock speed for the second processor, the first maximum clock speed of the first power profile being different from the first maximum clock speed of the second power profile.

2. The host computer system of claim 1,

the structured application development system has:

a structured intent system, comprising:

a set of target intents including a first target intent and a second target intent;

an intent selection interface that selects a first segment and a second segment and selects a target intent from the set of target intents for association with the first segment and the second segment, respectively; and

a power profile lookup that determines, for each of the first and second segments, a power profile for the respective segment from the power profile data by matching a target intent selected for the respective segment with a reference intent to associate a power profile.

3. The host computer system of claim 2,

the structured application development system has:

a development kit, comprising:

a tool set;

a tool selection interface that selects tools from the toolset and arranges the tools in a customizable order for the first segment and the second segment;

application development logic configured to generate an application based on the order in which the tools are arranged for the first segment and the second segment, the application executable by a processor of a consumer device; and

power limiting logic, as a result of associating each of the first segment and the second segment with a respective power profile, configured to limit the first processor and the second processor to the maximum clock speed of the respective power profile for the respective segment when the respective segment is executed on a consumer device having the first processor and the second processor.

4. The host computer system of claim 3, wherein the intent selection interface is accessible from a developer computer system over a network to select the first segment and the second segment and to select the target intent from the set of target intents for association with the first segment and the second segment, respectively.

5. The host computer system of claim 3, wherein the intent selection interface is accessible from a developer computer system over a network to select the tools from the set of tools and arrange the tools in a customizable order for the first and second segments.

6. The host computer system of claim 3, wherein the power limit logic inserts the maximum clock speed for the respective power profile for the respective segment into the application.

7. The host computer system of claim 6, wherein the structured application development system further has:

a download interface accessible from a developer computer system over a network to download the application from the host computer system onto the developer computer system with the maximum clock speed for the respective power profile for the respective segment in the application.

8. The host computer system of claim 1, wherein the second maximum clock speed of the first power profile is different from the second maximum clock speed of the second power profile.

9. The host computer system of claim 1, wherein the second maximum clock speed of the first power profile is the same as the second maximum clock speed of the second power profile.

10. A method of operating a host computer system, comprising:

storing a power profile database on a computer readable medium, the power profile database comprising:

a first reference intent;

a first power profile associated with the first intent to reference and having a respective first maximum clock speed for a first processor and a respective second maximum clock speed for a second processor;

a second reference intent; and

a second power profile associated with the second intent to reference and having a respective first maximum clock speed for the first processor and a respective second maximum clock speed for the second processor, the first maximum clock speed of the first power profile being different from the first maximum clock speed of the second power profile.

11. The method of claim 10, further comprising:

storing a set of target intents including a first target intent and a second target intent on the computer-readable medium;

displaying, with a host computer processor, an intent selection interface to select a first segment and a second segment and to select a target intent from the set of target intents for association with the first segment and the second segment, respectively; and

performing, with the host computer processor, a power profile lookup that determines, for each of the first segment and the second segment, a power profile for the respective segment from the power profile data by matching a target intent selected for the respective segment with a reference intent to associate a power profile.

12. The method of claim 11, further comprising:

storing a toolset on the computer-readable medium;

displaying, with the host computer processor, a tool selection interface to select tools from the set of tools and arrange the tools in a customizable order for the first segment and the second segment;

executing, with the host computer processor, application development logic that generates an application based on the order in which the tools are arranged for the first segment and the second segment, the application executable by a processor of a consumer device; and

executing power limiting logic with the host computer processor that limits the first processor and the second processor to the maximum clock speed for the respective power profile of the respective segment as a result of associating each of the first segment and the second segment with a respective power profile when the respective segment is executed on a consumer device having the first processor and the second processor.

13. A consumer device, comprising:

a multi-core processor chip having a body and a plurality of processors on the body;

a computer readable medium connected to the processor; and

an application on the computer readable medium, the application having:

a first segment having:

a first routine executable by the processor; and

a first power profile having a respective maximum clock speed for each of the processors; and

a second segment having:

a second routine executable by the processor; and

a second power profile having a respective maximum clock speed for each of the processors such that at least one of the processors has a maximum clock speed that changes from the first segment to the second segment, wherein the processors collectively generate a first amount of heat per unit time during the first segment and collectively generate a second amount of heat during the second segment, the second amount of heat differing from the first amount of heat by less than 10%.

14. The consumer device of claim 13, wherein the second amount of heat is the same as the first amount of heat.

15. The consumer device of claim 13, wherein the first processor and the second processor have different heat generation profiles.

16. The consumer device of claim 13, wherein the processor comprises at least a first processor and a second processor, the second processor generating less heat per unit time during the first period than the first processor and more heat per unit time during the second period than the first processor, wherein the processor comprises at least a third processor, the third processor generating less heat per unit time during the first period than the first processor and more heat per unit time during the second period than the first processor.

17. The consumer device of claim 13, further comprising:

a third section having:

a third routine executable by the processor; and

a third power profile having a respective maximum clock speed for each of the processors such that at least one of the processors has a maximum clock speed that changes from the first segment to the third segment, wherein the processors collectively generate a third amount of heat per unit time during the third segment, and the third amount of heat differs from the first amount of heat by less than 10%.

18. A method of operating a consumer device, comprising:

storing an application on the computer readable medium, the computer readable medium connected to a plurality of processors on a body of a multicore processor chip, the application having a first segment and a second segment;

executing, with the processor, the first segment having:

a first routine executable by the processor; and

a first power profile having a respective maximum clock speed for each of the processors; and

executing, with the processor, the second segment having:

a second routine executable by the processor; and

a second power profile having a respective maximum clock speed for each of the processors such that at least one of the processors has a maximum clock speed that changes from the first segment to the second segment, wherein the processors collectively generate a first amount of heat per unit time during the first portion and a second amount of heat during the second portion, and the second amount of heat differs from the first amount of heat by less than 10%.

19. A consumer device, comprising:

a first processor and a second processor;

a computer readable medium connected to the processor; and

an application on the computer readable medium, the application having:

a first segment having:

a first routine executable by the first and second processors; and

a first power profile having a first maximum clock speed and a second maximum clock speed for the first processor and the second processor; and

a second segment having:

a second routine executable by the first processor and the second processor; and

a second power profile having a first maximum clock speed and a second maximum clock speed for the first processor and the second processor, the first maximum clock speed of the first power profile being different from the first maximum clock speed of the second power profile, and the second maximum clock speed of the first power profile being different from the second maximum clock speed of the second power profile.

20. The consumer device of claim 19, further comprising:

a multi-core processor chip that holds the first processor and the second processor.

21. The consumer device of claim 19, wherein the first processor and the second processor have different heat generation profiles.

Technical Field

The invention relates to a structured application development system.

Background

A consumer device, such as a personal computer, smart phone, stereoscopic viewer, mixed reality viewer, etc., has a storage medium for storing an application program and one or more processors that execute routines of the application program. Such applications include operating systems and other applications (such as games, browsers, etc.) that perform numerous tasks.

A multi-core processor chip includes more than one processor core. These processor cores may include, for example, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), vector processing, and the like. When an application developer develops an application for running on multiple processors, the developer programs the clock speeds of the various processors.

Each processor generates heat per unit time that increases as the clock speed rises. A multi-processor chip can typically dissipate all of the heat of one processor running at 100% of its maximum clock speed. However, when all processors are running at 100% of their maximum clock speed, the multicore processor chip may not be able to release all of the heat generated by all processors, which may result in damage to the circuitry of the processors of the multicore processor chip. There may be specifications for the clock speed of a multicore processor chip that detail how the clock speed should be limited to limit the maximum amount of heat generated per unit time by all processors. There is a risk that the developer may ignore the specification, which will result in damage to the multicore processor chip.

Disclosure of Invention

According to one aspect of the present invention, there is provided a host computer system comprising a host computer processor, a computer readable medium connected to the host computer processor, and a set of instructions on the computer readable medium, the set of instructions being readable by the host computer processor and comprising a structured application development system having a power profile database on the computer readable medium, the power profile database comprising: a first reference intent; a first power profile associated with the first intent-to-reference and having a respective first maximum clock speed for the first processor and a respective second maximum clock speed for the second processor; a second reference intent; and a second power profile associated with the second intent-to-reference and having a respective first maximum clock speed for the first processor and a respective second maximum clock speed for the second processor, the first maximum clock speed of the first power profile being different from the first maximum clock speed of the second power profile.

The present invention also provides a method of operating a host computer system, comprising: storing a power profile database on a computer readable medium, the power profile database comprising: a first reference intent; a first power profile associated with the first intent-to-reference and having a respective first maximum clock speed for the first processor and a respective second maximum clock speed for the second processor; a second reference intent; and a second power profile associated with the second intent to reference and having a respective first maximum clock speed for the first processor and a respective second maximum clock speed for the second processor, the first maximum clock speed of the first power profile being different from the first maximum clock speed of the second power profile.

The present invention also provides a consumer device comprising: a multi-core processor chip having a body and a plurality of processors on the body; a computer readable medium connected to the processor; and an application on the computer readable medium, the application having: a first segment having a first routine executable by the processors and a first power profile having a respective maximum clock speed for each processor; and a second section having a second routine executable by the processors and a second power profile having a respective maximum clock speed for each processor such that at least one processor has a maximum clock speed that changes from the first section to the second section, wherein the processors collectively generate a first amount of heat per unit time during the first section and a second amount of heat during the second section, the second amount of heat differing from the first amount of heat by less than 10%.

The present invention also provides a method of operating a consumer device, comprising: storing an application on a computer readable medium connected to a plurality of processors on a body of a multicore processor chip, the application having a first segment and a second segment; executing a first segment with the processors, the first segment having a first routine executable by the processors and a first power profile having a respective maximum clock speed for each processor; and executing a second segment with the processors, the second segment having a second routine executable by the processors and a second power profile having a respective maximum clock speed for each processor such that at least one processor has a maximum clock speed that changes from the first segment to the second segment, wherein the processors collectively generate a first amount of heat per unit of time during the first segment and collectively generate a second amount of heat during the second segment, the second amount of heat differing from the first amount of heat by less than 10%.

The present invention also provides a consumer device comprising: a first processor and a second processor; a computer readable medium connected to the processor; and an application on the computer readable medium, the application having: a first segment having a first routine executable by the first processor and the second processor, and a first power profile having a first maximum clock speed and a second maximum clock speed for the first processor and the second processor; and a second segment having a second routine executable by the first processor and the second processor, and a second power profile having a first maximum clock speed and a second maximum clock speed for the first processor and the second processor, the first maximum clock speed of the first power profile being different from the first maximum clock speed of the second power profile, and the second maximum clock speed of the first power profile being different from the second maximum clock speed of the second power profile.

Drawings

The invention is further described, by way of example, with reference to the accompanying drawings, in which:

FIG. 1 is a block diagram illustrating a network environment having a host computer system and a developer computer system connected to each other through a network in the form of the Internet according to an embodiment of the present invention;

FIG. 2 is a block diagram similar to FIG. 1 showing a download interface;

FIG. 3 is a block diagram of a developer computer system and a consumer device;

FIG. 4 is a block diagram showing the functionality of an application on a consumer device;

FIG. 5 is a block diagram illustrating other functionality of an application on a consumer device;

6A, 6B, and 6C are graphs showing power curves for three different processors;

FIGS. 7A, 7B, and 7C are diagrams illustrating three different power profiles;

FIGS. 8A, 8B and 8C are diagrams illustrating heat generated by the power profiles of FIGS. 7A, 7B and 7C, respectively;

FIG. 9 is a block diagram of a machine in the form of a computer system that forms a part of a network environment.

Detailed Description

FIG. 1 of the drawings illustrates a network environment 10 including a host computer system 12 and a developer computer system 14 connected to each other by a network in the form of the Internet 16, according to an embodiment of the invention. Most of the data and logic resides on the host computer system 12 and permits the developer computer system 14 to access certain components on the host computer system 12 through the internet 16 using only the browser application resident on the developer computer system 14. In another embodiment, all data and functionality may reside on the developer computer system 14, thus eliminating the need for the host computer system 12 — the developer computer system 14 effectively becomes the host computer system. However, preferably, some controls reside on the host computer system 12 and are not accessible to the developer at the developer computer system 14. Another embodiment may include some data and functionality being on host computer system 12, particularly such data and functionality that should be under the control of host computer system 12, while the remaining data and functionality may reside on developer computer system 14.

Host computer system 12 includes a structured application development system 18. The structured application development system 18 initially resides on a storage medium of the host computer system 12. The components of the structured application development system 18 are loaded into the memory of the host computer system 12 as needed. The components of the structured application development system 18 include selection data 52 that is left on memory and various logical components that are executable by a host computer processor of the host computer system 12 that is connected to the memory.

The structured application development system 18 includes a power profile database 20, a structured intent system 22, a development kit 24, and an application 26 being developed. The application 26 may not initially form part of the structured application development system 18. However, it is shown as part of the structured application development system 18 because it is built by other components of the structured application development system 18 in conjunction with the developer's selections made on the developer computer system 14.

The power profile database 20 has a first reference intent 28 and a second reference intent 30. For example, the first intent to reference 28 may be "graphics intensive," and the second intent to reference 30 may be "startup," or any other label designated to characterize the demand or load on the devices included in the running system of the program. The first reference intent 28 has a first power profile 32 associated therewith. The first power profile 32 has a first clock speed 34 for the first processor and a second clock speed 36 for the second processor. The first processor may be, for example, a Graphics Processing Unit (GPU) and the second processor may be a Central Processing Unit (CPU). If the first intent to reference 28 is a graphics intensive intent, the first clock speed for the GPU 34 will be set high and the second clock speed for the CPU 36 will be set low. The clock speed is selected as follows: the maximum amount of heat per unit time that the first processor and the second processor collectively generate on the multi-core processor chip will be limited while at the same time causing each processor to run at the optimal clock speed in the case of the first reference intent 28.

The second reference intent 30 has a second power profile 38 associated therewith. The second power profile 38 has a first clock speed 40 for the first processor and a second clock speed 42 for the second processor. For example, the second reference intent 30 is an activation intent. For startup purposes, the first clock speed 40 is set relatively low if the first processor is a GPU and the second clock speed 42 is set relatively high if the second processor is a CPU. If the first processor and the second processor are on the same multi-core processor chip, a first clock speed 40 and a second clock speed 42 are preemptively determined to keep the heat generated by the first processor and the second processor below the maximum heat per unit time. It should be noted that the first clock speed 34 of the first power profile 32 may be higher than the first clock speed 40 of the second power profile 38, and the second clock speed 36 of the first power profile 32 may be lower than the second clock speed 42 of the second power profile 36.

The power profile database 20 has only a first power profile 32 and a second power profile 38. However, it should be understood that the power profile database 20 may include more power profiles, such as four power profiles, each associated with a respective intent to reference.

Further, the first power profile 32 and the second power profile 38 include clock speeds for only the first processor and the second processor. Each power profile may also include a clock speed for a third processor, a fourth processor, and so on.

Structured intent system 22 includes a set of target intents 46, an intent selection interface 48, a power profile lookup (lookup)50, and selection data 52.

The set of target intents 46 includes a first target intent 56 and a second target intent 58. The first target intent 56 may be, for example, "graphics intensive" and the second target intent 58 may be "startup," and thus, similar to the first reference intent 28 and the second reference intent 30 in the power profile database 20.

A developer at the developer computer system 14 uses a browser resident on the developer computer system 14 to access the intent selection interface 48 over the internet 16. The intent selection interface 48 may be, for example, an interactive web page that is downloadable by a browser application from the host computer system 12 over the internet 16 onto the developer computer system 14 and viewable within a browser window on a display of the developer computer system 14. The intent selection interface 48 allows a developer to select segments of an application and select a target intent for the corresponding segment.

At 60, the developer selects a first segment 62 that will ultimately form part of the application. The structured intent system 22 displays the first target intent 58 as a first target intent 64 and the second target intent 58 as a second target intent 66 in the intent selection interface 48. The developer is then prompted to select either the first target intent 64 or the second target intent 66 for association with the first segment 62. Note that the developer is not allowed to select both the first target intent 64 and the second target intent 66. The first target intent 64 and the second target intent 66 may be presented within the intent selection interface 48, for example, in a drop down list that allows selection of only one of the first target intent 64 and the second target intent 66 and does not allow selection of the other target intent. At 70, the developer chooses to associate a second target intent (which is the same as the second target intent 58) with the first segment 62. Thus, the first segment 62 has a second target intent 66 associated therewith, and the second target intent 66 is a launch-intensive target intent. The arrow 72 indicates the association of the second target intent 66 with the first segment 62.

At 74, the developer makes a selection for a second segment 76 of the final application. The structured intent system 22 displays the first target intent 56 as a first target intent 78 and the second target intent 58 as a second target intent 80 such that the developer can select between the first target intent 78 and the second target intent 80. Again, the developer is only allowed to select one of the first target intent 78 and the second target intent 80, while excluding the other target intent. At 82, the developer chooses to associate a first target intent (which is the same as the first target intent 56) with the second segment 76. The arrow 84 indicates the association of the first target intent 78 with the second segment 76.

The power profile lookup 50 uses the second target intent 66 of the first segment 62 to determine a reference intent within the power profile database 20. In this example, the second target intent 66 matches the second reference intent 30 because they are both launch intensive intents. The power profile lookup 50 then extracts a second power profile 38 from the power profile database 20, which includes the first clock speed 40 and the second clock speed 42. The power profile lookup 50 then stores the second power profile 38 in the selection data 52 as a second power profile 86. The power profile lookup 50 stores the first segment 62 as the first segment 88. Power profile lookup 50 also associates a second power profile 86 with first segment 88. As will be understood by those skilled in the art of data structures, the first segment 88 and the first segment 62 may be identical segments of data. However, for purposes of illustration and ease of explanation, the first segment 62 and the first segment 88 are shown as distinct data segments.

Similarly, the power profile lookup 50 uses the first target intent 78 associated with the second segment 76 to lookup the reference intent in the power profile database 20. In this example, the first target intent 78 matches the first reference intent 28 because they are both graphically dense intents. The power profile lookup 50 extracts the first power profile 32 associated with the first intent to reference 28, which includes the first clock speed 34 and the second clock speed 36. Power profile lookup 50 then stores first power profile 32 within selection data 52 as first power profile 90. Power profile lookup 50 stores second segment 76 within selection data 52 as second segment 92. Power profile lookup 50 also associates first power profile 90 with second segment 92 in selection data 52.

The developer is not allowed to select clock speeds that are not represented in the respective power profiles 86 and 90. Therefore, it is not possible for developers to choose clock speeds that combine to result in too much heat being generated per unit time on a multi-core processor chip. However, developers are allowed to select target intents for respective segments in order to adjust the clock speeds of the individual processors without causing the processors to combine to generate too much heat per unit time.

The development kit 24 includes a toolset 96, a tool selection interface 94, application development logic 100, and power limiting logic 102.

The toolset 96 is the basic toolset required by developers to structure the components of segments of an application stored on the storage device of the host computer system 12. The toolset 96 is represented as tools 1 through 6. The developer at the developer computer system 14 downloads the tool selection interface 94 from the host computer system 12 for display on the developer computer system 14, similar to the manner in which the intent selection interface 48 is displayed. The tool selection interface 94 includes a first segment 104 and a second segment 106 corresponding to the first segment 88 and the second segment 92 in the selection data 52. The tools of the toolset 96 are also displayed within the tool selection interface 94. At 108, the developer selects a first tool (tool 3) for the first segment 104. The developer then proceeds to select other tools for the first segment 104. Thus, the tools for the first segment 104 may be configured by the developer in their selection and their order. The developer also selects a tool for the second segment 106 in a configurable manner. The first segment 104 and its tools and the second segment 106 and its tools represent to the developer how the application will function in terms of segments and the functionality of each segment of the application.

Application development logic 100 creates a first section 112 and a second section 114 in application 26. The first segment 112 corresponds to the first segments 62, 88, and 104. The second segment 114 corresponds to the second segments 76, 92, and 106. The application development logic 100 compiles the tools of the first segment 104 into a first routine 118 and inputs the first routine 118 within the first segment 112 of the application program 26. The application development logic 100 compiles the tools of the second segment 106 into a second routine 120 and enters the second routine 120 in the second segment 114.

The power limiting logic 102 retrieves the second power profile 86 corresponding to the first segment 88 from the selection data 52 and inputs the second power profile 86 as a second power profile 122 as part of the first segment 112 of the application 26. The power limiting logic 102 also retrieves the first power profile 90 corresponding to the second segment 92 in the selection data 52 and inputs the first power profile 90 in the second segment 114 as the first power profile 124. The second power profile 122 of the first segment 112 includes a first clock speed 40 for the first processor and a second clock speed 42 for the second processor. The first power profile 124 of the second segment 114 includes a first clock speed 34 for the first processor and a second clock speed 36 for the second processor. Thus, the first segment 112 and the second segment 114 each have a respective routine 118 and 120, and each have a respective clock speed for the first processor and the second processor, the clock speeds being selected to be intent specific and limited by the power limit logic 102 to limit the amount of heat the processors combine to generate per unit time in excess of a predetermined amount of heat.

As shown in FIG. 2, the structured application development system 18 also includes a download interface 98. The developer at developer computer system 14 retrieves download interface 98 from host computer system 12 and displays download interface 98 on a display of developer computer system 14. The developer uses the developer computer system 14 to interact with the download interface 98 to download the application 26 from the host computer system 12 onto the developer computer system 14. Application 26 then resides as application 130 on developer computer system 14.

FIG. 3 illustrates developer computer system 14 and consumer device 132. Consumer device 132 has storage medium 134 and multicore processor chip 136. Multicore processor chip 136 has a body 140 and first and second processors 142, 144 fabricated in and on body 140. Body 140 comprises a semiconductor material such as silicon, germanium, gallium arsenide, and the like, and may include other components and materials commonly known in the art of semiconductor packaging. The first processor 142 and the second processor 144 include transistors and other electronic components that are interconnected to form a logic device. The first processor 142 and the second processor 144 are connected to an external power source and have clocks that can be set at a preselected clock speed. The developer uses developer computer system 14 to create a copy of application program 130 and store the copy of the application program as application program 150 on storage medium 134. The consumer device 132 is then programmed with the application 150. In a batch manufacturing process, the application 130 may first be transferred to a programmer for programming a plurality of consumer devices for proportional distribution.

Fig. 4 and 5 illustrate how the application 150 executes on the consumer device 132. In fig. 4, the first segment 112 of the application 150 executes. The clock speed of the second power profile 122 is used to set the clock speed of the first processor 142 and the second processor 144. For example, the second power profile 122 includes a first clock speed 39GHz for the first processor 142 and a second clock speed 200GHz for the second processor 144. The first processor 142 and the second processor 144 execute the first routine 118. Segments of the first routine 118 that are executed by the first processor 142 are represented by a first routine 118A, and segments of the first routine 118 that are executed by the second processor 144 are represented by a first routine 118B. The first routines 118A and 118B may be partially executed at the same time or may have portions that are interleaved such that portions of the first routine 118A and the first routine 118B alternate with one another. The clock speeds of the first routine 118A and the first routine 118B executed by the first processor 142 and the second processor 144 are derived from the power profile database 20 in fig. 1, and the developer is prevented from selecting different clock speeds due to the logic provided to the developer and not provided to the developer.

Fig. 5 shows the execution of the second segment 114. The first power profile 124 is used to set the clock speed of the first processor 142 and the second processor 144. For example, the first processor 142 has a clock speed of 150GHz and the second processor 144 has a clock speed of 120 GHz. The second routine 120 is executed by a first processor 142 and a second processor 144. The components of the second routine 120 that are executed by the first processor 142 are represented by the second routine 120A and the components of the second routine 120 that are executed by the second processor 144 are represented as the second routine 120B.

Fig. 6A, 6B and 6C show that three different processors may have three different heat generation curves. In each graph, heat generated per unit time in watts is shown on the vertical axis and performance as a percentage of maximum clock speed is shown on the horizontal axis. The heat generation curve of the processor shown in fig. 6A initially increases slowly, followed by an increase in acceleration, and then an increase in deceleration. The heat generation curve of the processor shown in fig. 6B initially increases rapidly, followed by a gradual deceleration increase. The heat generation curve of the processor shown in fig. 6C increases linearly. When calculating the total heat generated by the three processors, the heat generation curves shown in fig. 6A, 6B, and 6C must be considered.

Fig. 7A, 7B, and 7C illustrate three different power profiles that may be stored. FIG. 7A illustrates a power profile in which a first one of the processors is given priority. The first processor is allowed to run at 100% of its maximum clock speed. The clock speeds of the second processor and the third processor are reduced to less than 100% of their maximum clock speeds. Fig. 7B shows a power profile in which priority is given to the third processor. The third processor is set to run at a clock speed equal to 100% of its maximum clock speed, while the clock speeds of the first and second processors are reduced to less than 100% of their maximum clock speeds. Fig. 7C shows a power profile in which performance is balanced. The clock speed of all three processors is reduced to less than 100% of their maximum clock speed.

Fig. 8A, 8B and 8C illustrate the heat generated by the power profiles in fig. 7A, 7B and 7C, respectively. Each processor generates heat according to its corresponding heat generation curve in fig. 6A, 6B, and 6C. The total heat generated per unit time by all three processors is the same in fig. 8A, 8B, and 8C. Although the total amount of heat generated per unit time is the same, minor variations are possible without departing from the scope and spirit of the invention. For example, the total heat generated per unit time by the first power profile may be less than 10% higher or less than 10% lower than the total heat generated per unit time following the second power profile. The third power profile may produce less than 10% more or less heat per unit time than the first power profile.

The consumer device 132 described herein may be a mixed reality system as described in U.S. patent application No.14/331,218, which is incorporated herein by reference.

Fig. 9 shows a diagrammatic representation of a machine in the exemplary form of a computer system 900, within which computer system 900 a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, may be executed. In alternative embodiments, the machine operates as a standalone device or may be connected (e.g., networked) to other machines. In a networked deployment, the machine may operate in the capacity of a server or a client machine in server-client network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The machine may be a Personal Computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a network router, switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while only a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

Exemplary computer system 900 includes a processor 930 (e.g., a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), or both), a main memory 932 (e.g., Read Only Memory (ROM), flash memory, Dynamic Random Access Memory (DRAM), such as synchronous DRAM (sdram) or Rambus DRAM (RDRAM)), etc.), and a static memory 934 (e.g., flash memory, static random access memory SRAM, etc.), which communicate with each other via a bus 936.

The computer system 900 may also include a video display 938, such as a Liquid Crystal Display (LCD) or a Cathode Ray Tube (CRT). Computer system 900 also includes an alphanumeric input device 940 (e.g., a keyboard), a cursor control device 942 (e.g., a mouse), a disk drive unit 944, a signal generation device 946 (e.g., a speaker), and a network interface device 948.

The disk drive unit 944 includes a machine-readable medium 950 on which is stored one or more sets of instructions 952 (e.g., software) embodying any one or more of the methodologies or functions described herein. The software may also reside, completely or at least partially, within the main memory 932 and/or within the processor 930 during execution thereof by the computer system 900, the memory 932 and the processor 930 also constituting machine-readable media. The software may further be transmitted or received over a network 954 via a network interface device 948.

While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive on the broad invention, and that this invention not be limited to the specific constructions and arrangements shown and described, since modifications may occur to those ordinarily skilled in the art.