Mathematical model and realization circuit of four-order complex value hyperchaotic system
阅读说明：本技术 一种四阶复值超混沌系统的数学模型及实现电路 (Mathematical model and realization circuit of four-order complex value hyperchaotic system ) 是由 刘娜 刘鹏 李宗翰 邓玮 方洁 栗三一 孙军伟 王国印 于 2020-05-29 设计创作，主要内容包括：本发明提出了一种四阶复值超混沌系统的数学模型及实现电路,所述数学模型由4个非线性微分方程组成,其中每个微分方程中均包含1个非线性乘积项；数学模型构建的复值超混沌系统具有三个正的李亚普诺夫指数,具有非常丰富的混沌动力学行为。所述实现电路由23个运算放大器、6个乘法器、54个电阻和7个电容构建七条通道电路,6个模拟乘法器用于实现复值系统中的四个二次乘积项；23个运算放大器、54个电阻和7个电容分别用于完成加、减、电压反转和积分功能。该实现电路实现简单,集成方便,为复值超混沌系统在信息科学和保密通信等领域中的应用奠定了基础。(The invention provides a mathematical model of a four-order complex value hyperchaotic system and a realization circuit, wherein the mathematical model consists of 4 nonlinear differential equations, wherein each differential equation comprises 1 nonlinear product term; the complex value hyperchaotic system constructed by the mathematical model has three positive Lyapunov indexes and very rich chaotic dynamic behaviors. The implementation circuit is characterized in that a seven-channel circuit is constructed by 23 operational amplifiers, 6 multipliers, 54 resistors and 7 capacitors, and the 6 analog multipliers are used for implementing four secondary product terms in a complex value system; 23 operational amplifiers, 54 resistors and 7 capacitors are used for completing the functions of adding, subtracting, voltage inverting and integrating respectively. The realization circuit is simple to realize and convenient to integrate, and lays a foundation for the application of the complex value hyper-chaotic system in the fields of information science, secret communication and the like.)
1. A four-order complex value hyperchaotic system is characterized in that the mathematical model of the system is as follows:
wherein x, y, z and w are system state complex variables, a, b, c, d, r and e are system parameters,
let x be x1+jx2，y＝x3+jx4，z＝x5+jx6，w＝x7Separating the real part and the imaginary part of the system state complex variable in the mathematical model to obtain a system model:
2. a circuit for realizing a four-order complex value hyperchaotic system is characterized by comprising a first channel circuit, a second channel circuit, a third channel circuit, a fourth channel circuit, a fifth channel circuit, a sixth channel circuit and a seventh channel circuit; the signal output by the output end of the first channel circuit is x1The signal output by the output end of the second channel circuit is x2The signal output by the output end of the third channel circuit is x3Fourth channel circuitThe output end of (1) outputs a signal of x4The signal output by the output end of the fifth channel circuit is x5The signal output by the output end of the sixth channel circuit is x6The output end of the seventh channel circuit outputs a signal x7(ii) a The input of the first channel circuit is composed of an output signal x1、x3And x5Formed compositely, the input of the second channel circuit is the output signal x2、x4And x6Formed by compounding, the input of the third channel circuit is the output signal x1、x3、x5And x7Compositely formed, the input of the fourth channel circuit is the output signal x2、x4、x6And x7Compositely formed, the input of the fifth channel circuit is the output signal x1、x3And x5Compositely formed, the input of the sixth channel circuit is the output signal x2、x4And x6Compositely formed, the input of the seventh channel circuit is the output signal x3、x5And x7And (4) compounding.
3. The four-order complex value hyperchaotic system realizing circuit according to claim 2, characterized in that said first channel circuit comprises a first subtracter, a first inverting adder and a first inverting integrator connected in series in turn; the first subtracter comprises an operational amplifier U11, a resistor R11, a resistor R12, a resistor R13 and a resistor R14, wherein one end of the resistor R11 is connected with a signal x1The other end of the resistor R11 is connected with the inverting input end of the operational amplifier U11 and the resistor R14 respectively, and one end of the resistor R12 is connected with the signal x3The other end of the resistor R12 and the resistor R13 are connected with the positive phase input end of the operational amplifier U11, the resistor R13 is grounded, and the resistor R14 is connected with the output end of the operational amplifier U11; the first inverting adder comprises an operational amplifier U12, a resistor R15, a resistor R16 and a resistor R17, one end of the resistor R15 is connected with the output end of the operational amplifier U11, the other end of the resistor R15 and the resistor R16 are both connected with the inverting input end of the operational amplifier U12, the resistor R17 is connected between the inverting input end and the output end of the operational amplifier U12, and the operational amplifier U12 is connected with the inverting input end of the operational amplifier U15The non-inverting input of amplifier U12 is connected to ground; the first inverting integrator comprises an operational amplifier U13, a resistor R18 and a capacitor C1, wherein one end of the resistor R18 is connected with the output end of the operational amplifier U12, the other end of the resistor R18 is respectively connected with the inverting input end of the operational amplifier U13 and the capacitor C1, the capacitor C1 is connected with the output end of the operational amplifier U13, and the non-inverting input end of the operational amplifier U13 is grounded; signal x3Sum signal x5Are connected to a first multiplier a1, a first multiplier a1 is connected to a resistor R16.
4. The four-order complex value hyperchaotic system realizing circuit according to claim 2, characterized in that said second channel circuit comprises a second subtracter, a second inverting adder and a second inverting integrator connected in series in turn; the second subtracter comprises an operational amplifier U21, a resistor R21, a resistor R22, a resistor R23 and a resistor R24, wherein one end of the resistor R21 is connected with a signal x2The other end of the resistor R21 is connected with the inverting input end of the operational amplifier U21 and the resistor R24 respectively, and one end of the resistor R22 is connected with the signal x4The other end of the resistor R22 and the resistor R23 are connected with the positive phase input end of the operational amplifier U21, the resistor R23 is grounded, and the resistor R24 is connected with the output end of the operational amplifier U21; the second inverting adder comprises an operational amplifier U22, a resistor R25, a resistor R26 and a resistor R27, one end of the resistor R25 is connected with the output end of the operational amplifier U21, the other end of the resistor R25 and the resistor R26 are both connected with the inverting input end of the operational amplifier U22, the resistor R27 is connected between the inverting input end and the output end of the operational amplifier U22, and the non-inverting input end of the operational amplifier U22 is grounded; the second inverting integrator comprises an operational amplifier U23, a resistor R28 and a capacitor C2, one end of the resistor R28 is connected with the output end of the operational amplifier U22, the other end of the resistor R28 is respectively connected with the inverting input end of the operational amplifier U23 and the capacitor C2, the capacitor C2 is connected with the output end of the operational amplifier U23, and the non-inverting input end of the operational amplifier U23 is grounded; signal x4Sum signal x6Are connected to a second multiplier a2, a second multiplier a2 is connected to a resistor R26.
5. The four-order complex value hyperchaotic system realizing circuit according to claim 2, characterized in that said third channel circuit comprises a third multiplier a3, a first inverter, a third inverting adder and a third inverting integrator connected in series in this order; the third multipliers A3 are respectively connected with the signal x1、x5Connecting; the first inverter comprises an operational amplifier U31, a resistor R31 and a resistor R33, one end of the resistor R31 is connected with the output end of the third multiplier A3, the other end of the resistor R31 is respectively connected with the inverting input end of the operational amplifier U31 and the resistor R33, the resistor R33 is connected with the output end of the operational amplifier U31, and the non-inverting input end of the operational amplifier U31 is grounded; the third inverting adder comprises an operational amplifier U32, a resistor R34, a resistor R36, a resistor R37, a resistor R38 and a resistor R39, one end of the resistor R34 is connected with the output end of the operational amplifier U31, the other end of the resistor R34, the other end of the resistor R36, the other end of the resistor R37 and the other end of the resistor R38 are connected with the inverting input end of the operational amplifier U32, the resistor R36 is connected with a second inverter, one end of the resistor R37 is connected with a signal x 371Connected to one end of resistor R387A resistor R39 is connected between the inverting input end and the output end of the operational amplifier U32, and the non-inverting input end of the operational amplifier U32 is grounded; the third inverting integrator comprises an operational amplifier U33, a resistor R3X and a capacitor C3, one end of the resistor R3X is connected with the output end of the operational amplifier U32, the other end of the resistor R3X is respectively connected with the inverting input end of the operational amplifier U33 and the capacitor C3, the capacitor C3 is connected with the output end of the operational amplifier U33, and the non-inverting input end of the operational amplifier U33 is grounded; the third channel circuit also comprises a second inverter, the second inverter comprises an operational amplifier U34, a resistor R32 and a resistor R35, one end of the resistor R32 is connected with the signal x3The other end of the resistor R32 is connected to the inverting input terminal of the operational amplifier U34 and the resistor R35, the resistor R35 is connected to the output terminal of the operational amplifier U34, the output terminal of the operational amplifier U34 is connected to the resistor R36, and the non-inverting input terminal of the operational amplifier U34 is grounded.
6. The implementation circuit of the fourth-order complex value hyperchaotic system according to claim 2, characterized in that the fourth channel circuit comprises a fourth multiplier a4, a third inverter, a fourth inverting adder and a fourth inverting integrator connected in series in this order; the fourth multipliers A4 are respectively connected with the signal x2、x6Connecting; the third inverter comprises an operational amplifier U41, a resistor R41 and a resistor R42, one end of the resistor R41 is connected with the output end of the fourth multiplier A4, the other end of the resistor R41 is respectively connected with the inverting input end of the operational amplifier U41 and the resistor R42, the resistor R42 is connected with the output end of the operational amplifier U41, and the non-inverting input end of the operational amplifier U41 is grounded; the fourth inverting adder comprises an operational amplifier U42, a resistor R43, a resistor R46, a resistor R47, a resistor R48 and a resistor R49, one end of the resistor R43 is connected with the output end of the operational amplifier U41, the other end of the resistor R43, the other end of the resistor R46, the other end of the resistor R47 and the other end of the resistor R48 are connected with the inverting input end of the operational amplifier U42, the resistor R46 is connected with a fourth inverter, one end of the resistor R47 is connected with a signal x 472Connected to one end of resistor R487A resistor R49 is connected between the inverting input end and the output end of the operational amplifier U42, and the non-inverting input end of the operational amplifier U42 is grounded; the fourth inverting integrator comprises an operational amplifier U43, a resistor R4X and a capacitor C4, one end of the resistor R4X is connected with the output end of the operational amplifier U42, the other end of the resistor R4X is respectively connected with the inverting input end of the operational amplifier U43 and the capacitor C4, the capacitor C4 is connected with the output end of the operational amplifier U43, and the non-inverting input end of the operational amplifier U43 is grounded; the fourth channel circuit further comprises a fourth inverter, the fourth inverter comprises an operational amplifier U44, a resistor R44 and a resistor R45, one end of the resistor R44 is connected with the signal x4The other end of the resistor R44 is connected to the inverting input terminal of the operational amplifier U44 and the resistor R45, the resistor R45 is connected to the output terminal of the operational amplifier U44, the output terminal of the operational amplifier U44 is connected to the resistor R46, and the non-inverting input terminal of the operational amplifier U44 is grounded.
7. The four-order complex value hyperchaotic system realizing circuit according to claim 2, characterized in that said fifth channel circuit comprises a fifth inverter, a fifth inverting adder and a fifth inverting integrator connected in series in this order; the fifth inverter comprises an operational amplifier U51, a resistor R51, a resistor R52, one end of the resistor R51 and a signal x5The other end of the resistor R51 is respectively connected with the inverting input end of the operational amplifier U51 and the resistor R52, the resistor R52 is connected with the output end of the operational amplifier U51, and the non-inverting input end of the operational amplifier U51 is grounded; the fifth inverting adder comprises an operational amplifier U52, a resistor R53, a resistor R54 and a resistor R55, one end of the resistor R53 is connected with the output end of the operational amplifier U51, the other end of the resistor R53 and the resistor R54 are both connected with the inverting input end of the operational amplifier U52, the resistor R55 is connected between the inverting input end and the output end of the operational amplifier U52, and the non-inverting input end of the operational amplifier U52 is grounded; the fifth inverting integrator comprises an operational amplifier U53, a resistor R56 and a capacitor C5, one end of the resistor R56 is connected with the output end of the operational amplifier U52, the other end of the resistor R56 is respectively connected with the inverting input end of the operational amplifier U53 and the capacitor C5, the capacitor C5 is connected with the output end of the operational amplifier U53, and the non-inverting input end of the operational amplifier U53 is grounded; signal x3Sum signal x1Are connected to a fifth multiplier a2, a fifth multiplier a5 is connected to a resistor R54.
8. The four-order complex value hyperchaotic system realizing circuit according to claim 2, characterized in that said sixth channel circuit comprises a sixth inverter, a sixth inverting adder and a sixth inverting integrator connected in series in this order; the sixth inverter comprises an operational amplifier U61, a resistor R61 and a resistor R62, wherein one end of the resistor R61 is connected with the signal x6The other end of the resistor R61 is respectively connected with the inverting input end of the operational amplifier U61 and the resistor R62, the resistor R62 is connected with the output end of the operational amplifier U61, and the non-inverting input end of the operational amplifier U61 is grounded; the sixth inverting adder includes an operational amplifier U62, a resistor R63, and a resistorThe circuit comprises a resistor R64 and a resistor R65, wherein one end of the resistor R63 is connected with the output end of an operational amplifier U61, the other end of the resistor R63 and a resistor R64 are both connected with the inverting input end of an operational amplifier U62, a resistor R65 is connected between the inverting input end and the output end of the operational amplifier U62, and the non-inverting input end of an operational amplifier U62 is grounded; the sixth inverting integrator comprises an operational amplifier U63, a resistor R66 and a capacitor C6, one end of the resistor R66 is connected with the output end of the operational amplifier U62, the other end of the resistor R66 is respectively connected with the inverting input end of the operational amplifier U63 and the capacitor C6, the capacitor C6 is connected with the output end of the operational amplifier U63, and the non-inverting input end of the operational amplifier U63 is grounded; signal x2Sum signal x4Are connected to a sixth multiplier a6, a sixth multiplier a6 is connected to a resistor R64.
9. The four-order complex value hyperchaotic system realizing circuit according to claim 3, characterized in that said seventh channel circuit comprises a seventh inverter, a seventh inverting adder and a seventh inverting integrator connected in series in this order; the seventh inverter comprises an operational amplifier U71, a resistor R71 and a resistor R72, one end of the resistor R71 is connected with the output end of the first multiplier A1, the other end of the resistor R71 is respectively connected with the inverting input end of the operational amplifier U71 and the resistor R72, the resistor R72 is connected with the output end of the operational amplifier U71, and the non-inverting input end of the operational amplifier U71 is grounded; the seventh inverting adder comprises an operational amplifier U72, a resistor R73, a resistor R74 and a resistor R75, wherein one end of the resistor R73 is connected with the output end of the operational amplifier U71, and one end of the resistor R74 is connected with the signal x7The other end of the resistor R73 and the other end of the resistor R74 are both connected with the inverting input end of the operational amplifier U72, a resistor R75 is connected between the inverting input end and the output end of the operational amplifier U72, and the non-inverting input end of the operational amplifier U72 is grounded; the seventh inverting integrator comprises an operational amplifier U73, a resistor R76 and a capacitor C7, one end of the resistor R76 is connected with the output end of the operational amplifier U72, the other end of the resistor R76 is respectively connected with the inverting input end of the operational amplifier U73 and the capacitor C7, and the capacitor C7 is connected with the output end of the operational amplifier U73Connected to ground, the non-inverting input of operational amplifier U73.
Technical Field
The invention relates to the technical field of secret communication, in particular to a mathematical model of a four-order complex value hyper-chaotic system and a realization circuit.
Background
Chaos refers to an uncertain or unpredictable random phenomenon of a certain nonlinear system under a certain condition, and the phenomenon represents organic unification of certainty and uncertainty, orderliness and orderless or regularity and irregularity. The long-term unpredictability, ergodicity and extreme sensitivity to initial conditions of chaos suggest that chaos will find wide application in cryptography.
The complex chaotic system is a popularization and extension of a research domain of the chaotic system from a real number domain to a complex number domain, has a very deep physical research background, and plays an important role in the field of physics. A complex variable exists in the chaotic system, the complex variable has double variable numbers after the separation of a virtual real part, and a generated chaotic signal has more unpredictability and randomness. Since the sequence it generates is a secure pseudo-random sequence, it cannot be predicted successfully. If the invader knows the calculation method for forming the pseudo-random sequence, the next random number cannot be successfully calculated, so that the attacker is more difficult to intercept valuable information from the information transmission process. Therefore, its value is immeasurable in the field of secure communications.
Compared with a chaotic system, the hyperchaotic system has two or more positive Lyapunov indexes, the lowest dimension of the system is four-dimensional, the dynamic characteristic of the hyperchaotic system is more complex, and the change of the system orbit is more complex and disordered. Due to the good randomness and initial value sensitivity of the hyper-chaotic system, the generated pseudo-random sequence can enhance the encryption quality to a certain extent, increase the difficulty of deciphering, and embody the unique superiority when applied in the fields of cryptography, information security and the like. In addition, compared with a low-dimensional chaotic system, the hyper-chaotic system has a plurality of positive Lyapunov indexes in an output sequence, and the phase space of the hyper-chaotic system is more difficult to reconstruct. When a dynamic model of the hyper-chaotic system is known, the security of secret communication realized based on hyper-chaotic synchronization is determined by the extreme sensitivity of the hyper-chaotic system to system parameters and initial values, and the higher the sensitivity is, the stronger the anti-deciphering capability of the hyper-chaotic system is. Therefore, the hyperchaotic system is effectively controlled to realize multi-channel and multi-mode output, so that the key generation and encryption algorithm has good operability.
The chaos theory is improved day by day, which provides guarantee for the application research of complex value hyperchaotic and also provides higher requirement for the design of novel complex value hyperchaotic system. By designing a novel complex value hyperchaotic system, the complex value hyperchaotic system can be utilized and the hyperchaotic system can be restrained in the future only by deeply understanding the principle and theoretically researching the application of the complex value hyperchaotic system. Therefore, designing a new complex value hyper-chaotic system and analyzing the dynamic behavior thereof can develop a new research foundation and development prospect for the application of the chaotic system in the fields of secret communication and the like.
Disclosure of Invention
The invention provides a mathematical model of a four-order complex value hyperchaotic system and a realization circuit, which have three positive Lyapunov indexes, can generate abundant dynamic behaviors, and are simple to realize and easy to integrate.
The technical scheme of the invention is realized as follows:
a mathematical model of a four-order complex value hyperchaotic system is as follows:
wherein x, y, z and w are system state complex variables, a, b, c, d, r and e are system parameters,
let x be x1+jx2，y＝x3+jx4，z＝x5+jx6，w＝x7Separating the real part and the imaginary part of the system state complex variable in the mathematical model to obtain a system model:
a circuit for realizing a four-order complex value hyperchaotic system comprises a first channel circuit, a second channel circuit, a third channel circuit, a fourth channel circuit, a fifth channel circuit, a sixth channel circuit and a seventh channel circuit; the signal output by the output end of the first channel circuit is x1The signal output by the output end of the second channel circuit is x2The signal output by the output end of the third channel circuit is x3The signal output by the output end of the fourth channel circuit is x4The signal output by the output end of the fifth channel circuit is x5The signal output by the output end of the sixth channel circuit is x6The output end of the seventh channel circuit outputs a signal x7(ii) a The input of the first channel circuit is composed of an output signal x1、x3And x5Formed compositely, the input of the second channel circuit is the output signal x2、x4And x6Formed by compounding, the input of the third channel circuit is the output signal x1、x3、x5And x7Compositely formed, the input of the fourth channel circuit is the output signal x2、x4、x6And x7Compositely formed, the input of the fifth channel circuit is the output signal x1、x3And x5Compositely formed, the input of the sixth channel circuit is the output signal x2、x4And x6Compositely formed, the input of the seventh channel circuit is the output signal x3、x5And x7And (4) compounding.
The first channel circuit comprises a first subtracter, a first inverse adder and a first inverse integrator which are sequentially connected in series; the first subtracter comprises an operational amplifier U11, a resistor R11, a resistor R12, a resistor R13 and a resistor R14, wherein one end of the resistor R11 is connected with a signal x1The other end of the resistor R11 is connected with the inverting input end of the operational amplifier U11 and the resistor R14 respectively, and one end of the resistor R12 is connected with the signal x3The other end of the resistor R12 and the resistor R13 are connected with the positive phase input end of the operational amplifier U11, the resistor R13 is grounded, and the resistor R14 is connected with the output end of the operational amplifier U11; the first inverting adder comprises an operational amplifier U12, a resistor R15, a resistor R16 and a resistor R17, one end of the resistor R15 is connected with the output end of the operational amplifier U11, the other end of the resistor R15 and the resistor R16 are both connected with the inverting input end of the operational amplifier U12, the resistor R17 is connected between the inverting input end and the output end of the operational amplifier U12, and the non-inverting input end of the operational amplifier U12 is grounded; the first inverting integrator comprises an operational amplifier U13, a resistor R18 and a capacitor C1, wherein one end of the resistor R18 is connected with the output end of the operational amplifier U12, the other end of the resistor R18 is respectively connected with the inverting input end of the operational amplifier U13 and the capacitor C1, the capacitor C1 is connected with the output end of the operational amplifier U13, and the non-inverting input end of the operational amplifier U13 is grounded; signal x3Sum signal x5Are connected to a first multiplier a1, a first multiplier a1 is connected to a resistor R16.
The second channel circuit comprises a second subtracter, a second inverse adder and a second inverse integrator which are sequentially connected in series; the second subtracter comprises an operational amplifier U21, a resistor R21, a resistor R22, a resistor R23 and a resistor R24, wherein one end of the resistor R21 is connected with a signal x2The other end of the resistor R21 is connected with the inverting input end of the operational amplifier U21 and the resistor R24 respectively, and one end of the resistor R22 is connected with the signal x4The other end of the resistor R22 and the resistor R23 are connected with the positive phase input end of the operational amplifier U21, the resistor R23 is grounded, and the resistor R24 is connected with the output end of the operational amplifier U21; the second inverting adder comprises an operational amplifier U22, a resistor R25, a resistor R26 and a resistor R27, one end of the resistor R25 is connected with the output end of the operational amplifier U21, the other end of the resistor R25 and the resistor R26 are both connected with the inverting input end of the operational amplifier U22, the resistor R27 is connected between the inverting input end and the output end of the operational amplifier U22,the non-inverting input terminal of the operational amplifier U22 is grounded; the second inverting integrator comprises an operational amplifier U23, a resistor R28 and a capacitor C2, one end of the resistor R28 is connected with the output end of the operational amplifier U22, the other end of the resistor R28 is respectively connected with the inverting input end of the operational amplifier U23 and the capacitor C2, the capacitor C2 is connected with the output end of the operational amplifier U23, and the non-inverting input end of the operational amplifier U23 is grounded; signal x4Sum signal x6Are connected to a second multiplier a2, a second multiplier a2 is connected to a resistor R26.
The third channel circuit comprises a third multiplier A3, a first inverter, a third inverting adder and a third inverting integrator which are sequentially connected in series; the third multipliers A3 are respectively connected with the signal x1、x5Connecting; the first inverter comprises an operational amplifier U31, a resistor R31 and a resistor R33, one end of the resistor R31 is connected with the output end of the third multiplier A3, the other end of the resistor R31 is respectively connected with the inverting input end of the operational amplifier U31 and the resistor R33, the resistor R33 is connected with the output end of the operational amplifier U31, and the non-inverting input end of the operational amplifier U31 is grounded; the third inverting adder comprises an operational amplifier U32, a resistor R34, a resistor R36, a resistor R37, a resistor R38 and a resistor R39, one end of the resistor R34 is connected with the output end of the operational amplifier U31, the other end of the resistor R34, the other end of the resistor R36, the other end of the resistor R37 and the other end of the resistor R38 are connected with the inverting input end of the operational amplifier U32, the resistor R36 is connected with a second inverter, one end of the resistor R37 is connected with a signal x 371Connected to one end of resistor R387A resistor R39 is connected between the inverting input end and the output end of the operational amplifier U32, and the non-inverting input end of the operational amplifier U32 is grounded; the third inverting integrator comprises an operational amplifier U33, a resistor R3X and a capacitor C3, one end of the resistor R3X is connected with the output end of the operational amplifier U32, the other end of the resistor R3X is respectively connected with the inverting input end of the operational amplifier U33 and the capacitor C3, the capacitor C3 is connected with the output end of the operational amplifier U33, and the non-inverting input end of the operational amplifier U33 is grounded; the third channel circuit further comprises a second inverter comprising an operational amplifierA U34, a resistor R32 and a resistor R35, one end of the resistor R32 and the signal x3The other end of the resistor R32 is connected to the inverting input terminal of the operational amplifier U34 and the resistor R35, the resistor R35 is connected to the output terminal of the operational amplifier U34, the output terminal of the operational amplifier U34 is connected to the resistor R36, and the non-inverting input terminal of the operational amplifier U34 is grounded.
The fourth channel circuit comprises a fourth multiplier A4, a third inverter, a fourth inverting adder and a fourth inverting integrator which are sequentially connected in series; the fourth multipliers A4 are respectively connected with the signal x2、x6Connecting; the third inverter comprises an operational amplifier U41, a resistor R41 and a resistor R42, one end of the resistor R41 is connected with the output end of the fourth multiplier A4, the other end of the resistor R41 is respectively connected with the inverting input end of the operational amplifier U41 and the resistor R42, the resistor R42 is connected with the output end of the operational amplifier U41, and the non-inverting input end of the operational amplifier U41 is grounded; the fourth inverting adder comprises an operational amplifier U42, a resistor R43, a resistor R46, a resistor R47, a resistor R48 and a resistor R49, one end of the resistor R43 is connected with the output end of the operational amplifier U41, the other end of the resistor R43, the other end of the resistor R46, the other end of the resistor R47 and the other end of the resistor R48 are connected with the inverting input end of the operational amplifier U42, the resistor R46 is connected with a fourth inverter, one end of the resistor R47 is connected with a signal x 472Connected to one end of resistor R487A resistor R49 is connected between the inverting input end and the output end of the operational amplifier U42, and the non-inverting input end of the operational amplifier U42 is grounded; the fourth inverting integrator comprises an operational amplifier U43, a resistor R4X and a capacitor C4, one end of the resistor R4X is connected with the output end of the operational amplifier U42, the other end of the resistor R4X is respectively connected with the inverting input end of the operational amplifier U43 and the capacitor C4, the capacitor C4 is connected with the output end of the operational amplifier U43, and the non-inverting input end of the operational amplifier U43 is grounded; the fourth channel circuit further comprises a fourth inverter, the fourth inverter comprises an operational amplifier U44, a resistor R44 and a resistor R45, one end of the resistor R44 is connected with the signal x4The other end of the resistor R44 is connected with the inverting input end of the operational amplifier U44 and the resistorThe resistor R45 is connected, the resistor R45 is connected with the output end of the operational amplifier U44, the output end of the operational amplifier U44 is connected with the resistor R46, and the non-inverting input end of the operational amplifier U44 is grounded.
The fifth channel circuit comprises a fifth inverter, a fifth inverting adder and a fifth inverting integrator which are sequentially connected in series; the fifth inverter comprises an operational amplifier U51, a resistor R51, a resistor R52, one end of the resistor R51 and a signal x5The other end of the resistor R51 is respectively connected with the inverting input end of the operational amplifier U51 and the resistor R52, the resistor R52 is connected with the output end of the operational amplifier U51, and the non-inverting input end of the operational amplifier U51 is grounded; the fifth inverting adder comprises an operational amplifier U52, a resistor R53, a resistor R54 and a resistor R55, one end of the resistor R53 is connected with the output end of the operational amplifier U51, the other end of the resistor R53 and the resistor R54 are both connected with the inverting input end of the operational amplifier U52, the resistor R55 is connected between the inverting input end and the output end of the operational amplifier U52, and the non-inverting input end of the operational amplifier U52 is grounded; the fifth inverting integrator comprises an operational amplifier U53, a resistor R56 and a capacitor C5, one end of the resistor R56 is connected with the output end of the operational amplifier U52, the other end of the resistor R56 is respectively connected with the inverting input end of the operational amplifier U53 and the capacitor C5, the capacitor C5 is connected with the output end of the operational amplifier U53, and the non-inverting input end of the operational amplifier U53 is grounded; signal x3Sum signal x1Are connected to a fifth multiplier a2, a fifth multiplier a5 is connected to a resistor R54.
The sixth channel circuit comprises a sixth inverter, a sixth inverting adder and a sixth inverting integrator which are sequentially connected in series; the sixth inverter comprises an operational amplifier U61, a resistor R61 and a resistor R62, wherein one end of the resistor R61 is connected with the signal x6The other end of the resistor R61 is respectively connected with the inverting input end of the operational amplifier U61 and the resistor R62, the resistor R62 is connected with the output end of the operational amplifier U61, and the non-inverting input end of the operational amplifier U61 is grounded; the sixth inverting adder comprises an operational amplifier U62, a resistor R63, a resistor R64 and a resistor R65, wherein one end of the resistor R63 and the output end of the operational amplifier U61The other end of the resistor R63 and the resistor R64 are connected with the inverting input end of the operational amplifier U62, a resistor R65 is connected between the inverting input end and the output end of the operational amplifier U62, and the non-inverting input end of the operational amplifier U62 is grounded; the sixth inverting integrator comprises an operational amplifier U63, a resistor R66 and a capacitor C6, one end of the resistor R66 is connected with the output end of the operational amplifier U62, the other end of the resistor R66 is respectively connected with the inverting input end of the operational amplifier U63 and the capacitor C6, the capacitor C6 is connected with the output end of the operational amplifier U63, and the non-inverting input end of the operational amplifier U63 is grounded; signal x2Sum signal x4Are connected to a sixth multiplier a6, a sixth multiplier a6 is connected to a resistor R64.
The seventh channel circuit comprises a seventh inverter, a seventh inverting adder and a seventh inverting integrator which are sequentially connected in series; the seventh inverter comprises an operational amplifier U71, a resistor R71 and a resistor R72, one end of the resistor R71 is connected with the output end of the first multiplier A1, the other end of the resistor R71 is respectively connected with the inverting input end of the operational amplifier U71 and the resistor R72, the resistor R72 is connected with the output end of the operational amplifier U71, and the non-inverting input end of the operational amplifier U71 is grounded; the seventh inverting adder comprises an operational amplifier U72, a resistor R73, a resistor R74 and a resistor R75, wherein one end of the resistor R73 is connected with the output end of the operational amplifier U71, and one end of the resistor R74 is connected with the signal x7The other end of the resistor R73 and the other end of the resistor R74 are both connected with the inverting input end of the operational amplifier U72, a resistor R75 is connected between the inverting input end and the output end of the operational amplifier U72, and the non-inverting input end of the operational amplifier U72 is grounded; the seventh inverting integrator comprises an operational amplifier U73, a resistor R76 and a capacitor C7, wherein one end of the resistor R76 is connected with the output end of the operational amplifier U72, the other end of the resistor R76 is respectively connected with the inverting input end of the operational amplifier U73 and the capacitor C7, the capacitor C7 is connected with the output end of the operational amplifier U73, and the non-inverting input end of the operational amplifier U73 is grounded.
Compared with the prior chaotic technology, the technical scheme has the following beneficial effects:
(1) the invention has three positive Lyapunov indexes, is a complex value hyperchaotic system and has rich complex dynamic behaviors;
(2) the circuit of the invention has simple structure and convenient integration, and has great promotion effect on the development of the chaotic system in the fields of secret communication, information processing and the like.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a circuit diagram of the present invention;
FIG. 2 is a circuit diagram of each channel of the present invention, (a) is a circuit diagram of a first channel, (b) is a circuit diagram of a second channel, (c) is a circuit diagram of a third channel, (d) is a circuit diagram of a fourth channel, (e) is a circuit diagram of a fifth channel, (f) is a circuit diagram of a sixth channel, and (g) is a circuit diagram of a seventh channel;
FIG. 3 is a Lyapunov index diagram of the present invention;
FIG. 4 is the computer simulation result of the phase diagram of the complex hyperchaotic attractor of the present invention in x1-x3-x7 three-dimensional space;
FIG. 5 is the computer simulation result of the phase diagram of the complex hyperchaotic attractor of the present invention in x2-x5-x7 three-dimensional space;
FIG. 6 is the computer simulation result of the phase diagram of the complex hyperchaotic attractor of the present invention in x1-x3-x4 three-dimensional space;
FIG. 7 is the computer simulation result of the phase diagram of the complex hyperchaotic attractor of the present invention in x5-x6-x7 three-dimensional space;
FIG. 8 is a computer simulation of a phase diagram of a complex hyperchaotic attractor of the present invention in the x3-x4 plane;
FIG. 9 is a circuit simulation result of a phase diagram of the complex hyperchaotic attractor of the present invention in the x3-x4 plane;
FIG. 10 is a computer simulation of a phase diagram of a complex hyperchaotic attractor of the present invention in the x1-x3 plane;
FIG. 11 is a circuit simulation result of a phase diagram of the complex hyperchaotic attractor of the present invention in the x1-x3 plane;
FIG. 12 is a computer simulation of a phase diagram of a complex hyperchaotic attractor of the present invention in the x3-x6 plane;
FIG. 13 is a circuit simulation result of a phase diagram of the complex hyperchaotic attractor of the present invention in the x3-x6 plane;
FIG. 14 is a computer simulation of a phase diagram of a complex hyperchaotic attractor of the present invention in the x2-x7 plane;
FIG. 15 is a circuit simulation result of a phase diagram of the complex hyperchaotic attractor of the present invention in the x2-x7 plane.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive effort based on the embodiments of the present invention, are within the scope of the present invention.
The invention provides a mathematical model of a four-order complex value hyperchaotic system, which comprises the following steps:
wherein x, y, z and w are system state complex variables, and a, b, c, d, r and e are system parameters;both represent the derivative of the system state complex variable with respect to time.
Let x be x1+jx2，y＝x3+jx4，z＝x5+jx6，
when the parameter a is 15, b is 1.5, c is 5, d is 43, r is 0.5, and e is 3.5, the system has hyperchaotic behavior.
The Lyapunov indexes of the mathematical model obtained by simulating the system model by using the Wolf method are respectively as follows: 3.945771, 0.001854, 0.000554, -1.289807, -4.019445, -9.318841, -19.702222, i.e., having three positive Lyapunov indices, as shown in FIG. 3.
Considering that the state variable is in a large dynamic variation range, and exceeds a reasonable voltage supply range, the problem can be solved through variable conversion. Order: x is the number of1＝x1/50，x2＝x2/50，x3＝x3/50，x4＝x4/50，x5＝x5/50，x6＝x6/50，x7＝x7/50. Under this scale transformation, the system model can be converted into the formula:
the state variables in the converted system have similar dynamic variation ranges and do not exceed typical voltage supply limits, and are easily implemented in a circuit. The circuitry in the converted system is shown in fig. 1.
As shown in fig. 1, an implementation circuit of a four-order complex value hyper-chaotic system includes a first channel circuit, a second channel circuit, a third channel circuit, a fourth channel circuit, a fifth channel circuit, a sixth channel circuit, and a seventh channel circuit; the signal output by the output end of the first channel circuit is x1The signal output by the output end of the second channel circuit is x2The signal output by the output end of the third channel circuit is x3A signal output from an output terminal of the fourth channel circuitIs x4The signal output by the output end of the fifth channel circuit is x5The signal output by the output end of the sixth channel circuit is x6The output end of the seventh channel circuit outputs a signal x7(ii) a The input of the first channel circuit is composed of an output signal x1、x3And x5Formed compositely, the input of the second channel circuit is the output signal x2、x4And x6Formed by compounding, the input of the third channel circuit is the output signal x1、x3、x5And x7Compositely formed, the input of the fourth channel circuit is the output signal x2、x4、x6And x7Compositely formed, the input of the fifth channel circuit is the output signal x1、x3And x5Compositely formed, the input of the sixth channel circuit is the output signal x2、x4And x6Compositely formed, the input of the seventh channel circuit is the output signal x3、x5And x7And (4) compounding.
As shown in fig. 2(a), the first channel circuit includes a first subtractor, a first inverting adder, and a first inverting integrator, which are connected in series in this order; the first subtracter comprises an operational amplifier U11, a resistor R11, a resistor R12, a resistor R13 and a resistor R14, wherein one end of the resistor R11 is connected with a signal x1The other end of the resistor R11 is connected with the inverting input end of the operational amplifier U11 and the resistor R14 respectively, and one end of the resistor R12 is connected with the signal x3The other end of the resistor R12 and the resistor R13 are connected with the positive phase input end of the operational amplifier U11, the resistor R13 is grounded, and the resistor R14 is connected with the output end of the operational amplifier U11; the first inverting adder comprises an operational amplifier U12, a resistor R15, a resistor R16 and a resistor R17, one end of the resistor R15 is connected with the output end of the operational amplifier U11, the other end of the resistor R15 and the resistor R16 are both connected with the inverting input end of the operational amplifier U12, the resistor R17 is connected between the inverting input end and the output end of the operational amplifier U12, and the non-inverting input end of the operational amplifier U12 is grounded; the first inverting integrator comprises an operational amplifier U13, a resistor R18 and a capacitor C1, wherein one end of the resistor R18 and operational amplificationThe output end of the device U12 is connected, the other end of the resistor R18 is respectively connected with the inverting input end of the operational amplifier U13 and the capacitor C1, the capacitor C1 is connected with the output end of the operational amplifier U13, and the non-inverting input end of the operational amplifier U13 is grounded; signal x3Sum signal x5Are connected to a first multiplier a1, a first multiplier a1 is connected to a resistor R16. The signal x output by the output end of the operational amplifier U131Respectively connected to one end of the resistor R11, one end of the third multiplier A3, one end of the resistor R37, and the fifth multiplier a 5.
As shown in fig. 2(b), the second channel circuit includes a second subtractor, a second inverting adder, and a second inverting integrator that are connected in series in this order; the second subtracter comprises an operational amplifier U21, a resistor R21, a resistor R22, a resistor R23 and a resistor R24, wherein one end of the resistor R21 is connected with a signal x2The other end of the resistor R21 is connected with the inverting input end of the operational amplifier U21 and the resistor R24 respectively, and one end of the resistor R22 is connected with the signal x4The other end of the resistor R22 and the resistor R23 are connected with the positive phase input end of the operational amplifier U21, the resistor R23 is grounded, and the resistor R24 is connected with the output end of the operational amplifier U21; the second inverting adder comprises an operational amplifier U22, a resistor R25, a resistor R26 and a resistor R27, one end of the resistor R25 is connected with the output end of the operational amplifier U21, the other end of the resistor R25 and the resistor R26 are both connected with the inverting input end of the operational amplifier U22, the resistor R27 is connected between the inverting input end and the output end of the operational amplifier U22, and the non-inverting input end of the operational amplifier U22 is grounded; the second inverting integrator comprises an operational amplifier U23, a resistor R28 and a capacitor C2, one end of the resistor R28 is connected with the output end of the operational amplifier U22, the other end of the resistor R28 is respectively connected with the inverting input end of the operational amplifier U23 and the capacitor C2, the capacitor C2 is connected with the output end of the operational amplifier U23, and the non-inverting input end of the operational amplifier U23 is grounded; signal x4Sum signal x6Are connected to a second multiplier a2, a second multiplier a2 is connected to a resistor R26. The signal x output by the output end of the operational amplifier U232Respectively connected with one end of the resistor R21, the fourth multiplier A4 and the resistor R47One end is connected to a sixth multiplier a 6.
As shown in fig. 2(c), the third channel circuit includes a third multiplier a3, a first inverter, a third inverting adder, and a third inverting integrator, which are connected in series in this order; the third multipliers A3 are respectively connected with the signal x1、x5Connecting; the first inverter comprises an operational amplifier U31, a resistor R31 and a resistor R33, one end of the resistor R31 is connected with the output end of the third multiplier A3, the other end of the resistor R31 is respectively connected with the inverting input end of the operational amplifier U31 and the resistor R33, the resistor R33 is connected with the output end of the operational amplifier U31, and the non-inverting input end of the operational amplifier U31 is grounded; the third inverting adder comprises an operational amplifier U32, a resistor R34, a resistor R36, a resistor R37, a resistor R38 and a resistor R39, one end of the resistor R34 is connected with the output end of the operational amplifier U31, the other end of the resistor R34, the other end of the resistor R36, the other end of the resistor R37 and the other end of the resistor R38 are connected with the inverting input end of the operational amplifier U32, the resistor R36 is connected with a second inverter, one end of the resistor R37 is connected with a signal x 371Connected to one end of resistor R387A resistor R39 is connected between the inverting input end and the output end of the operational amplifier U32, and the non-inverting input end of the operational amplifier U32 is grounded; the third inverting integrator comprises an operational amplifier U33, a resistor R3X and a capacitor C3, one end of the resistor R3X is connected with the output end of the operational amplifier U32, the other end of the resistor R3X is respectively connected with the inverting input end of the operational amplifier U33 and the capacitor C3, the capacitor C3 is connected with the output end of the operational amplifier U33, and the non-inverting input end of the operational amplifier U33 is grounded; the third channel circuit also comprises a second inverter, the second inverter comprises an operational amplifier U34, a resistor R32 and a resistor R35, one end of the resistor R32 is connected with the signal x3The other end of the resistor R32 is connected to the inverting input terminal of the operational amplifier U34 and the resistor R35, the resistor R35 is connected to the output terminal of the operational amplifier U34, the output terminal of the operational amplifier U34 is connected to the resistor R36, and the non-inverting input terminal of the operational amplifier U34 is grounded. The signal x output by the output end of the operational amplifier U333Respectively connected with one end of a resistor R12 and a first multiplierThe comparator a1, one end of the resistor R32, and the fifth multiplier a5 are connected.
As shown in fig. 2(d), the fourth channel circuit includes a fourth multiplier a4, a third inverter, a fourth inverting adder, and a fourth inverting integrator, which are connected in series in this order; the fourth multipliers A4 are respectively connected with the signal x2、x6Connecting; the third inverter comprises an operational amplifier U41, a resistor R41 and a resistor R42, one end of the resistor R41 is connected with the output end of the fourth multiplier A4, the other end of the resistor R41 is respectively connected with the inverting input end of the operational amplifier U41 and the resistor R42, the resistor R42 is connected with the output end of the operational amplifier U41, and the non-inverting input end of the operational amplifier U41 is grounded; the fourth inverting adder comprises an operational amplifier U42, a resistor R43, a resistor R46, a resistor R47, a resistor R48 and a resistor R49, one end of the resistor R43 is connected with the output end of the operational amplifier U41, the other end of the resistor R43, the other end of the resistor R46, the other end of the resistor R47 and the other end of the resistor R48 are connected with the inverting input end of the operational amplifier U42, the resistor R46 is connected with a fourth inverter, one end of the resistor R47 is connected with a signal x 472Connected to one end of resistor R487A resistor R49 is connected between the inverting input end and the output end of the operational amplifier U42, and the non-inverting input end of the operational amplifier U42 is grounded; the fourth inverting integrator comprises an operational amplifier U43, a resistor R4X and a capacitor C4, one end of the resistor R4X is connected with the output end of the operational amplifier U42, the other end of the resistor R4X is respectively connected with the inverting input end of the operational amplifier U43 and the capacitor C4, the capacitor C4 is connected with the output end of the operational amplifier U43, and the non-inverting input end of the operational amplifier U43 is grounded; the fourth channel circuit further comprises a fourth inverter, the fourth inverter comprises an operational amplifier U44, a resistor R44 and a resistor R45, one end of the resistor R44 is connected with the signal x4The other end of the resistor R44 is connected to the inverting input terminal of the operational amplifier U44 and the resistor R45, the resistor R45 is connected to the output terminal of the operational amplifier U44, the output terminal of the operational amplifier U44 is connected to the resistor R46, and the non-inverting input terminal of the operational amplifier U44 is grounded. The signal x output by the output end of the operational amplifier U434Respectively associated with the resistorsOne end of the R22, one end of the second multiplier a2, one end of the resistor R44, and the sixth multiplier a6 are connected.
As shown in fig. 2(e), the fifth channel circuit includes a fifth inverter, a fifth inverting adder, and a fifth inverting integrator, which are connected in series in this order; the fifth inverter comprises an operational amplifier U51, a resistor R51, a resistor R52, one end of the resistor R51 and a signal x5The other end of the resistor R51 is respectively connected with the inverting input end of the operational amplifier U51 and the resistor R52, the resistor R52 is connected with the output end of the operational amplifier U51, and the non-inverting input end of the operational amplifier U51 is grounded; the fifth inverting adder comprises an operational amplifier U52, a resistor R53, a resistor R54 and a resistor R55, one end of the resistor R53 is connected with the output end of the operational amplifier U51, the other end of the resistor R53 and the resistor R54 are both connected with the inverting input end of the operational amplifier U52, the resistor R55 is connected between the inverting input end and the output end of the operational amplifier U52, and the non-inverting input end of the operational amplifier U52 is grounded; the fifth inverting integrator comprises an operational amplifier U53, a resistor R56 and a capacitor C5, one end of the resistor R56 is connected with the output end of the operational amplifier U52, the other end of the resistor R56 is respectively connected with the inverting input end of the operational amplifier U53 and the capacitor C5, the capacitor C5 is connected with the output end of the operational amplifier U53, and the non-inverting input end of the operational amplifier U53 is grounded; signal x3Sum signal x1Are connected to a fifth multiplier a2, a fifth multiplier a5 is connected to a resistor R54. The signal x output by the output end of the operational amplifier U535Is connected to one end of the resistor R51, the first multiplier a1, and the third multiplier A3, respectively.
As shown in fig. 2(f), the sixth channel circuit includes a sixth inverter, a sixth inverting adder, and a sixth inverting integrator, which are connected in series in this order; the sixth inverter comprises an operational amplifier U61, a resistor R61 and a resistor R62, wherein one end of the resistor R61 is connected with the signal x6The other end of the resistor R61 is respectively connected with the inverting input end of the operational amplifier U61 and the resistor R62, the resistor R62 is connected with the output end of the operational amplifier U61, and the non-inverting input end of the operational amplifier U61 is grounded; the sixth inverting adder includes an operational amplifierU62, a resistor R63, a resistor R64 and a resistor R65, wherein one end of the resistor R63 is connected with the output end of the operational amplifier U61, the other end of the resistor R63 and the resistor R64 are both connected with the inverting input end of the operational amplifier U62, the resistor R65 is connected between the inverting input end and the output end of the operational amplifier U62, and the non-inverting input end of the operational amplifier U62 is grounded; the sixth inverting integrator comprises an operational amplifier U63, a resistor R66 and a capacitor C6, one end of the resistor R66 is connected with the output end of the operational amplifier U62, the other end of the resistor R66 is respectively connected with the inverting input end of the operational amplifier U63 and the capacitor C6, the capacitor C6 is connected with the output end of the operational amplifier U63, and the non-inverting input end of the operational amplifier U63 is grounded; signal x2Sum signal x4Are connected to a sixth multiplier a6, a sixth multiplier a6 is connected to a resistor R64. The signal x output by the output end of the operational amplifier U636Is connected to one end of the resistor R61, the second multiplier a2, and the fourth multiplier a4, respectively.
As shown in fig. 2(g), the seventh channel circuit includes a seventh inverter, a seventh inverting adder, and a seventh inverting integrator, which are connected in series in this order; the seventh inverter comprises an operational amplifier U71, a resistor R71 and a resistor R72, one end of the resistor R71 is connected with the output end of the first multiplier A1, the other end of the resistor R71 is respectively connected with the inverting input end of the operational amplifier U71 and the resistor R72, the resistor R72 is connected with the output end of the operational amplifier U71, and the non-inverting input end of the operational amplifier U71 is grounded; the seventh inverting adder comprises an operational amplifier U72, a resistor R73, a resistor R74 and a resistor R75, wherein one end of the resistor R73 is connected with the output end of the operational amplifier U71, and one end of the resistor R74 is connected with the signal x7The other end of the resistor R73 and the other end of the resistor R74 are both connected with the inverting input end of the operational amplifier U72, a resistor R75 is connected between the inverting input end and the output end of the operational amplifier U72, and the non-inverting input end of the operational amplifier U72 is grounded; the seventh inverting integrator comprises an operational amplifier U73, a resistor R76 and a capacitor C7, one end of the resistor R76 is connected with the output end of the operational amplifier U72, the other end of the resistor R76 is respectively connected with the inverting input end of the operational amplifier U73 and the capacitor C7, and the seventh inverting integrator is electrically connected with the inverting input end of the operational amplifier U73 and the capacitor C7Capacitor C7 is connected to the output of operational amplifier U73, with the non-inverting input of operational amplifier U73 connected to ground. The signal x output by the output end of the operational amplifier U737One end of the resistor R38, one end of the resistor R48, and one end of the resistor R74 are connected to each other.
The positive phase input ends of the power supplies of the operational amplifiers U11-U13, U21-U23, U31-U34, U41-U44, U51-U53, U61-U63 and U71-U73 are all connected with a power supply VCC, and the negative phase input ends of the power supplies of the operational amplifiers U11-U13, U21-U23, U31-U34, U41-U44, U51-U53, U61-U63 and U71-U73 are all connected with a power supply VEE.
In order to facilitate the application of the mathematical model to engineering practice, the implementation circuit is designed. The first and second subtractors (U11, U21), first, second, third, fourth, fifth, sixth and seventh inverting adders (U12, U22, U32, U42, U52, U62 and U72), first, second, third, fourth, fifth, sixth and seventh inverting integrators (U13, U23, U33, U43, U43, U43 and U43), first, second, third, fourth, fifth, sixth and seventh inverters ((U43, U43, U43, U43, U43 and U43) are of the same type and are all selected as
R11＝R12＝R13＝R14＝R21＝R22＝R23＝R24＝1kΩ,R27＝17kΩ，
R31＝R32＝R33＝R35＝R41＝R42＝R44＝R45＝1kΩ，R51＝R52＝R61＝R62＝R71＝R72＝1kΩ，
R17＝R39＝R49＝R55＝R65＝R75＝30kΩ,R16＝R26＝R34＝R43＝R54＝R64＝R73＝0.6kΩ,
R18＝R28＝R3X＝R4X＝R56＝R66＝R76＝10kΩ,R15＝R25＝1.111kΩ,R36＝R46＝6kΩ,
R37＝R47＝0.698kΩ,R38＝R48＝8.57kΩ,R53＝R63＝20kΩ,R74＝60kΩ。
the capacitance value is: c1 ═ C2 ═ C3 ═ C4 ═ C5 ═ C6 ═ C7 ═ 1 μ F.
In the implementation circuit, the inputs of the first channel circuit are x1, x3 and x3 × 5, and the output is x 1; the input of the second channel circuit is x2, x4 and x 4x 6, and the output is x 2; the input of the third channel circuit is x1, x3, x1 x5 and x7, and the output is x 3; the input of the fourth channel circuit is x2, x4, x2 x6 and x7, and the output is x 4; the input of the fifth channel circuit is x1 x3 and x5, and the output is x 5; the input of the sixth channel circuit is x2 x4 and x6, and the output is x 6; the input of the seventh channel circuit is x
Fig. 4, fig. 5, fig. 6 and fig. 7 are computer simulation graphs of the complex value hyper-chaotic system in a three-dimensional phase space. Fig. 8, fig. 10, fig. 12 and fig. 14 are computer simulation graphs of the complex value hyperchaotic system on a two-dimensional phase plane. Fig. 9, fig. 11, fig. 13 and fig. 15 are circuit simulation graphs of the hyper-chaotic system on a two-dimensional phase plane. Wherein, the ordinate of fig. 11 is 100mv/div, the abscissa is 200mv/div, the ordinate and the abscissa of fig. 13 are 100mv/div, the ordinate of fig. 9 and fig. 15 is 500mv/div, and the abscissa is 100 mv/div. Comparing the computer simulation graph and the circuit simulation graph of the complex value hyperchaotic system, the graphs of the computer simulation graph and the circuit simulation graph are consistent, and the complex value hyperchaotic attractor generated by the circuit of the invention meets the requirements.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
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