阅读说明：本技术 半导体存储装置 (Semiconductor memory device with a plurality of memory cells ) 是由 志村安广 上野广贵 四方刚 于 2019-07-01 设计创作，主要内容包括：根据一实施方式,半导体存储装置具备第1、第2存储器晶体管、及与它们的栅极电极连接的第1、第2字线。另外,半导体存储装置以依次执行针对第1存储器晶体管的第1写入动作、针对第2存储器晶体管的第1写入动作、针对第1存储器晶体管的第2写入动作、针对第2存储器晶体管的第2写入动作的方式构成。另外,在第1写入动作中,仅执行1次对第1字线或第2字线输入多个编程电压的编程动作,在执行编程动作后仅执行1次对第1字线或第2字线输入一个或多个验证脉冲的验证动作。(According to one embodiment, a semiconductor memory device includes 1 st and 2 nd memory transistors, and 1 st and 2 nd word lines connected to gate electrodes of the memory transistors. The semiconductor memory device is configured to sequentially perform a 1 st write operation to the 1 st memory transistor, a 1 st write operation to the 2 nd memory transistor, a 2 nd write operation to the 1 st memory transistor, and a 2 nd write operation to the 2 nd memory transistor. In the 1 st write operation, only the program operation of inputting a plurality of program voltages to the 1 st word line or the 2 nd word line is performed 1 time, and after the program operation is performed, only the verify operation of inputting one or more verify pulses to the 1 st word line or the 2 nd word line is performed 1 time.)

1. A semiconductor memory device includes:

a memory string including a 1 st memory transistor and a 2 nd memory transistor having a plurality of threshold voltages;

a 1 st word line connected to a gate electrode of the 1 st memory transistor;

a 2 nd word line connected to a gate electrode of the 2 nd memory transistor; and

a controller that performs a write operation and a read operation including a program operation and a verify operation on the 1 st memory transistor and the 2 nd memory transistor; and is

The controller sequentially executes:

a 1 st write operation to write the 1 st memory transistor to a 1 st threshold voltage using only a programming operation;

a 2 nd write act to write the 2 nd memory transistor to a 2 nd threshold voltage using only a programming act;

a 3 rd write operation of writing the 1 st memory transistor to a 3 rd threshold voltage higher than the 1 st threshold voltage using a program operation and a verify operation; and

a 4 th write action to write the 2 nd memory transistor to a 4 th threshold voltage higher than the 2 nd threshold voltage using a program action and a verify action.

2. The semiconductor memory device according to claim 1, wherein

The controller

In the 1 st write operation, a verify operation is performed after the program operation is finished, information indicating whether the 1 st write operation is normally finished is output,

in the 2 nd write operation, a verify operation is performed after the program operation is completed, and information indicating whether the 2 nd write operation is normally completed is output.

3. The semiconductor memory device according to claim 2, wherein

The controller

Classifying the 1 st memory transistor as a defective cell if the information output in the 1 st write operation indicates that the 1 st write operation does not end normally,

and classifying the 2 nd memory transistor as a defective cell when the information output in the 2 nd write operation indicates that the 2 nd write operation does not end normally.

4. The semiconductor memory device according to claim 1, wherein

The controller

The program action and the verify action are performed only once in the 1 st write action,

the program action and the verify action are performed only once in the 2 nd write action,

the program action and the verify action are alternately performed a plurality of times in the 3 rd write action,

the program action and the verify action are alternately performed a plurality of times in the 4 th write action.

5. The semiconductor memory device according to claim 4, wherein

The controller

Ending the 1 st write action after performing the verify action regardless of a result of the verify action in the 1 st write action,

ending the 2 nd write action after performing the verify action regardless of a result of the verify action in the 2 nd write action,

continuing or ending the 3 rd write action according to a result of the verifying action in the 3 rd write action,

and continuing or ending the 4 th writing action according to the result of the verification action in the 4 th writing action.

6. The semiconductor memory device according to claim 1, wherein

Setting a maximum programming voltage supplied to the 1 st memory transistor in the 1 st write operation to a 1 st programming voltage if the data written to the 1 st memory transistor corresponds to a maximum threshold voltage among the plurality of threshold voltages, the 1 st programming voltage being

Setting a maximum programming voltage supplied to the 1 st memory transistor in the 1 st write operation to a 2 nd programming voltage when the data written to the 1 st memory transistor corresponds to a 2 nd higher threshold voltage among the plurality of threshold voltages,

the 1 st programming voltage is greater than the 2 nd programming voltage.

7. The semiconductor memory device according to claim 1, wherein

Data of k (k is an integer of 2 or more) bits is recorded in each of the 1 st memory transistor and the 2 nd memory transistor,

for 2 corresponding to the k bits of data^kOne of all states corresponding to a threshold voltage lower than a specific threshold voltage and all states corresponding to a threshold voltage higher than the specific threshold voltage among the states is assigned a specific bit "0" among the k bits, and the other is assigned the specific bit "1",

after the 2 nd write operation is performed and before the 3 rd write operation is performed, a read operation for reading the specific bit of the 1 st memory transistor is performed.

8. The semiconductor memory device according to claim 7, wherein the number of the program voltages supplied to the 1 st word line in the 1 st write action is less than 2^k－1。

9. The semiconductor memory device according to claim 1, wherein the 2 nd memory transistor is adjacent to the 1 st memory transistor.

10. A semiconductor memory device includes:

a memory string including a 1 st memory transistor and a 2 nd memory transistor;

a 1 st word line connected to a gate electrode of the 1 st memory transistor;

a 2 nd word line connected to a gate electrode of the 2 nd memory transistor; and

a controller connected to the 1 st memory transistor and the 2 nd memory transistor, and configured to record k (k is an integer of 2 or more) bits of data in the 1 st memory transistor and the 2 nd memory transistor, respectively; and is

The controller sequentially executes:

sequentially supplying more than 1 and less than 2 to the 1 st word line^k1 st write action of different programming voltages;

sequentially supplying more than 1 and less than 2 to the 2 nd word line^kA 2 nd write action of different programming voltages;

supplying 2 to the 1 st word line^kThe 3 rd writing action of the programming voltage with the above different sizes; and

supplying 2 to the 2 nd word line^kThe 4 th writing action of the programming voltage with the above different sizes.

11. The semiconductor memory device according to claim 10, wherein

The controller

In the 1 st write operation, after the program voltage is supplied, a verify voltage is supplied to the 1 st word line and information indicating whether the 1 st write operation is normally ended is output,

in the 2 nd write operation, after the program voltage is supplied, a verify voltage is supplied to the 2 nd word line, and information indicating whether the 2 nd write operation is normally ended is output.

12. The semiconductor memory device according to claim 11, wherein

The controller

Classifying the 1 st memory transistor as a defective cell if the information output in the 1 st write operation indicates that the 1 st write operation does not end normally,

and classifying the 2 nd memory transistor as a defective cell when the information output in the 2 nd write operation indicates that the 2 nd write operation does not end normally.

13. The semiconductor memory device according to claim 10, wherein

The controller

In the 1 st write operation, a verify voltage is not supplied to the 1 st word line before all the program voltages are supplied,

in the 2 nd write operation, a verify voltage is not supplied to the 2 nd word line before all the program voltages are supplied,

in the 3 rd write operation, a verify voltage is supplied every time a program voltage is supplied,

in the 4 th write operation, the verify voltage is supplied every time the program voltage is supplied.

14. The semiconductor memory device according to claim 10, wherein

For 2 corresponding to the k bits of data^kOne of all states corresponding to a threshold voltage lower than a specific threshold voltage and all states corresponding to a threshold voltage higher than the specific threshold voltage among the states is assigned a specific bit "0" among the k bits, and the other is assigned the specific bit "1",

after the 2 nd write operation is performed and before the 3 rd write operation is performed, a read voltage is supplied to the 1 st word line.

15. The semiconductor memory device according to claim 14, wherein the number of the program voltages supplied to the 1 st word line in the 1 st write action is less than 2^k－1。

16. The semiconductor memory device according to claim 10, wherein the 2 nd memory transistor is adjacent to the 1 st memory transistor.

Technical Field

The embodiments described below relate to a semiconductor memory device.

Background

A semiconductor memory device including a memory string including a plurality of memory transistors is known.

Disclosure of Invention

One embodiment of the present invention provides a semiconductor memory device which is easy to be miniaturized.

A semiconductor memory device according to one embodiment includes: a memory string including a 1 st memory transistor and a 2 nd memory transistor having a plurality of threshold voltages; a 1 st word line connected to a gate electrode of the 1 st memory transistor; a 2 nd word line connected to a gate electrode of the 2 nd memory transistor; and a controller for performing a write operation and a read operation including a program operation and a verify operation on the 1 st memory transistor and the 2 nd memory transistor. In the semiconductor memory device, the controller controls to sequentially perform the following operations: a 1 st write operation of writing the 1 st memory transistor to a 1 st threshold voltage using only a programming operation; a 1 st write action to write the 2 nd memory transistor to a 2 nd threshold voltage using only the programming action; a 2 nd write operation of writing the 1 st memory transistor to a 3 rd threshold voltage higher than the 1 st threshold voltage using the program operation and the verify operation; and a 2 nd write operation of writing the 2 nd memory transistor to a 4 th threshold voltage higher than the 2 nd threshold voltage using the program operation and the verify operation.

According to the above configuration, a semiconductor memory device which is easy to be miniaturized can be provided.

Drawings

Fig. 1 is a schematic block diagram showing the configuration of a memory system 10.

Fig. 2 is a schematic block diagram showing the configuration of the memory die MD.

Fig. 3 is a schematic circuit diagram showing the configuration of the memory cell array MCA.

Fig. 4 is a schematic block diagram showing the configuration of the sense amplifier module SAM.

Fig. 5 is a schematic circuit diagram showing the configuration of the sense amplifier SA.

Fig. 6 is a schematic plan view showing the configuration of the memory die MD.

Fig. 7 is a schematic plan view showing the structure of the memory cell array MCA.

Fig. 8 is a schematic cross-sectional view showing the configuration of the memory cell array MCA.

Fig. 9 is a schematic cross-sectional view showing the structure of the memory cell MC.

Fig. 10(a) to (c) are schematic diagrams for explaining data recorded in the memory cell MC.

Fig. 11 is a schematic cross-sectional view for explaining a reading operation.

Fig. 12 is a schematic flowchart for explaining the write operation.

Fig. 13 is a schematic cross-sectional view for explaining a writing operation.

FIG. 14 is a schematic histogram to illustrate a fully sequential write.

Fig. 15 is a schematic cross-sectional view for explaining the sequence of writing operations in the full sequential writing.

Fig. 16 is a schematic bar graph illustrating NWI.

Fig. 17 is a schematic histogram to illustrate the blur/fine writing.

FIG. 18 is a schematic histogram to illustrate the blur/fine writing.

Fig. 19 is a schematic cross-sectional view for explaining the sequence of writing operations in the blur/fine writing.

FIG. 20 is a schematic histogram illustrating a two-phase write.

FIG. 21 is a schematic histogram illustrating a two-phase write.

Fig. 22A is a schematic flow chart to illustrate fast blur/fine writing.

Fig. 22B is a schematic waveform diagram to explain fast blur/fine writing.

Fig. 22C is a schematic waveform diagram to explain fast blur/fine writing.

Fig. 23 is a bar graph showing the results of an experiment performed by the inventors.

Fig. 24 is a bar graph showing the results of an experiment performed by the inventors.

Fig. 25 is a bar graph showing the results of an experiment performed by the inventors.

Fig. 26 is a bar graph showing the results of an experiment performed by the inventors.

FIG. 27 is a schematic histogram to illustrate fast dim/fine writing.

FIG. 28 is a schematic histogram to illustrate fast dim/fine writing.

FIG. 29 is a schematic histogram to illustrate fast dim/fine writing.

FIG. 30 is a schematic histogram to illustrate fast dim/fine writing.

Fig. 31 is a schematic histogram to illustrate fast blur/fine writing.

FIG. 32 is a schematic histogram to illustrate fast dim/fine writing.

FIG. 33 is a schematic histogram to illustrate fast blur/fine writing.

FIG. 34 is a schematic histogram to illustrate fast dim/fine writing.

Fig. 35 is a schematic cross-sectional view for explaining the sequence of writing operation in the fast blur/fine writing.

FIGS. 36(a) and (b) are diagrams showing 1-2-4-8 encoding.

Detailed Description

Next, the semiconductor memory device according to the embodiment will be described in detail with reference to the drawings. The following embodiments are merely examples, and are not intended to limit the present invention.

In the present specification, when a "semiconductor memory device" is referred to, a memory die may be referred to, and a memory system including a controller die such as a memory chip, a memory card, or an SSD (Solid State Drive) may be referred to. In addition, the configuration may include a host such as a smartphone, a tablet terminal, or a personal computer.

In the present specification, when the 1 st configuration and the 2 nd configuration are referred to as being "electrically connected", the 1 st configuration may be directly connected to the 2 nd configuration, and the 1 st configuration may be connected to the 2 nd configuration via a wiring, a semiconductor component, a transistor, or the like. For example, when 3 transistors are connected in series, the 1 st transistor is "electrically connected" to the 3 rd transistor even when the 2 nd transistor is in an OFF (OFF) state.

In the present specification, when the 1 st configuration and the 2 nd and 3 rd configurations are referred to as "connected between" there are cases where the 1 st configuration, the 2 nd configuration, and the 3 rd configuration are connected in series and the 1 st configuration is provided on the current path of the 2 nd and 3 rd configurations.

In addition, in this specification, when it is said that a circuit or the like turns "ON" 2 wirings or the like, it may mean that the circuit or the like includes a transistor or the like which is provided in a current path between the 2 wirings and which is turned ON (ON).

[ memory System 10]

Fig. 1 is a schematic block diagram showing the configuration of a memory system 10 according to embodiment 1.

The memory system 10 reads, writes, deletes, and the like user data in accordance with a signal transmitted from the host 20. The memory system 10 is, for example, a memory chip, memory card, SSD, or other system that can store user data. The memory system 10 is provided with a plurality of memory dies MD storing user data and a controller die CD connected with the plurality of memory dies MD and the host 20. The controller die CD includes, for example, a processor, a Random Access Memory (RAM), a Read-Only Memory (ROM), an Error Correction Code (ECC) circuit, and the like, and performs processing such as conversion between a logical address and a physical address, bit Error detection/correction, wear leveling, and the like.

Fig. 2 is a schematic block diagram showing the configuration of the memory die MD of embodiment 1. Fig. 3 to 5 are schematic circuit diagrams showing a partial configuration of the memory die MD.

As shown in fig. 2, the memory die MD includes a memory cell array MCA for storing data and a peripheral circuit PC connected to the memory cell array MCA.

[ memory cell array MCA ]

The memory cell array MCA includes a plurality of memory blocks MB. As shown in fig. 3, each of the plurality of memory blocks MB includes a plurality of sub blocks SB. The plurality of subblocks SB are respectively provided with a plurality of memory strings MS. One ends of the memory strings MS are connected to the peripheral circuit PC via bit lines BL, respectively. The other ends of the memory strings MS are connected to the peripheral circuit PC via common source lines SL.

The memory string MS includes a drain select transistor STD, a plurality of memory cells MC, and a source select transistor STS connected in series between a bit line BL and a source line SL. Hereinafter, the drain select transistor STD and the source select transistor STS may be simply referred to as select transistors (STD, STS).

The memory cell MC of the present embodiment is a field effect transistor (memory transistor) including a semiconductor layer functioning as a channel region, a gate insulating film including a charge storage film, and a gate electrode. The threshold voltage of the memory cell MC varies according to the amount of charge in the charge storage film. The memory cell MC stores 1-bit or multi-bit data. Further, word lines WL are connected to the gate electrodes of the memory cells MC corresponding to the 1 memory string MS, respectively. These word lines WL are commonly connected to all the memory strings MS in the 1 memory block MB, respectively.

The selection transistors (STD, STS) are field effect transistors having a semiconductor layer functioning as a channel region, a gate insulating film, and a gate electrode. The gate electrodes of the selection transistors (STD, STS) are connected to selection gate lines (SGD, SGS), respectively. The drain select line SGD is provided corresponding to the subblock SB, and is commonly connected to all the memory strings MS in 1 subblock SB. The source select line SGS is commonly connected to all the memory strings MS in the 1 memory block MB.

[ peripheral Circuit PC ]

As shown in fig. 2, the peripheral circuit PC as a controller includes a row decoder RD, a sense amplifier module SAM, a voltage generation circuit VG, and a sequencer SQC. The peripheral circuit PC includes an address register ADR, a command register CMR, and a status register STR. The peripheral circuit PC includes an input/output control circuit I/O and a logic circuit CTR.

The row decoder RD includes, for example, a decoding circuit and a switching circuit. The decode circuit decodes the row address RA held in the address register ADR. The switching circuit turns on the word line WL and the select gate line (SGD, SGS) corresponding to the row address RA and the corresponding voltage supply line in accordance with the output signal of the decoding circuit.

As shown in fig. 4, the sense amplifier module SAM is provided with a plurality of sense amplifier units SAU corresponding to a plurality of bit lines BL. The sense amplifier unit SAU includes a sense amplifier SA connected to the bit line BL, data latches SDL, ADL, BDL, CDL, DDL, XDL, a logic circuit OP, and a line LBUS connected to these components.

As shown in fig. 5, the sense amplifier SA includes a sense transistor 31 for discharging the charge on the line LBUS according to the current flowing through the bit line BL. The source electrode of the sense transistor 31 is connected to the node N0. The drain electrode is connected to the wiring LBUS via the switching transistor 32. The gate electrode is connected to the bit line BL via the sense node SEN, the discharge transistor 33, the node COM, and the clamp transistor 34. The sensing node SEN is connected to the node N1 via the charge transistor 35 and the charge transistor 36 and to the internal control signal CLK via the capacitor 37. The node COM is connected to the node N1 through the charge transistor 38 and the charge transistor 36, and is connected to the node N2 through the discharge transistor 39.

The sensing transistor 31, the switching transistor 32, the discharging transistor 33, the clamping transistor 34, the charging transistor 35, the charging transistor 38, the charging transistor 36, and the discharging transistor 39 are NMOS (N-channel Metal oxide semiconductor) transistors, for example. The charge transistor 36 is, for example, a PMOS (P-channel metal Oxide Semiconductor) transistor.

The data latch SDL includes nodes LAT and INV, inverters 41 and 42 connected in parallel to the nodes LAT and INV, a switching transistor 43 connected to the node LAT and a wiring LBUS, and a switching transistor 44 connected to the node INV and the wiring LBU. The switching transistors 43 and 44 are, for example, NMOS transistors.

Data contained in, for example, data latch SDL is transferred as appropriate to data latches ADL, BDL, CDL, DDL (FIG. 4). The logic circuit OP performs a logic operation such as AND/OR on data in the data latches ADL, BDL, CDL, AND DDL, for example, AND calculates user data assigned to the memory cell MC.

The data latch XDL is connected to the wiring LBUS and a wiring DB constituting the bus DB. User data written in the memory cell MC or user data read out from the memory cell MC, for example, is stored in the data latch XDL.

The sense amplifier module SAM includes a decoding circuit and a switching circuit, which are not shown. The decoding circuit decodes the column address CA held in the address register ADR (fig. 2). The switching circuit turns on the data latch XDL corresponding to the column address CA and the bus DB in accordance with an output signal of the decoding circuit.

The voltage generation circuit VG (fig. 2) includes a voltage boosting circuit such as a charge pump circuit connected to a power supply terminal and a ground terminal, a voltage dropping circuit, and a plurality of voltage supply lines (not shown). The voltage generation circuit VG generates a plurality of operation voltages to be supplied to the bit line BL, the source line SL, the word line WL, and the select gate line (SGD, SGS) when performing a read operation, a write operation, and an erase operation for the memory cell array MCA in accordance with an internal control signal from the sequencer SQC, and outputs the plurality of operation voltages simultaneously from a plurality of voltage supply lines.

The sequencer SQC sequentially decodes the command data CMD held in the command register CMR and outputs internal control signals to the row decoder RD, the sense amplifier module SAM, and the voltage generation circuit VG. In addition, the sequencer SQC outputs state data indicating its own state to the state register STR as appropriate. For example, when the write operation or the erase operation is executed, information indicating whether the write operation or the erase operation has ended normally is output as the status data.

The input/output control circuit I/O includes data input/output terminals I/O0 to I/O7, a shift register connected to the data input/output terminals I/O0 to I/O7, and a FIFO buffer connected to the shift register. The input/output control circuit I/O outputs data input from the data input/output terminals I/O0 to I/O7 to the data latch XDL, the address register ADR, or the command register CMR in the sense amplifier module SAM according to an internal control signal from the logic circuit CTR. In addition, data input from the data latch XDL or the status register STR is output to the data input/output terminals I/O0 to I/O7.

The logic circuit CTR receives an external control signal from the controller die CD via the external control terminals/CEn, CLE, ALE,/WE,/RE, and accordingly outputs an internal control signal to the input/output control circuit I/O.

Next, a configuration example of the semiconductor memory device of the present embodiment will be described with reference to fig. 6 to 9. Fig. 6 is a schematic plan view of the semiconductor memory device of this embodiment. Fig. 7 is a schematic enlarged view of a portion indicated by a of fig. 6. FIG. 8 is a schematic sectional view of the structure shown in FIG. 7, taken along the line B-B' and viewed in the direction of the arrows. Fig. 9 is a schematic enlarged view of fig. 8. Fig. 6 to 9 show schematic configurations, and the specific configuration may be modified as appropriate. In fig. 6 to 9, the components are omitted.

As shown in fig. 6, the semiconductor memory device of the present embodiment includes a semiconductor substrate 100. In the illustrated example, 2 memory cell arrays MCA arranged in parallel in the X direction are provided on the semiconductor substrate 100. In addition, a row decoder RD is provided in a region extending in the Y direction along both ends of the memory cell array MCA in the X direction. In addition, a sense amplifier module SAM is provided in a region extending in the X direction along an end portion of the Y direction of the memory cell array MCA. In the regions near both ends in the X direction of the region where the sense amplifier module SAM is provided, the drive circuit DRV is provided. In addition, in the regions outside these regions, a voltage generation circuit VG, a sequencer SQC, an input/output control circuit I/O, and a logic circuit CTR are provided.

The memory cell array MCA includes a plurality of memory blocks MB arranged in the Y direction. In the present embodiment, multi-value data is recorded in the memory cells MC included in the plurality of memory blocks MB. However, 2-value data is recorded in the memory cell MC included in the partial memory block MB. Such memory cells MC are used as the buffer SLCB.

As shown in fig. 7, the memory block MB includes 2 block structures BS arranged in the Y direction. Further, between 2 block structures BS adjacent in the Y direction, an inter-block insulating layer ST extending in the X direction is provided. The word lines WL included in the 2 memory blocks MB are electrically insulated via the inter-block insulating layer ST.

The block structure BS includes 2 sub-blocks SB arranged in the Y direction, and an inter-sub-block insulating layer SHE provided between the two sub-blocks SB.

As illustrated in fig. 8, the sub-block SB includes a plurality of conductive layers 110 and a plurality of semiconductor layers 120 provided above a semiconductor substrate 100, and a plurality of gate insulating films 130 provided between the plurality of conductive layers 110 and the plurality of semiconductor layers 120, respectively.

The semiconductor substrate 100 is, for example, a semiconductor substrate of monocrystalline silicon (Si) or the like containing a P-type impurity. An N-type well containing an N-type impurity such as phosphorus (P) is provided in a part of the surface of the semiconductor substrate 100. In addition, a P-type well containing a P-type impurity such as boron (B) is provided in a part of the surface of the N-type well.

The conductive layer 110 is a substantially plate-shaped conductive layer extending in the X direction, and a plurality of conductive layers are arranged in the Z direction. The conductive layer 110 may be formed of a laminated film of titanium nitride (TiN) and tungsten (W), or may be formed of polysilicon containing an impurity such as phosphorus or boron. In addition, silicon oxide (SiO) is provided between the conductive layers 110₂) Etc. insulating layer 111.

One or more conductive layers 110 positioned at the lowermost layer among the plurality of conductive layers 110 function as a source selection line SGS (fig. 3) and a gate electrode of a plurality of source selection transistors STS connected to the source selection line SGS. The conductive layers 110 located above the lowermost conductive layer function as gate electrodes of the word line WL (fig. 3) and the memory cells MC (fig. 3) connected to the word line WL. The one or more conductive layers 110 located above the conductive layer functioning as the gate electrodes of the word line WL (fig. 3) and the plurality of memory cells MC (fig. 3) connected to the word line WL function as the gate electrodes of the drain select line SGD and the plurality of drain select transistors STD (fig. 3) connected to the drain select line SGD.

As illustrated in fig. 7, a plurality of semiconductor layers 120 are provided in the X direction and the Y direction. The semiconductor layer 120 is, for example, a semiconductor film of undoped polysilicon (Si) or the like. For example, as illustrated in fig. 8, the semiconductor layer 120 has a substantially cylindrical shape, and an insulating film 121 such as silicon oxide is provided in the center portion. The outer peripheral surfaces of the semiconductor layers 120 are surrounded by the conductive layers 110. The lower end portion of the semiconductor layer 120 is connected to the P-type well of the semiconductor substrate 100 via a semiconductor layer 122 made of undoped single crystal silicon or the like. The semiconductor layer 122 faces the conductive layer 110 through an insulating layer 123 of silicon oxide or the like. The upper end of the semiconductor layer 120 is connected to the bit line BL via a semiconductor layer 124 containing an N-type impurity such as phosphorus (P), and contacts Ch and Cb. The semiconductor layer 120 functions as a channel region for each of the memory cells MC and the drain select transistor STD included in 1 memory string MS (fig. 3). The semiconductor layer 122 functions as a part of a channel region of the source select transistor STS.

For example, as shown in fig. 9, the gate insulating film 130 includes a tunnel insulating film 131, a charge storage film 132, and a barrier insulating film 133 laminated between the semiconductor layer 120 and the conductive layer 110. The tunnel insulating film 131 and the barrier insulating film 133 are insulating films such as silicon oxide. The charge storage film 132 is a film capable of storing charge, such as silicon nitride (SiN). The tunnel insulating film 131, the charge storage film 132, and the barrier insulating film 133 have a substantially cylindrical shape, and extend in the Z direction along the outer peripheral surface of the semiconductor layer 120.

Although fig. 9 shows an example in which the gate insulating film 130 includes the charge storage film 132 made of silicon nitride or the like, the gate insulating film 130 may include a floating gate made of polysilicon or the like containing N-type or P-type impurities, for example.

[ threshold voltage of memory cell MC ]

Next, the threshold voltage of the memory cell MC will be described with reference to fig. 10. Fig. 10(a) is a schematic histogram for explaining the threshold voltage of the memory cell MC. The horizontal axis represents the voltage of the word line WL, and the vertical axis represents the number of memory cells MC. Fig. 10(b) shows an example of the threshold voltage of the memory cell MC and data recorded in the memory cell MC. Fig. 10(c) shows another example of the threshold voltage of the memory cell MC and the data recorded in the memory cell MC.

As described above, the memory cell array MCA includes the plurality of memory cells MC. When the write operation is performed on the plurality of memory cells MC, the threshold voltages of the memory cells MC are controlled to a plurality of states. Fig. 10(a) shows the distribution of threshold voltages of the memory cells MC controlled to 8 states. For example, the threshold voltage of the memory cell MC controlled to the a state is larger than the read voltage V of fig. 10(a)_CGARAnd a verification voltage V_VFYAAnd is less than the read voltage V_CGBRAnd a verification voltage V_VFYB. In addition, the threshold voltage of all the memory cells MC is smaller than the read pass voltage V of fig. 10(a)_READ。

In the present embodiment, by adjusting the memory cells MC to 8 states, 3-bit data is recorded in each memory cell MC.

For example, the Er state corresponds to the lowest threshold voltage (threshold voltage of memory cell MC in the erased state). For example, data "111" is assigned to the memory cell MC corresponding to the Er state.

The a state corresponds to a threshold voltage higher than the threshold voltage corresponding to the Er state. For example, data "101" is assigned to the memory cell MC corresponding to the a state.

In addition, the B state corresponds to a threshold voltage higher than the threshold voltage corresponding to the a state. For example, data "001" is assigned to the memory cell MC corresponding to the B state.

Hereinafter, the C state to the G state in the figure correspond to threshold voltages higher than the threshold voltages corresponding to the B state to the F state. The memory cells MC corresponding to these distributions are assigned with, for example, data "011", "010", "110", "100", and "000".

Further, in the case of allocation as illustrated in fig. 10(b), the data of the lower bit can be read by 1 read voltage V_CGDRJudging that the data of the middle bit can be read by 3 read-out voltages V_CGAR、V_CGCR、V_CGFRJudging that the data of the high-order bit can be read by 3 read-out voltages V_CGBR、V_CGER、V_CGGRAnd (6) judging. This data allocation is sometimes referred to as 1-3-3 encoding.

The number of bits of data recorded in the memory cell MC, the number of states, data allocation to each state, and the like can be changed as appropriate.

For example, in the case of allocation as illustrated in fig. 10(c), the data of the lower bit may be read by 1 read voltage V_CGDRJudging that the data of the middle bit can be read by two reading voltages V_CGBR、V_CGFRJudging that the data of the high-order bit can be read by 3 read-out voltages V_CGAR、V_CGCR、V_CGER、V_CGGRAnd (6) judging. This data allocation is sometimes referred to as 1-2-4 encoding.

[ reading action ]

Next, a reading operation of the semiconductor memory device according to the present embodiment will be described with reference to fig. 10 and 11. Fig. 11 is a schematic cross-sectional view for explaining a reading operation. In the following description, an example of assigning data according to the 1-3-3 coding of fig. 10(b) will be described. In the illustrated example, the memory block MB includes 4 sub blocks SB. Hereinafter, the memory strings MS (fig. 3) included in the 4 sub blocks SB are sometimes referred to as a string StrA, a string StrB, a string StrC, and a string StrD, respectively.

When reading the lower bit, for example, as shown in fig. 11, the plurality of selected memory cells MC included in the selected page P are selectively brought into conduction with the bit lines BL and the source lines SL. For example, an ON voltage V is supplied to a drain selection line SGD and a source selection line SGS corresponding to the string StrA (selection page P)_ONThe selection transistors (STD, STS) are turned ON (ON). In addition, an OFF voltage V is supplied to the other drain select line SGD and source select line SGS_OFFThe selection transistors (STD, STS) are turned OFF. In addition, a read pass voltage V is supplied to the unselected word line WL corresponding to the unselected page_READAll the memory cells MC connected to the unselected word line WL are turned ON (ON).

In addition, as shown in FIG. 11, the page is selected and matchedThe selected word line WL corresponding to P supplies a read voltage V_CGDR. Thereby, the memory cells MC corresponding to the Er state to C state in fig. 10(a) are turned ON (ON), and the memory cells MC corresponding to the D state to G state are turned OFF (OFF).

In addition, the ON (ON) state/OFF (OFF) state of the selected memory cell MC is detected by the sense amplifier SA. For example, the wiring LBUS in fig. 5 is charged so that the node STL becomes "H" state and "H" is held in the data latch SDL. In addition, the nodes HLL, BLX, and BLC are brought into the "H" state, and charging of the bit line BL and the sense node SEN is started. In addition, switching the node HLL from the "H" state to the "L" state and switching the node XXL from the "L" state to the "H" state discharges the charge of the sense node SEN to the bit line BL. Here, the voltage of the sense node SEN to which the bit line BL corresponding to the memory cell MC in the ON (ON) state is connected is relatively significantly reduced. On the other hand, the voltage of the sense node SEN connected to the bit line BL corresponding to the memory cell MC in the OFF (OFF) state is not reduced so much. Therefore, by bringing node STB to the "H" state at a specific time point, releasing or maintaining the charge of wiring LBUS, and bringing node STL to the "H" state again, data latches SDL corresponding to selected memory cells MC in the ON (ON) state and the OFF (OFF) state latch "L" and "H" respectively.

Then, the data latched in the data latch SDL is output. For example, the data latched in the data latch SDL is transferred to the controller die CD via the wiring LBUS, the data latch XDL, the bus DB, and the input-output control circuit I/O. The controller die CD performs bit error detection/correction and the like on the data, and transmits the data to the host 20.

When reading the carry bit, for example, the selected memory cell MC is selectively turned on with the bit line BL and the source line SL. Next, for example, a read voltage V is supplied to the selected word line WL_CGARThe ON (ON) state/OFF (OFF) state of the selected memory cell MC is detected, and the data of the data latch SDL is transferred to the data latch ADL. Similarly, a read voltage V is supplied to the selected word line WL_CGCRDetecting the ON/OFF state of the selected memory cell MCThe state, transferring the data of data latch SDL to data latch BDL. Similarly, a read voltage V is supplied to the selected word line WL_CGFRThe ON (ON) state/OFF (OFF) state of the selected memory cell MC is detected, and the data of the data latch SDL is transferred to the data latch CDL. Next, arithmetic processing such as exclusive or is performed by the logic circuit OP, and data of the median bit of the selected memory cell MC is calculated. Then, the calculated data is output.

When reading the high-order bit, for example, the selected memory cell MC is selectively turned on with the bit line BL and the source line SL. Next, for example, a read voltage V is supplied to the selected word line WL_CGBRThe ON (ON) state/OFF (OFF) state of the selected memory cell MC is detected, and the data of the data latch SDL is transferred to the data latch ADL. Similarly, a read voltage V is supplied to the selected word line WL_CGERThe ON (ON) state/OFF (OFF) state of selected memory cell MC is detected, and the data of data latch SDL is transferred to data latch BDL. Similarly, a read voltage V is supplied to the selected word line WL_CGGRThe ON (ON) state/OFF (OFF) state of the selected memory cell MC is detected, and the data of the data latch SDL is transferred to the data latch CDL. Next, arithmetic processing such as exclusive or is performed by the logic circuit OP to calculate data of the upper bits of the selected memory cell MC. Then, the calculated data is output.

[ write operation ]

Next, a writing operation of the semiconductor memory device will be described with reference to fig. 12 and 13. Fig. 12 is a schematic flowchart for explaining the write operation. Fig. 13 is a schematic cross-sectional view for explaining a writing operation.

In step S101, the number of cycles n is set to 1. The number of cycles n is recorded in a register or the like.

In step S102, a programming operation is performed.

In the programming operation, for example, different voltages are supplied to the bit line BL connected to the memory cell MC whose threshold voltage is adjusted and the bit line BL connected to the memory cell MC whose threshold voltage is not adjusted. For example, the node LAT of the data latch SDL (fig. 5) corresponding to the former is set to "H", and the node LAT of the data latch SDL corresponding to the latter is set to "L". Nodes BLX and BLH are set to "H". The ground voltage is supplied to the bit line BL corresponding to the former via the node N0, for example. A specific program inhibit voltage is supplied to the bit line BL corresponding to the latter, for example, via the node N1.

As shown in fig. 13, the memory cell MC with the threshold voltage adjusted is selectively brought into conduction with the bit line BL. For example, an ON voltage V is supplied to a drain select line SGD corresponding to the string StrA (select page P)_ON' an OFF voltage V is supplied to the drain select line SGD_OFF. turn-ON (ON) voltage V_ON' for example, the ON voltage V of FIG. 11 may also be smaller_ON. Thereby, the drain select transistor STD corresponding to the bit line BL supplied with the ground voltage is turned ON (ON), and the drain select transistor STD corresponding to the bit line BL supplied with the program inhibit voltage is turned OFF (OFF). In addition, a write pass voltage V is supplied to the unselected word line WL corresponding to the unselected page_PASS. Write pass voltage V_PASSFor example, the read pass voltage V may also be greater than that of FIG. 11_READ。

In addition, as shown in fig. 13, a program voltage V is supplied to the selected word line WL_PGM. Programming voltage V_PGMGreater than the write pass voltage V_PASS. Thereby, electrons are stored in the charge storage film 132 (fig. 9) of the desired memory cell MC, and the threshold voltage of the memory cell MC increases.

In addition, a plurality of programming voltages V having different magnitudes may be sequentially supplied to the selected word line WL in the 1-time programming operation_PGM. For example, when the selected page P includes a plurality of memory cells MC corresponding to the a-state to the G-state, the selection of the memory cells MC by adjusting the voltage of the bit line BL a plurality of times and the program voltage V may be repeated in 1 programming operation_PGMSupply to the selected word line WL and a programming voltage V_PGMAnd (4) adjusting.

In step S103 (fig. 12), a verification operation is performed. In the verification operation, for example, the selected memory cell MC is selected in the same manner as in the read operationSelectively conductive to the bit lines BL and the source lines SL. Next, for example, a verify voltage V is supplied to the selected word line WL_VFYA、V_VFYB、V_VFYC、V_VFYD、V_VFYE、V_VFYFOr V_VFYG(fig. 10(a)), the ON (ON) state/OFF (OFF) state of the selected memory cell MC is detected, and the data of the data latch SDL is transferred to the data latch XDL.

In the 1-time verify operation, a plurality of verify voltages having different magnitudes may be sequentially supplied to the selected word line WL. For example, when the selected page P includes a plurality of memory cells MC corresponding to the a-state to the G-state, the selection of the memory cells MC, the supply of the verify voltage to the selected word line WL, and the selection of the verify voltage, which are performed by adjusting the voltage of the bit line BL a plurality of times, may be repeated in 1 verify operation.

In step S104, the result of the verification operation is determined. For example, if "L" is included in the data stored in the data latch XDL, the verification is determined to be NG, and the process proceeds to step S105. On the other hand, if all the data stored in the data latch XDL is "H", the verification is determined to be OK, and the process proceeds to step S107.

In step S105, it is determined whether the number of cycles N has reached a specific number N. If not, the process proceeds to step S106. If this is the case, the process proceeds to step S108.

In step S106, the number of cycles n is added to 1, and the process proceeds to step S102.

In step S107, the status register STR (fig. 2) stores status data indicating that the write operation has normally ended, and outputs the status data to the controller die CD (fig. 1) to end the write operation.

In step S108, the status register STR (fig. 2) stores status data indicating that the write operation has not normally ended, and outputs the status data to the controller die CD (fig. 1) to end the write operation. In this case, at least one of the host 20 and the sequencer SQC classifies the selected memory cell MC as a defective cell. For example, at least one of a page address, a block address, and a column address corresponding to the selected memory cell MC is recorded. At least one of the host 20 and the sequencer SQC may also prohibit, for example, a write operation to a page or block including a defective cell or prohibit the use of a bit line BL connected to the defective cell, by referring to at least one of the page address, the block address, and the column address of the record. Such a write operation includes a program operation and a verify operation.

[ writing sequence ]

The above description has been made of the write operation of the semiconductor memory device. Hereinafter, several methods are exemplified as the execution order of the write operation in the memory block MB. In addition, such a method is hereinafter referred to as "writing order" or the like.

[ complete sequential writing ]

Fig. 14 is a schematic histogram for explaining one of the writing sequences. Hereinafter, the writing order shown in fig. 14 is referred to as "full order writing".

The dotted line in the figure indicates the distribution of the threshold voltages of the memory cells MC in the page in the erased state. In the page in the erase state, all the memory cells MC are controlled to the Er state.

The solid line in the figure represents the distribution of the threshold voltages of the memory cells MC in the page after the completely sequential write execution. After the full sequential writing is performed, the memory cell MC is controlled to 8 states.

Fig. 15 is a diagram showing the sequence of executing write operations in the full sequential write. The numbers shown in fig. 15 indicate the order in which the write actions are performed.

In the example of fig. 15, as the 1 st to 4 th write operations, the write operation is performed on the page corresponding to the lowermost word line WL. Next, as the 5 th to 8 th write operations, the write operation is performed on the page corresponding to the 2 nd layer word line WL. Hereinafter, similarly, as the 9 th to 20 th write operations, the write operation is performed on the page corresponding to the 3 rd to uppermost word line WL.

In this method, if the 5 th write operation corresponding to the string StrD and the 2 nd layer word line WL is performed as shown in fig. 15, for example, the distribution of the threshold voltages of the memory cells MC included in the page on which the 1 st write operation corresponding to the string StrD and the 1 st layer word line WL is performed may be widened as shown in fig. 16. The reason is considered to be that: due to the fringe electric field generated in the 5 th write operation, electrons are injected into the portion of the charge storage film 132 corresponding to the space between the word lines WL (the portion indicated by a in fig. 9). Hereinafter, this phenomenon is referred to as NWI (neighbor Word Line Interference).

If the distribution of the threshold voltage of the memory cell MC becomes wide, for example, the threshold voltage of the memory cell MC controlled to be in the A state becomes larger than the read voltage V_CGBRAnd is read as a B state, or the like, when a bit error increases. When the bit error rate is equal to or larger than a certain level, the bit error detection/correction in the controller die CD (fig. 1) may be difficult, and the data may not be read normally.

In addition, NWI appears more prominently as the distance between word lines decreases. However, with the high integration of the semiconductor memory device, the distance between adjacent word lines WL in the Z direction tends to decrease.

[ blur/Fine write ]

Fig. 17 and 18 are schematic histograms to illustrate other write sequences. Hereinafter, the writing sequence shown in fig. 17 and 18 is referred to as "blur/fine writing".

In the foggy/fine writing, the control of the threshold voltage of the memory cell MC is performed in two stages of the "foggy writing operation" and the "fine writing operation" in order to suppress the influence of NWI. In the foggy write operation, as shown in fig. 17, the threshold voltage of the memory cell MC is controlled to be smaller than the final target threshold voltage. For example, the voltage supplied to the selected memory cell MC in the verify operation (step S103 in fig. 12) is set to be lower than the normal verify voltage. In the fine write operation, as shown in fig. 18, the threshold voltage of the memory cell MC is more accurately controlled.

In fig. 17, threshold distributions of the memory cells MC corresponding to the Er state to the G state after the execution of the blur writing are shown as foge to FogG, respectively. Similarly, the threshold distributions of the memory cells MC corresponding to the Er state to the G state after the fine writing are performed are shown as FineEr to FineG, respectively.

Hereinafter, the verify voltage V in the verify operation of the fuzzy write operation may be set_VFYA～V_VFYGIs recorded as fuzzy verification voltage V_FOGVA～V_FOGVGAnd the like. In addition, the verification voltage V in the verification operation of the fine write operation may be set_VFYA～V_VFYGRecording as a fine verification voltage V_FINVA～V_FINVGAnd the like. Fuzzy verification voltage V_FOGVA～V_FOGVGAre respectively less than the fine verification voltage V_FINVA～V_FINVG. In addition, a fine verify voltage V_FINVA～V_FINVGRespectively having a verify voltage V for use in full sequential writing or the like_VFYA～V_VFYGThe same degree of size.

FIG. 19 is a diagram showing the sequence of the fuzzy write operation and the fine write operation. The numbers shown in fig. 19 indicate the order in which the write actions are performed.

In the example of fig. 19, as the 1 st to 4 th write operations, the blur write operation is performed on the page corresponding to the lowermost word line WL. Next, as the 5 th to 12 th write operations, the fuzzy write operation for the page corresponding to the 2 nd layer word line WL and the fine write operation for the page corresponding to the 1 st layer word line WL are alternately executed. Similarly, as the 13 th to 36 th write operations, the fuzzy write operation for the page corresponding to the word line WL from the 3 rd to the uppermost layer and the fine write operation for the page corresponding to the word line WL from the 2 nd to the lower layer than the uppermost layer are alternately performed. Then, as the 37 th to 40 th write operations, a fine write operation is performed on the page corresponding to the uppermost word line WL.

In this method, if, for example, the 5 th vague write operation corresponding to the string StrD and the 2 nd word line WL is performed, the influence of NWI is generated on the page on which the 1 st vague write operation corresponding to the string StrD and the 1 st word line WL has been performed. However, in the 1 st foggy write operation, the threshold voltage of the memory cell MC is controlled to be lower than the final level. Therefore, even if the influence of NWI occurs, the final threshold voltage can be suppressed from greatly exceeding the allowable range. Therefore, by executing the 6 th fine write operation after the 5 th blur write operation is completed, the influence of the NWI due to the 5 th blur write operation can be greatly suppressed.

In this method, if, for example, the 14 th fine write corresponding to the string StrD and the 2 nd layer word line WL is performed, the influence of NWI is exerted on the page on which the 6 th fine write corresponding to the string StrD and the 1 st layer word line WL is performed. However, the page on which the 14 th fine write action is to be performed has been subjected to the vague write action. Therefore, the program voltage V supplied to the word line WL at the 14 th fine write operation_PGMIs small compared to the write action in a fully sequential write. Therefore, the influence of NWI on the page on which the 6 th fine write action has been performed can be greatly suppressed as compared with the case of full sequential writing.

As described above, according to the blur/fine writing, the influence of NWI can be suppressed greatly compared to the full sequential writing.

However, in the fuzzy/fine writing, the number of steps is larger than that in the full sequential writing, and it is difficult to speed up the processing.

In the case of the full sequential writing, if data corresponding to the lower bit, the middle bit, and the upper bit is obtained, the writing operation is executed, and after the writing operation is executed, the reading operation is executed. On the other hand, in the blur/fine writing, the read operation cannot be performed until the fine writing operation is performed. In the example of fig. 19, the fine write operation cannot be performed until the blur write operation corresponding to the 5 th write operation is performed. Therefore, all the data inputted before this time must be written in the buffer memory SLCB (fig. 6) or the like in advance. Therefore, the area of the buffer memory SLCB or the like may be increased.

[ two-stage writing ]

Fig. 20 and 21 are schematic histograms to illustrate other writing sequences. Hereinafter, the writing procedure shown in fig. 20 and 21 is referred to as "two-stage writing".

In the two-stage write, the control of the threshold voltage of the memory cell MC is divided into "first-stage write operation" and "second-stage write operation" to suppress the influence of NWISegment write action "these two phases are performed. In the first-stage write operation, as shown in fig. 20, the memory cell MC corresponding to the lower state (Er state to C state in fig. 10) is brought into the L state, and the memory cell MC corresponding to the upper state (D state to G state in fig. 10) is brought into the M state. For example, the voltage supplied to the selected memory cell MC in the verify operation (step S103 in fig. 12) is set to be lower than the verify voltage V_VFYDSpecific verification voltage V_VFYMThe write operation is executed to the memory cell MC corresponding to the upper state. In the second stage write operation, as shown in fig. 21, the threshold voltage of the memory cell MC is more accurately controlled. Verification voltage V in second stage write operation_VFYA～V_VFYGRespectively having a verify voltage V for use in full sequential writing or the like_VFYA～V_VFYGThe same degree of size.

The two-stage writing is performed in the same order as the blur/fine writing, for example, as shown in fig. 19.

According to the two-stage writing, the speed can be greatly increased compared with the blur/fine writing. The reason for this is that: the threshold voltage of the memory cell MC is controlled to 8 in the foggy write operation, whereas the threshold voltage of the memory cell MC is controlled to only 2 in the first-stage write operation.

However, in the first-stage write operation, the threshold voltage of the memory cell MC corresponding to the upper state is controlled to be lower than the read voltage V_CGER(FIG. 10). The reason for this is that: the memory cell MC corresponding to the upper state also includes a memory cell corresponding to the D state. Therefore, in the second stage write operation, the threshold voltage of the memory cell MC corresponding to the G state must be controlled to the read voltage V_CGERFrom the following magnitude to a verification voltage V_VFYGThe above sizes. Therefore, the programming voltage V supplied to the word line WL in the second stage write operation_PGMIs larger than the fine writing action. Therefore, for example, if the second-stage write operation is performed as the 14 th write operation in fig. 19, there is a case where a relatively large NWI shadow is generated in the memory cell MC on which the second-stage write operation is performed as the 6 th write operationA loud condition.

[ Rapid blur/Fine write ]

FIG. 22A is a schematic flow chart illustrating other writing sequences. The writing sequence explained below is referred to as "fast blur/fine writing".

In the fast dim/fine write, the control of the threshold voltage of the memory cell MC is performed in two stages of "fast dim write operation" and "fine write operation" in order to suppress the influence of NWI.

In the fast foggy write operation, the write operation is completed in 1-time programming operation without verifying operation so that the memory cell MC to be written has the target threshold voltage value. In other words, in the fast foggy write operation, writing is performed to the memory cell MC to be written using only the programming operation. In some cases, the verification operation is performed only once after the target threshold voltage value is written in the memory cell MC to be written. This verification operation is not used for writing to the memory cell MC to be written.

Unlike the write operation described with reference to fig. 12, in the fast dim write operation, as shown in fig. 22A, even in the case of verification NG, only the program operation is performed 1 time and only the verification operation is performed 1 time or less. Therefore, steps S101, S105, and S106 relating to the setting and determination of the loop count n are not included, and the process proceeds to step S108 when NG is verified. For example, in the case of verification NG, the memory cell MC is set as a defective cell without performing additional writing.

In the fast dim write operation, the target threshold voltage of the memory cell MC is controlled to be smaller than the final target threshold voltage as shown in fig. 17, for example. For example, the programming voltage is adjusted in a manner that can be written as a target threshold voltage in a fuzzy write. Hereinafter, the procedure of performing the fuzzy writing of the C state to a selected memory cell MC will be described as an example.

In step S102 of the fast dim write operation, the program voltage V corresponding to the a state is set as shown in fig. 22B_FOGPAProgramming voltage V corresponding to the G state_FOGPGAre sequentially supplied to the selected word line WL. For the memory cell MC corresponding to the C state, a programming voltage V for performing fuzzy writing of the A state is first supplied_FOGPAThe fuzzy writing of the A state is performed, and then the programming voltage V for performing the fuzzy writing of the B state is supplied_FOGPAAnd the B state is written with blur. Finally, a programming voltage V for performing fuzzy C-state writing is supplied_FOGPCAnd the fuzzy writing of the C-state is performed. Thereby, the selected memory cell MC is subjected to the fuzzy writing of the C state. In this case, the a state to the C state are overwritten on a selected memory cell MC. In addition, when the programming voltage V is supplied_FOGPD～V_FOGPGAt time point (b), a program inhibit voltage is supplied to the bit line BL connected to the memory cell MC corresponding to the C state. In addition, a plurality of programming voltages V_FOGPA～V_FOGPGHas a size of V_FOGPA＜V_FOGPB＜V_FOGPC＜V_FOGPD＜V_FOGPE＜V_FOGPF＜V_FOGPGThe relationship (2) of (c).

In addition, the program voltage V may be supplied to the selected word line WL_FOGPA、V_FOGPBDuring which a program-inhibit voltage is supplied to the bit line BL to which the memory cell MC corresponding to the C state is connected. In this case, the programming voltage V is used_FOGPCOne fuzzy write of the C state is performed to a selected memory cell MC.

The other memory cells MC corresponding to the a-state to the G-state are also subjected to the foggy write by the same method. During this period, the threshold voltage may not be checked by the verify operation. The threshold voltage may be checked once after all the fuzzy writing is completed by the verifying operation.

In addition, a fine write operation is performed on the memory cell MC written by the fast dim write operation. For example, as illustrated in fig. 22C, the program operation (step S102 in fig. 12) and the verify operation (step S103 in fig. 12) are alternately performed to adjust the threshold voltage of the memory cell MC corresponding to the a state to the final target threshold voltage. Next, the program operation and the verify operation are alternately performed to adjust the threshold voltage of the memory cell MC corresponding to the B state to the final target threshold voltage. In the following, the same shall applyThe threshold voltage of the memory cell MC corresponding to the C-state to the G-state is adjusted to the final target threshold voltage. Programming voltage V for fast fuzzy write operation_FOGPA～V_FOGPGRespectively lower than the programming voltage V for the fine write operation_FINPA～V_FINPG. In addition, Δ PG in fig. 22C indicates the program voltage V due to the increase in the number of cycles n (fig. 12)_FOGPAThe amount of increase of (c).

In addition, the fast blur/fine writing may be performed in the order as shown in fig. 19, for example.

[ comparison of writing order ]

The inventors have conducted experiments to perform the comparison of the 4 writing orders. In the experiment, the 4 writing orders were executed, and the time required from the start to the end of execution and the threshold distribution after execution were compared. In addition, in the experiment, two samples were used. As the sample of the 2 nd type, a sample in which the thickness of the word line WL in the Z direction is smaller than that of the sample of the 1 st type was used.

The time required for execution to begin to end is compared and the result is the shortest for full sequential writing and the longest for fuzzy/fine writing. The two-stage writing is the same degree as the fast blur/fine writing.

Fig. 23 to 26 are histograms showing the comparison results of the threshold distributions. Fig. 23 and 24 correspond to sample No. 1, fig. 23 shows the results of an experiment performed at a high temperature, and fig. 24 shows the results of an experiment performed at a low temperature. Fig. 25 and 26 correspond to the 2 nd sample, with fig. 25 showing the results of an experiment performed at a high temperature, and fig. 26 showing the results of an experiment performed at a low temperature.

As shown in fig. 23 to 26, the effect of NWI was the greatest in the full sequential writing, and particularly in the 2 nd sample, the effect was significant. On the other hand, the impact of NWI is minimal in fast dim/fine writing. In particular, in sample 2, the effect of NWI was minimal compared to the full sequential writing and the two-stage writing.

From the above results, it is understood that the influence of NWI can be significantly reduced by relatively high-speed processing based on the fast blur/fine writing. It is also known that such an effect is more remarkable with the miniaturization of the semiconductor memory device. From the above, a semiconductor memory device which is easy to be miniaturized can be realized according to the fast blur/fine writing.

[ omission of Programming Voltage ]

In the fast dim/fine write, the supply of one or more program voltages in the fast dim write operation is omitted, thereby realizing further high speed.

For example, the supply of the program voltage corresponding to the a state may be omitted, or the supply of the program voltage corresponding to the a state and the B state may be omitted as shown in fig. 27. That is, fast fuzzy writing is not performed for the a state and the B state. Then, as shown in fig. 28, fine writing is performed by the program voltages corresponding to the a-state to the G-state, respectively.

The supply of the program voltage corresponding to the a-state to the C-state may be omitted as shown in fig. 29. That is, fast fuzzy writing is not performed for the a-state and the C-state. Then, as shown in fig. 30, fine writing is performed by the program voltages corresponding to the a-state to the G-state, respectively.

Thereby, a further high speed of the fast blur/fine writing can be realized. In the programming operation of the low state in the fine write operation, a relatively small program voltage is supplied only to the selected word line WL. Therefore, NWI can be suppressed well even if such supply of the program voltage is omitted.

For example, in the case where the programming voltage corresponding to the upper states (D state to G state) is supplied while omitting the supply of the programming voltage corresponding to the lower states (a state to C state) in the fast dim write operation, a constant voltage difference is generated between the threshold distribution foge corresponding to the lower state and the threshold distribution FogD corresponding to the D state at the time point when the fast dim write operation is performed, as shown in fig. 29. Therefore, for example, the allocation may be performed by using the 1-3-3 coding described with reference to fig. 10(a), the 1-2-4 coding described with reference to fig. 10(b), or the like, so that the reading operation can be performed at a point in time when the fast blur writing operation is performed. In such a read operation, for example, a threshold distribution foge and a threshold distribution foge corresponding to the D state are supplied to the selected word line WLVoltage V between threshold distributions FogD_SLC. Thus, it is not necessary to record the data of the lower bits in the buffer memory SLCB. Therefore, the area of the buffer memory SLCB in the memory cell array MCA can be reduced.

In this method, the memory cell MC that performs the fast dim write operation functions as a part of the buffer memory. Therefore, when the fine write operation is performed, the data of the middle bit and the data of the high bit are read from the buffer memory SLCB, and the data of the low bit is read from the selected page. This readout is performed substantially in the same manner as the readout operation. However, the data of the lower bits, the middle bits, and the upper bits read by such reading may not be output to the controller die CD or the like. The fine write action is performed after such a read.

In addition, in the fast dim/fine write, a further increase in speed can be achieved by simultaneously supplying a program voltage to the memory cells MC corresponding to a plurality of states.

For example, the same level of program voltage may be supplied to the memory cells MC corresponding to a plurality of lower-level states. In the example shown in fig. 31, programming voltages of the same magnitude are supplied to the memory cells MC corresponding to the a-state to C-state, and the a-state to C-state are written in the same state when the fast-foggy write is performed. Then, as shown in fig. 32, fine writing is performed by the program voltages corresponding to the a-state to the G-state, respectively. Thereby, a further high speed of the fast blur/fine writing can be realized. In addition, it is considered that NWI can be suppressed well. In addition, the area of the buffer memory SLCB can be reduced.

In addition, for example, different states can be written simultaneously in the memory cells MC corresponding to a plurality of states by controlling the voltage of the bit line BL to a plurality of voltages. In the fast dim write shown in fig. 33, the a-state and the B-state are written by the same program voltage, the C-state and the D-state are written by the same program voltage, and the E-state and the F-state are written by the same program voltage. Then, as shown in fig. 34, the a-state and the B-state are finely written with the same program voltage, the C-state and the D-state are finely written with the same program voltage, and the E-state and the F-state are finely written with the same program voltage.

In addition, the voltage of the bit line BL can be adjusted by various methods. For example, when charging the bit line BL, the data of the data latch SDL corresponding to the bit line BL in a specific state may be switched from "H" to "L" or from "L" to "H", or at least one of the node N0 and the node N1 of the sense amplifier SA may be connected to two kinds of voltage supply lines.

[ other embodiments ]

For example, the writing sequence of the fast blur/fine writing or the like may be performed in the order as illustrated in fig. 19. However, for example, as illustrated in fig. 35, a fast dim write operation or the like may be performed on a page corresponding to the lowermost word line WL, a fast dim write operation or the like may be performed on a page corresponding to the 2 nd word line WL, a fine write operation may be performed on a page corresponding to the lowermost word line WL, a fast dim write operation may be performed on a page corresponding to the 3 rd word line WL, and the fine write operation may be performed on a page corresponding to the 2 nd word line WL.

In addition, the above description has been made of an example in which the threshold voltage of the memory cell MC is controlled to 8 states and 3-bit data is recorded in each memory cell MC, as shown in fig. 10(a), for example. However, the number of data recorded in the memory cell MC may be changed as appropriate as long as the data is multi-bit data having 2 or more bits. For example, when k (k is an integer of 2 or more) bits of data are recorded in the memory cell MC, the memory cell MC is controlled to be 2^kAnd (4) a state.

For example, as shown in fig. 36(a), the threshold voltage of each memory cell MC may be controlled to 16 states so that 4 bits of data are stored in each memory cell MC. In this case, for example, as shown in fig. 36(b), the data of the 1 st bit can be determined by 1 readout voltage, the data of the 2 nd bit can be determined by two readout voltages, the data of the 3 rd bit can be determined by 4 readout voltages, and the data of the 4 th bit can be determined by 8 readout voltages. This data allocation method is sometimes referred to as 1-2-4-8 encoding. Even in this case, the area of the buffer memory SLCB can be reduced by combining with, for example, the method illustrated in fig. 29 to 32.

The 1-3-3 codes (fig. 10(b), 1-2-4 codes (fig. 10(c)), 1-2-4-8 codes (fig. 36(b)) and the like have assignments such that lower bits data can be determined from 1 readout voltage, however, assignments such as 3-1-3 codes or 3-3-1 codes and the like that can determine data other than lower bits from 1 readout voltage may be made.

In fig. 15, 19, 35, and the like, data is written from the source side of the memory string (either one of the source lines). However, the same effect can be obtained by writing data from the drain side of the memory string (either side of the bit line).

The semiconductor memory device of the embodiment has been described above. However, the above description is merely exemplary, and the above configuration, method, and the like can be appropriately adjusted. In addition, the plurality of embodiments may be combined, respectively.

[ others ]

While particular embodiments of the present invention have been described above, these embodiments have been presented by way of example only, and are not intended to limit the scope of the invention. Indeed, the novel methods and systems described herein may be embodied in various other forms and various omissions, substitutions, and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.