Digital-to-analog converter device and correction method
阅读说明：本技术 数字模拟转换器装置与校正方法 (Digital-to-analog converter device and correction method ) 是由 周晓波 于 2019-02-27 设计创作，主要内容包括：本申请提供了数字模拟转换器装置与校正方法,所述数字模拟转换器装置包含数字模拟转换器电路系统以及校正电路系统。数字模拟转换器电路系统包含第一数字模拟转换器电路与第二数字模拟转换器电路,其根据输入式样产生第一信号与第二信号,输入式样包含数量不同的至少第一逻辑值与至少一第二逻辑值。校正电路系统根据多个第一比较结果与第二比较结果执行校正运算,以产生用于控制第二数字模拟转换器电路的控制信号。第一比较结果为当输入式样为第一式样时第一信号与第二信号的比较结果,第二比较结果为当该输入式样为第二式样时第一信号与第二信号的比较结果,且第一式样相反于第二式样。(The application provides a digital-to-analog converter device and a correction method. The digital-to-analog converter circuit system comprises a first digital-to-analog converter circuit and a second digital-to-analog converter circuit, which generate a first signal and a second signal according to an input pattern, wherein the input pattern comprises at least a first logic value and at least a second logic value which are different in quantity. The correction circuitry performs a correction operation based on the plurality of first comparison results and the second comparison results to generate a control signal for controlling the second digital-to-analog converter circuit. The first comparison result is the comparison result of the first signal and the second signal when the input pattern is the first pattern, the second comparison result is the comparison result of the first signal and the second signal when the input pattern is the second pattern, and the first pattern is opposite to the second pattern.)
1. A digital to analog converter apparatus, comprising:
a digital-to-analog converter circuitry, comprising:
a first digital-to-analog converter circuit; and
a second digital-to-analog converter circuit,
the first digital-to-analog converter circuit and the second digital-to-analog converter circuit are used for generating a first signal and a second signal according to an input pattern, the input pattern comprises at least one first logic value and at least one second logic value, and the number of the at least one first logic value is different from the number of the at least one second logic value; and
a calibration circuit system for performing a calibration operation according to the first comparison results and the second comparison results to generate a control signal for controlling the second digital-to-analog converter circuit,
wherein the first comparison result is a comparison result of the first signal and the second signal when the input pattern is a first pattern, the second comparison result is a comparison result of the first signal and the second signal when the input pattern is a second pattern, and the first pattern is opposite to the second pattern.
2. The digital-to-analog converter device of claim 1, wherein the correction circuitry comprises:
a comparator circuit for comparing the first signal with the second signal to generate a plurality of comparison signals;
an averaging circuit for averaging the comparison signals to generate an average signal;
a polarity judgment circuit for determining whether the average signal is greater than 0 to generate a correction signal; and
the processing circuit is used for executing the correction operation according to the correction signal to generate a first control code when the input pattern is the first pattern, and executing the correction operation according to the correction signal to generate a second control code when the input pattern is the second pattern, so as to generate the control signal according to the first control code and the second control code.
3. The digital-to-analog converter device of claim 2, wherein the processing circuit is configured to average the first control code and the second control code to generate the control signal.
4. The digital-to-analog converter device of claim 1, wherein the first digital-to-analog converter circuit is configured to process a plurality of least significant bits of a digital data, and the second digital-to-analog converter circuit is configured to process a plurality of most significant bits of the digital data.
5. The digital-to-analog converter device of claim 1, wherein the first digital-to-analog converter circuit comprises a current source circuit, and the first digital-to-analog converter circuit is configured to direct a current of the current source circuit to different output terminals of the digital-to-analog converter circuit system according to the input pattern to generate the first signal and the second signal.
6. The digital-to-analog converter device of claim 1, wherein the second digital-to-analog converter circuit comprises a current source circuit, and the second digital-to-analog converter circuit is configured to direct a current of the current source circuit to different output terminals of the digital-to-analog converter circuit system according to the input pattern to generate the first signal and the second signal.
7. A calibration method, comprising:
generating a first signal and a second signal by a first digital-to-analog converter circuit and a second digital-to-analog converter circuit according to an input pattern, wherein the input pattern comprises at least one first logic value and at least one second logic value, and the number of the at least one first logic value is different from the number of the at least one second logic value; and
performing a calibration operation according to the first comparison results and the second comparison results to generate a control signal for controlling the second DAC circuit,
wherein the first comparison result is a comparison result of the first signal and the second signal when the input pattern is a first pattern, the second comparison result is a comparison result of the first signal and the second signal when the input pattern is a second pattern, and the first pattern is opposite to the second pattern.
8. The calibration method of claim 7, wherein generating the control signal comprises:
comparing the first signal with the second signal to generate a plurality of comparison signals; and
the plurality of comparison signals are averaged to generate an average signal.
9. The calibration method of claim 8, wherein generating the control signal further comprises:
determining whether the average signal is greater than 0 to generate a calibration signal;
when the input pattern is the first pattern, executing the correction operation according to the correction signal to generate a first control code;
when the input pattern is the second pattern, executing the correction operation according to the correction signal to generate a second control code; and
the control signal is generated according to the first control code and the second control code.
10. The calibration method of claim 9, wherein generating the control signal comprises:
averaging the first control code and the second control code to generate the control signal.
Technical Field
The present disclosure relates to digital-to-analog converters, and more particularly, to a digital-to-analog converter capable of eliminating amplitude errors and timing errors and a calibration method thereof.
Background
Digital-to-analog converters are commonly found in a variety of electronic devices. In practical applications, due to various variations or circuit offsets, an amplitude error and/or a timing error may occur in an output signal of the digital-to-analog converter. In some applications (e.g., when the load is an inductive device), the two errors cannot be eliminated simultaneously, or a relatively complex and area-consuming calibration circuit is required to eliminate the two errors.
Disclosure of Invention
To solve the above problem, some embodiments of the present disclosure provide a digital-to-analog converter (DAC) device including DAC circuitry and correction circuitry. The DAC circuitry includes a first DAC circuit and a second DAC circuit. The first DAC circuit and the second DAC circuit are used for generating a first signal and a second signal according to an input pattern, the input pattern comprises at least one first logic value and at least one second logic value, and the number of the at least one first logic value is different from the number of the at least one second logic value. The correction circuitry is configured to perform a correction operation according to the first comparison results and the second comparison results to generate a control signal for controlling the second DAC circuit. The first comparison result is the comparison result of the first signal and the second signal when the input pattern is the first pattern, the second comparison result is the comparison result of the first signal and the second signal when the input pattern is the second pattern, and the first pattern is opposite to the second pattern.
Some embodiments of the present disclosure provide a calibration method, comprising the operations of: generating a first signal and a second signal according to an input pattern by a first DAC circuit and a second DAC circuit, wherein the input pattern comprises at least one first logic value and at least one second logic value, and the number of the at least one first logic value is different from the number of the at least one second logic value; and performing a calibration operation according to a plurality of first comparison results and a plurality of second comparison results to generate a control signal for controlling the second DAC circuit, wherein the first comparison result is a comparison result of the first signal and the second signal when the input pattern is the first pattern, the second comparison result is a comparison result of the first signal and the second signal when the input pattern is the second pattern, and the first pattern is opposite to the second pattern.
In summary, some embodiments of the present disclosure provide a DAC device and a calibration method thereof, which can calibrate the circuit offset in the DAC device by using dc unbalanced input pattern and averaging operation, so as to improve the problems of amplitude error and timing error.
Drawings
The drawings of the disclosure are illustrated as follows:
fig. 1 is a schematic diagram of a digital-to-analog converter (DAC) device according to some embodiments of the present disclosure;
FIG. 2 is a circuit schematic diagram of the DAC circuit of FIG. 1 shown in accordance with some embodiments of the present disclosure;
FIG. 3 is a waveform schematic of the analog output of FIG. 1 and a related art analog output, plotted according to some embodiments of the present disclosure; and
FIG. 4 is a flow chart of a calibration method according to some embodiments of the present disclosure.
Description of the symbols
100: digital-to-analog converter device 110: inverter with a capacitor having a capacitor element
120: DAC circuitry SIP: inputting a pattern
And SS: switching signal T1: during a predetermined period
1. 0: logical values 121, 122: DAC circuit
121A, 121B: DAC O1, O2: output end
S1, S2: signal SOUT: analog output
130: correction circuitry a 1: average signal
132: the averaging circuit 131: comparator circuit
134: the processing circuit 133: polarity judging circuit
CC. C1, C2: control code CO 1: comparing signals
134B: control circuit SCA: correcting signal
C [0] to C [6 ]: bit 134A: correction circuit
201-208: the current source circuit SC: control signal
210. 218: switching circuits 122-0 to 122-14: unit circuit
M1-M4: switches 211 to 217: current source circuit
T0-T6: switches 56I, 8I, 4I: electric current
301A, 301B: waveform 0.125I, 32I, 16I, I: electric current
302A, 302B: waveforms A1-A4: area of
303A, 303B: waveform 400: correction method
S410 and S420: operations S430, S440, S450: operation of
Detailed Description
As used herein, the term "circuit system" generally refers to a single system comprising one or more circuits (circuits). The term "circuit" broadly refers to an object connected in some manner by one or more transistors and/or one or more active and passive components to process a signal.
For ease of understanding, like elements in the various figures will be designated with the same reference numerals.
Fig. 1 is a schematic diagram of a digital-to-analog converter (DAC) device 100 according to some embodiments of the present disclosure.
DAC device 100 includes an inverter 110, DAC circuitry 120, and correction circuitry 130. The inverter 110 receives an input pattern (input pattern) SIP and outputs a switching signal SS. That is, the input pattern SIP is opposite to the switching signal SS. In some embodiments, the input pattern SIP is a test signal for calibrating the DAC device 100. In some embodiments, the input pattern SIP has at least one logic value 1 and at least one logic value 0 within the predetermined period T1, and the number of the at least one logic value 1 is different from the number of the at least one logic value 0.
The DAC circuitry 120 includes a plurality of DAC circuits 121 and 122. DAC circuit 121 includes DAC 121A and DAC 121B. The DAC 121A processes N Least Significant Bits (LSBs) of a digital data (not shown). DAC121B provides additional current I. DAC circuit 122 processes the M Most Significant Bits (MSBs) of the digital data. The DAC circuitry 120 may generate corresponding analog outputs SOUT from the output terminals O1 and O2 according to the digital data.
The DAC circuits 121 and 122 generate signals S1 and S2 to the output terminals O1 and O2, respectively, according to the input pattern SIP and the switching signal SS. For example, DAC circuits 121 and 122 each include a current source circuit (shown later in fig. 2) that provides a current. The DAC circuits 121 and 122 each direct different currents to the output terminals O1 and O2 according to the input pattern SIP. Thus, the plurality of currents superimposed on the output terminal O1 form the signal S1, and the plurality of currents superimposed on the output terminal O2 form the signal S2.
The calibration circuitry 130 is coupled to the output terminals O1 and O2 for receiving the signals S1 and S2. In some embodiments, the calibration circuitry 130 generates the average signal A1 according to the multiple comparisons associated with the signals S1 and S2 and performs a calibration operation according to the average signal A1 to generate the control signal SC for controlling the DAC circuit 122.
In some embodiments, the calibration circuitry 130 includes a comparator circuit 131, an averaging circuit 132, a polarity determination circuit 133, and a processing circuit 134.
Two input terminals of the comparator circuit 131 are coupled to the output terminals O1 and O2, respectively. The comparator circuit 131 compares the signals S1 and S2 for a predetermined period T1 to generate a plurality of comparison signals CO 1. In some embodiments, the comparator circuit 131 may be a current comparator. In some embodiments, the comparator circuit 131 may be an analog-to-digital converter. The above embodiments are for illustration and the disclosure is not limited thereto.
The averaging circuit 132 averages a plurality of comparison signals CO1 to generate an average signal a 1. The polarity determination circuit 133 determines whether the average signal a1 is greater than 0 to generate a calibration signal SCA. The processing circuit 134 receives the calibration signal SCA and performs a calibration operation according to the calibration signal SCA to generate a corresponding control code CC. In some embodiments, the polarity determining circuit 133 can be implemented by a comparator circuit, but the disclosure is not limited thereto.
During the whole test process, the input pattern SIP is set to two opposite patterns (such as the first pattern and the second pattern in fig. 1), and two sets of control codes CC are generated through the above operations. The processing circuit 134 further generates the aforementioned control signal SC according to the two sets of control codes CC.
In some embodiments, the processing circuit 134 includes a calibration circuit 134A and a control circuit 134B. The calibration circuit 134A performs a calibration operation according to the calibration signal SCA to generate the corresponding control code CC. In some embodiments, the calibration operation may be a gradual approximation method or a binary search method, but the disclosure is not limited thereto. The control circuit 134B generates the control signal SC according to the two sets of control codes CC.
In some embodiments, the calibration circuit 134A and/or the control circuit 134B may be implemented by a digital signal processing circuit, one or more logic circuits, and/or a processing circuit executing a finite state machine, etc., but the disclosure is not limited thereto.
By arranging the input pattern SIP and the correction circuitry 130, the control signal SC can be used to correct circuit offset in the DAC device 100 and compensate for timing errors and amplitude errors of the analog output SOUT. The relevant description here will be explained later with reference to fig. 3.
Fig. 2 is a circuit schematic diagram illustrating DAC circuits 121 and 122 of fig. 1 according to some embodiments of the present disclosure. In this example, N is set to 6, M is set to 4, and LSB is encoded in binary code and MSB is encoded in thermal code. Thus, the DAC circuit 122 includes 15 sets of unit circuits (cells) 122-0 to 122-14, wherein the 15 sets of unit circuits 122-0 to 122-14 have the same configuration.
Taking the unit circuit 122-0 as an example, the unit circuit 122-0 includes a plurality of current source circuits 201-208 and a switching circuit 210. Current source circuit 201 provides current 56I. The current source circuits 202-208 sequentially provide currents of 0.125I, 4I, …, and 8I, and further include a plurality of switches T0-T6, respectively, for selectively turning on according to the control signal SC to adjust the current outputted by the unit circuit 122-0. For example, the switches T0-T6 are controlled by bits C0-C6 of the control signal SC, respectively. When one of the switches T0-T6 is turned on, a corresponding one of the currents 8I, 4I, …, 0.125I can be transmitted to the switching circuit 210. When all of the switches T0-T6 are turned on, all of the currents 8I, 4I, …, 0.125I can be transferred to the switching circuit 210.
The switching circuit 210 directs the current in the current source circuits 201-208 to the output terminal O1 or O2 according to the input pattern SIP to form a signal S1 or S2. For example, the switching circuit 210 includes switches M1-M2. The switch M1 is coupled between the output terminal O1 and the current source circuits 201-208, and is turned on according to the input pattern SIP. The switch M2 is coupled between the output terminal O2 and the current source circuits 201-208, and is turned on according to the switching signal SS.
Furthermore, the DAC circuit 121 includes a plurality of current source circuits 211-217 and a plurality of switching circuits 218. A plurality of current source circuits 211-216 correspond to DAC 121A and sequentially provide currents 32I, 16I, …, and I. The current source circuit 217 corresponds to the DAC121B, which supplies a current I. The plurality of switching circuits 218 are respectively disposed corresponding to the plurality of current source circuits 211 to 217, and each of the switching circuits 218 has the same circuit configuration.
Each switching circuit 218 directs a current of a corresponding one of the current source circuits 211-217 to the output terminal O1 or O2 according to the input pattern SIP to form a signal S1 or S2. Taking the switching circuit 218 corresponding to the current source circuit 211 as an example, the switching circuit 218 includes switches M3 to M4. The switch M3 is coupled between the output terminal O1 and the current source circuit 211, and is turned on according to the switching signal SS. The switch M4 is coupled between the output terminal O2 and the current source circuit 211, and is turned on according to the input pattern SIP. When the switch M3 is turned on, the current of the current source circuit 211 is directed to the output terminal O1. Conversely, when the switch M4 is turned on, the current of the current source circuit 211 is directed to the output terminal O2. Accordingly, the arrangement of the remaining switching circuits 218 and the current source circuits 212 to 217 can be understood, and thus, the description thereof is not repeated.
Reference is also made to fig. 1-2 for describing the operation of the calibration circuitry 130. Ideally, the current of any one of the unit circuits 122-0 to 122-14 (hereinafter, IMSB) should be the same as the sum of all the currents of the current source circuits 211 to 216 (hereinafter, ILSB) and the current of the current source circuit 217 (hereinafter, IUSB). That is, IMSB ═ ILSB + IUSB.
However, due to non-idealities such as circuit offsets, there is actually an error between the IMSB and ILSB + IUSB, and the correction circuitry 130 is used to eliminate this error.
As previously described, the correction circuitry 130 may generate the control signal SC to correct for circuit offsets in the DAC device 100. For ease of understanding, the following operations illustrate the operation of the correction circuitry 130 with respect to the correction unit circuit 122-0.
In some embodiments, when calibrating the unit circuit 122-0, all of the remaining unit circuits 122-1 to 122-14 can be turned off. Alternatively, in some embodiments, when calibrating the unit cell 122-0, half of the current of the unit cells 122-1 to 122-7 can be directed to the output terminal O1, and half of the current of the unit cells 122-8 to 122-14 can be directed to the output terminal O2. For ease of understanding, the following description will be made by taking as an example that the remaining unit circuits 122-1 to 122-14 can all be turned off.
As shown in fig. 1, in the first operation, the input pattern SIP is set to "1110", … (i.e., the first pattern in fig. 1) during the predetermined period T1. In the first pattern, the proportion of the number occupied by the logical value 1 is about 75%, and the proportion of the number occupied by the logical value 0 is about 25%. In response to the input pattern SIP, the switching signal SS is set to "0001", … for a predetermined period T1. In the switching signal SS, the ratio of the number of logical values 1 is about 25%, and the ratio of the number of logical values 0 is about 75%.
In response to the input pattern SIP and the switching signal SS, the switching circuits 210 and 218 are turned on continuously for a predetermined period T1. Thus, the currents IMSB, ILSB and IUSB are respectively directed to different output terminals O1 and O2 to form signals S1 and S2 corresponding to the first pattern at the output terminals O1 and O2. During a predetermined period T1, the comparator circuit 131 continuously compares the signal S1 with the signal S2 to generate a plurality of comparison signals CO1 corresponding to the first pattern. Then, a corresponding set of control codes CC (hereinafter referred to as control codes C1) can be generated by the operations of the averaging circuit 132, the polarity determining circuit 133 and the processing circuit 134.
As described previously, when the input pattern SIP is set to the first pattern, the logical value 1 corresponds to 75% and the logical value 0 corresponds to 25%. Under this condition, as shown in FIG. 2, about 75% of the current of the unit circuit 122-0 is directed to the output terminal O1 through the switch M1, and about 25% of the current source circuits 211-217 is directed to the output terminal O1 through the corresponding switch circuits 218, so as to form the signal S1 corresponding to the first pattern. Similarly, about 25% of the current of the unit circuit 122-0 is directed to the output terminal O2 through the switch M2, and about 75% of the current source circuits 211-217 is directed to the output terminal O2 through the corresponding switching circuits 218, so as to form the signal S2 corresponding to the first pattern. Corresponding to the control code C1, the above relationship can be derived as the following equation (1) in the steady state:
0.75×IMSB(C1)+0.25×(ILSB+IUSB)＝
0.25×IMSB(C1)+0.75×(ILSB+IUSB)+IOFFSET
→IMSB(C1)＝ILSB+IUSB+2×IOFFSET…(1)
where IMSB (C1) is the current value generated by the unit circuit 122-0 according to the control code C1, IOFFSET is the equivalent input current offset additionally introduced by the correction circuitry 130, i.e. the equivalent input current offset generated by the addition of the correction circuitry 130.
In some embodiments, the control circuit 134B may record the control code C1 and enter a second operation. In the second operation, during the predetermined period T1, the input pattern SIP is set to "0001", … (i.e. the second pattern in fig. 1), wherein the first pattern is opposite to the second pattern. In the second pattern, the percentage of the number occupied by the logic value 1 is about 25%, and the percentage of the number occupied by the logic value 0 is about 75%. In response to this input pattern SIP, the switching signal SS is set to "1110", …. Wherein the proportion of the number of logic values 1 is about 75%, and the proportion of the number of logic values 0 is about 25%.
Similar to the first operation, the output O1 and the output O2 form the signal S1 and the signal S2 corresponding to the second pattern in response to the input pattern SIP and the switching signal SS. Then, another set of corresponding control codes CC (hereinafter referred to as control codes C2) is generated by the related operations of the comparator circuit 131, the averaging circuit 132, the polarity determination circuit 133 and the processing circuit 134.
As described previously, in the second pattern, the number of logical values 1 corresponds to a proportion of 25%, and the number of logical values 0 corresponds to a proportion of 75%. Under this condition, about 25% of the current of the unit circuit 122-0 is directed to the output terminal O1 through the switch M1, and about 75% of the current source circuits 211-217 is directed to the output terminal O1 through the corresponding switching circuits 218, so as to form the signal S1 corresponding to the second pattern. Similarly, about 75% of the current of the unit circuit 122-0 is directed to the output terminal O2 through the switch M2, and about 25% of the current source circuits 211-217 is directed to the output terminal O2 through the corresponding switching circuits 218, so as to form the signal S2 corresponding to the second pattern. Corresponding to the control code C2, the above relationship can be derived as the following equation (2) in the steady state:
0.25×IMSB(C2)+0.75×(ILSB+IUSB)＝
0.75×IMSB(C2)+0.25×(ILSB+IUSB)+IOFFSET
→ILSB+IUSB＝IMSB(C2)+2×IOFFSET…(2)
here, IMSB (C2) represents the current value generated by the unit circuit 122-0 according to the control code C2.
Accordingly, the control circuit 133B subtracts equation (2) from equation (1) to obtain equation (3), where ILSB and IUSB are the corrected target current values. Thus, the control circuit 134B averages the control code C1 with the control code C2 to generate the control signal SC.
[IMSB(C1)+IMSB(C2)]/2＝ILSB+IUSB…(3)
→SC＝(C1+C2)/2
According to equation (3), the current of the unit circuit 122-0 in response to the control signal SC may be represented as follows:
IMSB(SC)＝IMSB[(C1+C2)/2]
＝[IMSB(C1)+IMSB(C2)]/2
＝ILSB+IUSB
as can be seen from the above equation, the unit circuit 122-0 is not affected by the equivalent input current offset generated by the correction circuitry 130, so the control signal SC generated by the correction circuitry 130 can make IMSB equal to ILSB + IUSB. In this way, the same operations as described above are repeated to generate the corresponding control signals SC for the remaining unit circuits 122-1 to 122-14.
The various circuit arrangements described above are for example purposes and the disclosure is not so limited. For example, in some embodiments, the DAC device 100 may further include a resistive load (not shown) coupled to the output terminals O1 and O2 to output the analog output SOUT as a voltage signal. In this example, the comparator circuit 131 may be implemented by a voltage comparator circuit.
The arrangement of the first pattern and the second pattern in fig. 1 is for example, and the disclosure is not limited thereto. Various input patterns SIP with different numbers of logic values 1 and 0 are all covered by the present disclosure.
Fig. 3 is a waveform diagram of the analog output SOUT of fig. 1 and the analog output of the related art, drawn according to some embodiments of the present disclosure. Before correction, as shown by the waveform 301A or 301B, there exists an amplitude error and a timing error between the analog output SOUT before correction and the ideal waveform. In some related art, a technique of "dc correction" is used to correct the DAC circuit. In these techniques, a dc signal is directly inputted to the input terminal of the DAC circuit for calibration. In this case, the output terminal of the DAC circuit (e.g., the output terminal O1 or O2) also outputs a dc signal. In these techniques, although the amplitude error between the analog output SOUT and the ideal waveform can be eliminated, the timing error cannot be eliminated, as shown by the waveforms 302A or 302B. In addition, in the above-mentioned techniques, if the output terminal is coupled to an inductive load (such as a transformer, etc.), an additional switch is required to cut off the output terminal and the inductive load to generate the dc signal for calibration. Therefore, unnecessary area waste and excessive parasitic capacitance will be introduced.
In contrast to the above-mentioned techniques, in some embodiments of the present disclosure, by inputting a toggle (toggle) signal (e.g., the input pattern SIP) to the DAC apparatus 100, various errors at different times can be eliminated. For example, as shown in the waveforms 303A or 303B, the amplitude error or timing error between the analog output SOUT and the ideal waveform can be eliminated. The total amount of current of the analog output SOUT corresponding to the waveform 303A is equal to the total amount of current of the ideal waveform. That is, the area a1 corresponds to the sum of 2 areas a2, wherein the sum of 2 areas a2 corresponds to the timing error amount. Alternatively, the total amount of current of the analog output SOUT corresponding to the waveform 303B is equal to the total amount of current of the ideal waveform. That is, the area A3 corresponds to the sum of 2 areas a4, wherein 2 areas a4 correspond to the timing error amount. In addition, compared to the "dc calibration" technique, in some embodiments of the present disclosure, the output of the DAC device 100 is a jump signal. Thus, the DAC device 100 may be connected to an inductive load without using additional switches.
Fig. 4 is a flow chart of a
In operation S410, the input pattern SIP is set to the first pattern to generate signals S1 and S2 corresponding to the first pattern.
In operation S420, the signals S1 and S2 corresponding to the first pattern are compared to generate an average signal A1 corresponding to the first pattern.
In operation S430, the input pattern SIP is set to a second pattern to generate signals S1 and S2 corresponding to the second pattern, wherein the second pattern is opposite to the first pattern.
In operation S440, the signals S1 and S2 corresponding to the second pattern are compared to generate an average signal A1 corresponding to the second pattern.
In operation S450, a calibration operation is performed according to two average signals a1 corresponding to the first pattern and the second pattern to generate a control signal SC.
The above operations can be described with reference to the embodiments of fig. 1 to 3, and thus, the description is not repeated. The operations of the
In summary, some embodiments of the present disclosure provide a DAC device and a calibration method thereof, which can calibrate the circuit offset in the DAC device by means of input pattern and averaging of dc imbalance (i.e., the number of logic values 1 is different from the number of logic values 0), so as to improve the problems of amplitude error and timing error.
Although the present disclosure has been described with reference to the above embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the disclosure, and therefore, the scope of the disclosure is to be determined by the appended claims.