阅读说明：本技术 驱动对象开关的驱动电路 (Drive circuit for driving object switch ) 是由 渡邉一范 于 2019-01-11 设计创作，主要内容包括：驱动电路(Dr)对相互并联连接的多个驱动对象开关(SW1～SW3)进行驱动。驱动对象开关具有第一主端子、第二主端子以及主控制端子,通过使主控制端子与第二主端子的电位差在阈值电压以上,允许电流在第一主端子与第二主端子之间流通。各驱动对象开关中的至少两个驱动对象开关的阈值电压彼此不同。对于各驱动对象开关,驱动电路包括电气路径(Loff1、Loff2、Ldis2、Ldis3),该电气路径从第二主端子或者具有比第二主端子的电位低的负电压的负电压源(57)电连接到主控制端子。对于各电气路径,电气路径的阻抗成为使由于经由驱动对象开关的寄生电容流入电气路径的电荷而上升的上述电位差低于阈值电压的阻抗。(A drive circuit (Dr) drives a plurality of switches (SW 1-SW 3) to be driven, which are connected in parallel with each other. The switch to be driven has a first main terminal, a second main terminal, and a main control terminal, and allows a current to flow between the first main terminal and the second main terminal when a potential difference between the main control terminal and the second main terminal is equal to or higher than a threshold voltage. Threshold voltages of at least two of the drive target switches are different from each other. For each of the drive object switches, the drive circuit includes an electrical path (Loff1, Loff2, Ldis2, Ldis3) electrically connected from the second main terminal or a negative voltage source (57) having a negative voltage lower than the potential of the second main terminal to the main control terminal. The impedance of the electric path is such that the potential difference, which is increased by the electric charge flowing into the electric path through the parasitic capacitance of the switch to be driven, becomes lower than the threshold voltage for each electric path.)

1. A drive circuit (Dr) for driving an object switch,

drives a plurality of switches (SW 1-SW 3) to be driven connected in parallel,

the drive-target switch has a first main terminal, a second main terminal, and a main control terminal, and is set to an on state in which a current is allowed to flow between the first main terminal and the second main terminal when a potential difference between the main control terminal and the second main terminal is equal to or greater than a threshold voltage, and is set to an off state in which a current is prevented from flowing from the first main terminal to the second main terminal when the potential difference is lower than the threshold voltage,

the threshold voltages of at least two of the plurality of the drive object switches are different from each other,

for the plurality of the drive object switches, respectively including an electrical path (Loff1, Loff2, Ldis2, Ldis3) electrically connected to the main control terminal from the second main terminal or a negative voltage source (57) having a negative voltage lower than the potential of the second main terminal,

the impedance of each of the electric paths is an impedance that makes the potential difference, which rises due to the electric charge flowing into the electric path via the parasitic capacitance of the drive target switch, lower than the threshold voltage.

2. The drive circuit of driving an object switch according to claim 1,

the impedance of the electrical path connected to the main control terminal of the drive target switch (SW1) having the lowest threshold voltage among the plurality of drive target switches is lower than the impedance of the electrical path connected to the main control terminal of the other drive target switch (SW 2).

3. The drive circuit of driving an object switch according to claim 2,

the electrical path has an open hold path (Loff1, Loff2) that shorts the second main terminal or the negative voltage source with the main control terminal,

each of the off hold paths has an off hold switch (55A, 55B) which is turned on to electrically connect the second main terminal or the negative voltage source with the main control terminal, and which is turned off to electrically block the second main terminal or the negative voltage source from the main control terminal,

the distance between the main control terminal of the drive target switch (SW1) having the lowest threshold voltage among the plurality of drive target switches and the off hold switch (55A) on the off hold path (Loff1) connected to the main control terminal is shorter than the distance between the main control terminal of the other drive target switch (SW2) and the off hold switch (55B) on the off hold path (Loff2) connected to the main control terminal.

4. The drive circuit of driving an object switch according to claim 3,

includes a drive control unit (56) for driving the open hold switches on each of the open hold paths,

the off hold switch on the off hold path connected to the main control terminal of the lowest switch to be driven is disposed outside the drive control unit, and the off hold switch on the off hold path connected to the main control terminal of the other switch to be driven is incorporated in the drive control unit.

5. The drive circuit of driving an object switch according to claim 3,

includes a drive control unit (56) for driving the open hold switches on each of the open hold paths,

each of the off hold switches is built in the drive control section,

the distance between the main control terminal of the lowest switch to be driven and the drive control unit is shorter than the distance between the main control terminal of the other switch to be driven and the drive control unit.

6. The drive circuit of driving an object switch according to claim 2,

the electrical path has:

an open hold path (Loff1, Loff2) that shorts the second main terminal or the negative voltage source with the main control terminal; and

a discharge path (Ldis1, Ldis2) connecting the second main terminal or the negative voltage source with the main control terminal and having a higher impedance than the open hold path,

each of the off hold paths has an off hold switch (55A, 55B) which is turned on to electrically connect the second main terminal or the negative voltage source with the main control terminal, and which is turned off to electrically block the second main terminal or the negative voltage source from the main control terminal,

includes a drive control unit (56) for driving the open hold switches on each of the open hold paths,

the off hold switch on the off hold path connected to the main control terminal of the lowermost switch to be driven is incorporated in the drive control unit, and the off hold switch on the off hold path connected to the main control terminal of the other switch to be driven is disposed outside the drive control unit,

the distance between the main control terminal of the lowest switch to be driven and the drive control unit is shorter than the distance between the main control terminal of the other switch to be driven and the drive control unit,

an impedance of the discharge path (Ldis1) connected to the main control terminal of the lowermost drive-target switch is lower than an impedance of the discharge path (Ldis2) connected to the main control terminals of the other drive-target switches.

7. The drive circuit of driving an object switch according to claim 2,

the electrical path has an open hold path (Loff1, Loff2) that shorts the second main terminal or the negative voltage source with the main control terminal,

each of the off hold paths has an off hold switch (55A, 55B) which is turned on to electrically connect the second main terminal or the negative voltage source with the main control terminal, and which is turned off to electrically block the second main terminal or the negative voltage source from the main control terminal,

an on-resistance of the off hold switch (55A) on the off hold path (Loff1) connected to the main control terminal of the drive target switch having the lowest threshold voltage among the plurality of drive target switches is smaller than an on-resistance of the off hold switch (55B) on the off hold path (Loff2) connected to the main control terminal of the other drive target switch.

8. The drive circuit of driving an object switch according to claim 2,

the electrical path has an open hold path (Loff1, Loff2) that shorts the second main terminal or the negative voltage source with the main control terminal,

each of the off hold paths has an off hold switch (55A, 55B) which is turned on to electrically connect the second main terminal or the negative voltage source with the main control terminal, and which is turned off to electrically block the second main terminal or the negative voltage source from the main control terminal,

when the off hold switch (55A) on the off hold path (Loff1) connected to the main control terminal of the drive target switch having the lowest threshold voltage among the plurality of drive target switches is set to a low-side switch, and the off hold switch (55B) on the off hold path (Loff2) connected to the main control terminal of another drive target switch is set to a high-side switch, the gate voltage of the low-side switch in the on state is higher than the gate voltage of the high-side switch in the on state.

9. The drive circuit of driving an object switch according to claim 2,

the drive control unit (56) is provided with a first switch (SW1) as a drive target switch having a characteristic of minimum on-resistance in a low current region smaller than a predetermined current (I alpha) among the plurality of drive target switches, and a second switch (SW2) as a drive target switch having a characteristic of minimum on-resistance in a high current region equal to or larger than the predetermined current, the drive control unit (56) switches the first switch to an on state after the second switch is initially switched to the on state,

among the plurality of drive target switches, the drive target switch having the lowest threshold voltage is the second switch, and the other drive target switches are the first switches.

10. The drive circuit of driving an object switch according to claim 2,

the drive control unit (56) is provided with a first switch (SW1) as a drive target switch having a characteristic of minimum on-resistance in a low current region smaller than a predetermined current (I alpha) and a second switch (SW2) as a drive target switch having a characteristic of minimum on-resistance in a large current region equal to or larger than the predetermined current, wherein the drive control unit (56) switches the second switch to an off state after the first switch is initially switched to the off state,

among the plurality of drive target switches, the drive target switch having the lowest threshold voltage is the second switch, and the other drive target switches are the first switches.

11. The drive circuit of driving an object switch according to claim 2,

the electric path connected to the main control terminal of the drive object switch (SW1) having the lowest threshold voltage among the plurality of drive object switches has an off hold path (Loff1) that short-circuits the second main terminal or the negative voltage source to the main control terminal, and the electric path connected to the main control terminal of the other drive object switch (SW2) has a discharge path (Ldis2) that connects the second main terminal or the negative voltage source to the main control terminal and has a higher impedance than the off hold path, and does not have the off hold path.

Technical Field

The present invention relates to a drive circuit for driving an object switch.

Background

Conventionally, as described in patent document 1, for example, a switch such as a MOSFET or an IGBT having a first main terminal, a second main terminal, and a main control terminal is known. When the potential difference between the main control terminal and the second main terminal is equal to or higher than the threshold voltage, the switch is turned on to allow a current to flow between the first main terminal and the second main terminal. On the other hand, when the potential difference is lower than the threshold voltage, the switch is turned off to prevent the current from flowing from the first main terminal to the second main terminal.

Disclosure of Invention

When the switch is turned off, electric charge can be supplied to the main control terminal through the parasitic capacitance of the switch. In this case, the potential difference between the main control terminal and the second main terminal is equal to or greater than the threshold voltage, and the switch is maintained in the off state, but the switch is erroneously switched to the on state, that is, the switch is automatically turned on. In order to solve the above problem, the drive circuit includes an electrical path electrically connected from the second main terminal or a negative voltage source having a negative voltage lower than the potential of the second main terminal to the main control terminal.

As a switch driving circuit, a circuit for driving a plurality of switches connected in parallel to each other is known. In this case, for the plurality of switches, the second main terminal or the negative voltage source is electrically connected to the main control terminal through an electrical path, respectively. Here, there are cases where the threshold voltages of at least two of the plurality of switches are different from each other. A switch with a lower threshold voltage is more likely to turn on automatically than a switch with a higher threshold voltage. Therefore, a driving circuit for driving a plurality of switches connected in parallel to each other needs a configuration for reliably suppressing the automatic conduction.

The invention provides a driving circuit of a switch to be driven, which can suppress the occurrence of automatic conduction.

A drive circuit for a switch to be driven according to the present invention drives a plurality of switches to be driven, which are connected in parallel with each other, the switch to be driven having a first main terminal, a second main terminal, and a main control terminal, the switch to be driven being in an on state in which a current is allowed to flow between the first main terminal and the second main terminal by setting a potential difference between the main control terminal and the second main terminal to be equal to or greater than a threshold voltage, the switch to be driven being in an off state in which the current is prevented from flowing from the first main terminal to the second main terminal by setting the potential difference to be lower than the threshold voltage, the threshold voltages of at least two switches to be driven being different from each other, and the plurality of switches to be driven including, respectively, an electrical path electrically connecting the second main terminal or a negative voltage source having a negative voltage lower than the potential of the second main terminal to be driven being electrically connected from the second main terminal to the negative voltage source The impedance of the electric path among the plurality of electric paths to the main control terminal is such that the potential difference that increases due to the electric charge flowing into the electric path through the parasitic capacitance of the drive target switch is lower than the threshold voltage.

In the present invention, each of the plurality of switches to be driven connected in parallel to each other includes an electrical path electrically connected from the second main terminal or a negative voltage source having a negative voltage lower in potential than the second main terminal to the main control terminal. Further, the impedance of the electric path is such that the potential difference, which is increased by the electric charge flowing into the electric path through the parasitic capacitance of the switch to be driven, becomes lower than the threshold voltage with respect to the plurality of electric paths. Therefore, even when the threshold voltages of at least two of the plurality of drive-target switches are different from each other, the occurrence of the automatic turn-on can be suppressed.

Drawings

The above objects, other objects, features and advantages of the present invention will become more apparent with reference to the accompanying drawings and the following detailed description. The drawings are as follows.

Fig. 1 is an overall configuration diagram of a control system of a rotating electric machine according to a first embodiment.

Fig. 2 is a diagram showing current-voltage characteristics of the switch.

Fig. 3 is a perspective view showing a partial structure of the inverter.

Fig. 4 is a perspective view showing a module with a built-in switch.

Fig. 5 is a diagram showing a structure of a module.

Fig. 6 is a diagram showing a configuration of a driving circuit.

Fig. 7 is a flowchart for explaining a driving method of the off hold switch.

Fig. 8 is a flowchart showing transition of the gate voltage and the like of the second switch, which is the IGBT.

Fig. 9 is a flowchart showing transition of the gate voltage and the like of the first switch, which is the MOSFET.

Fig. 10 is a plan view showing a part of the control board.

Fig. 11 is a diagram showing a configuration of a drive circuit according to modification 1 of the first embodiment.

Fig. 12 is a diagram showing a cross-sectional structure of the control board according to the first embodiment.

Fig. 13 is a diagram showing a cross-sectional structure of a control board according to modification 2 of the first embodiment.

Fig. 14 is a plan view showing a part of a control board according to the second embodiment.

Fig. 15 is a plan view showing a part of a control board according to the third embodiment.

Fig. 16 is a plan view showing a part of a control board according to the fourth embodiment.

Fig. 17 is a plan view showing a part of a control board according to the fifth embodiment.

Fig. 18 is a diagram showing a configuration of a drive circuit according to the sixth embodiment.

Fig. 19 is a flowchart showing a driving method of the first and second switches and the first and second off hold switches according to the seventh embodiment.

Fig. 20 is a diagram showing a configuration of a drive circuit according to the eighth embodiment.

Fig. 21 is a diagram showing a configuration of a drive circuit according to the ninth embodiment.

Fig. 22 is a plan view showing a part of a control board according to another embodiment.

Fig. 23 is a perspective view showing a partial structure of an inverter according to another embodiment.

Fig. 24 is a perspective view showing a module according to another embodiment.

Detailed Description

< first embodiment >

Hereinafter, a first embodiment of a drive circuit according to the present invention will be described with reference to the drawings. The drive circuit of the present embodiment constitutes a control system of the rotating electric machine.

As shown in fig. 1, the control system includes a dc power supply 10, an inverter 20 as a power converter, a rotating electric machine 30, and a control device 40. The rotating electrical machine 30 is, for example, an in-vehicle main unit. The rotating electric machine 30 is electrically connected to the dc power supply 10 via the inverter 20. In the present embodiment, the rotating electrical machine 30 has a three-phase structure. As the rotating electrical machine 30, for example, a permanent magnet synchronous machine can be used. The dc power supply 10 is a battery having a terminal voltage of 100V or more, for example. Specifically, the dc power supply 10 is a secondary battery such as a lithium ion battery or a nickel metal hydride battery, for example. Further, the capacitor 11 is connected in parallel with the dc power supply 10.

Inverter 20 includes an upper arm switch unit 20H and a lower arm switch unit 20L corresponding to each other. In each phase, upper arm switch 20H and lower arm switch 20L are connected in series. In each phase, a first end of a winding 31 of each phase of the rotating electric machine 30 is connected to a connection point of the upper arm switch portion 20H and the lower arm switch portion 20L. The 2 nd ends of the windings 31 of the respective phases are connected at a neutral point.

Each of the switch sections 20H and 20L includes a parallel connection body of a first switch SW1 and a second switch SW 2. The first switch SW1 and the second switch SW2 correspond to drive target switches. In each phase, the positive side of the dc power supply 10 is connected to the first main terminal of each of the first switch SW1 and the second switch SW2 of the upper arm switch unit 20H. In each phase, the negative side of the dc power supply 10 is connected to the second main terminal of each of the first switch SW1 and the second switch SW2 of the lower arm switch unit 20L. In each phase, the first main terminals of the first switch SW1 and the second switch SW2 of the lower arm switch section 20L are connected to the second main terminals of the first switch SW1 and the second switch SW2 of the upper arm switch section 20H.

In the present embodiment, the first switch SW1 is an N-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) as an SiC device. Therefore, in the first switch SW1, the second main terminal is a source, the first main terminal is a drain, and the main control terminal is a gate. The second switch SW2 is an IGBT (Insulated Gate Bipolar Transistor) as a Si device. Therefore, in the second switch SW2, the second main terminal is an emitter, the first main terminal is a collector, and the main control terminal is a gate. Further, a flywheel diode is connected in antiparallel with each second switch SW 2. Each first switch SW1 includes a body diode. A freewheeling diode may also be connected in anti-parallel with each first switch SW 1.

In the present embodiment, the reason why each switch unit is formed by a parallel connection body of an IGBT and a MOSFET is as follows: the loss in the small current region is reduced by causing a current to flow through a MOSFET having a lower on-resistance in the small current region. Hereinafter, description will be given with reference to fig. 2. In fig. 2, a chain line indicates voltage-current characteristics of a drain current Ids and a drain voltage Vds between the drain and the source of the MOSFET, and a broken line indicates voltage-current characteristics of a collector current Ice and a collector-emitter voltage Vce of the IGBT. The solid line indicates voltage-current characteristics when an IGBT and a MOSFET are used in parallel.

As shown in fig. 2, in a small current region where the current is smaller than the predetermined current Ith, the drain-source voltage Vds corresponding to the drain current Ids is lower than the collector-emitter voltage Vce corresponding to the collector current Ice. That is, in a small current region, the on resistance of the MOSFET is smaller than the on resistance of the IGBT. Therefore, in a small current region, a large amount of current flows through the MOSFETs and the MOSFETs in the IGBTs connected in parallel to each other. On the other hand, in a large current region where the current is larger than the predetermined current Ith, the voltage Vce between the collector and the emitter corresponding to the collector current Ice is lower than the voltage Vds between the drain and the source corresponding to the drain current Ids. That is, in the large current region, the on resistance of the IGBT is smaller than the on resistance of the MOSFET. Therefore, in the large current region, a large amount of current flows through the MOSFETs and the IGBTs connected in parallel to each other.

Further, the threshold voltage Vth2 of the second switch SW2 is set higher than the threshold voltage Vth1 of the first switch SW 1. In the present embodiment, the maximum value of the collector current Ice that can flow through the second switch SW2 is set to be larger than the maximum value of the drain current Ids that can flow through the first switch SW 1.

Returning to the description of fig. 1, the control device 40 drives the inverter 20 to control the control amount of the rotating electrical machine 30 to its command value. The control amount is, for example, torque. The controller 40 outputs drive signals corresponding to the switches SW1 and SW2 to the drive circuits Dr provided individually in the switches 20H and 20L to drive the switches SW1 and SW2 of the inverter 20. For example, the control device 40 generates the drive signals corresponding to the respective drive circuits Dr through PWM processing based on comparison of the magnitudes of three-phase command voltages whose phases are separated by an electrical angle of 120 ° with carrier signals such as triangular waves. The drive signal is any one of an on command indicating an on state of the switch and an off command indicating an off state. In the present embodiment, the on command is represented by a signal of logic H, and the off command is represented by a signal of logic L. In each phase, the drive signal on the upper arm side and the corresponding drive signal on the lower arm side are alternately turned on commands. Therefore, in each phase, the switches SW1 and SW2 of the upper arm switch unit 20H and the switches SW1 and SW2 of the lower arm switch unit 20L are alternately turned on

The inverter 20 will be further described with reference to fig. 3 to 6. Fig. 3 is a schematic diagram showing a plurality of sets of the first switch SW1, one set of the first switch SW1, and one set of the second switch SW2 in the second switch SW2 included in the inverter 20, and the peripheral structures thereof.

The inverter 20 includes a control substrate 41, a first module 101 having a first switch SW1 built therein, and a second module 102 having a second switch SW2 built therein. In the present embodiment, the control substrate 41 is, for example, a printed substrate, and is a multilayer substrate including an outer layer and an inner layer. The outer layer is a first surface of the control substrate 41 and a second surface that is a back surface of the first surface. The inner layer is a layer sandwiched between a pair of outer layers.

The terminals of the first module 101 are mechanically and electrically connected to the control board 41 by soldering or the like. The first module 101 includes: the battery module includes a main body portion incorporating a first switch SW1, a flywheel diode and a first thermal diode, a plurality of terminals protruding from the main body portion, and a plurality of power terminals protruding from the main body portion. The plurality of terminals includes a gate terminal G1 of the first switch SW1, a source terminal KE1, an anode terminal a1 of the first thermal diode, a cathode terminal K1 of the first thermal diode, and a sense terminal SE 1. The sense terminal SE1 is a terminal through which a minute current related to the drain current of the first switch SW1 flows. The power terminals include a first power terminal shorted by a drain of the first switch SW1 and a second power terminal shorted by a source of the first switch SW 1.

As shown in fig. 4 and 5, the second module 102 includes: a main body portion 102a incorporating a second switch SW2, a flywheel diode, and a second thermistor DT2, a plurality of terminals protruding from the main body portion 102a, and a plurality of power terminals protruding from the main body portion 102 a. The plurality of terminals include: a gate terminal G2 of the second switch SW2, an emitter terminal KE2, an anode terminal a2 of the second thermal diode DT2, a cathode terminal K2 of the second thermal diode DT2, and a sense terminal SE 2. The sense terminal SE2 is a terminal where a minute current related to the collector current of the second switch SW2 flows. The power terminals include a first power terminal TP1 shorted by a collector of the second switch SW2 and a second power terminal TP2 shorted by an emitter of the second switch SW 2. The terminals of the second module 102 are mechanically and electrically connected to the control board 41 by soldering or the like.

The main body of each module 101, 102 is a flat rectangular parallelepiped. Taking the second module 102 as an example, the terminals K2, a2, G2, SE2, and KE2 are provided on one of a pair of opposing surfaces of the main body portion 102a so as to protrude perpendicularly therefrom. On the other side, power terminals TP1 and TP2 are provided so as to protrude perpendicularly from the surface.

The driving circuit Dr of each of the switches SW1 and SW2 will be described with reference to fig. 6.

The drive circuit Dr includes: a positive voltage source 50, a first charge switch 51A, a first charge resistor 52A, a first discharge resistor 53A, a first discharge switch 54A, and a first off hold switch 55A. In the present embodiment, a P-channel MOSFET is used as the first charge switch 51A, and an N-channel MOSFET is used as the first discharge switch 54A and the first off hold switch 55A. In the present embodiment, the source potential of the first switch SW1 is 0, and the output voltage of the positive voltage source 50 is represented by VP (> 0).

A positive voltage source 50 is connected to the source of the first charge switch 51A, and a first terminal of a first charge resistor 52A is connected to the drain of the first charge switch 51A. A gate of the first switch SW1 is connected to a second terminal of the first charging resistor 52A. A first end of the first discharge resistor 53A and a drain of the first off hold switch 55A are connected to a gate of the first switch SW 1. A second end of the first discharge resistor 53A is connected to a drain of the first discharge switch 54A. A source of a first switch SW1 is connected to a source of the first discharge switch 54A and a source of the first off hold switch 55A.

In the present embodiment, an electrical path from the gate of the first switch SW1 to the drain of the first off-hold switch 55A, between the drain and the source of the first off-hold switch 55A, and from the source of the first off-hold switch 55A to the source of the first switch SW1 is a first off-hold path Loff1 corresponding to the first switch SW 1.

In the present embodiment, an electrical path from the gate of the first switch SW1 to the drain of the first discharge switch 54A via the first discharge resistor 53A, between the drain and the source of the first discharge switch 54A, and from the source of the first discharge switch 54A to the source of the first switch SW1 is a first discharge path Ldis1 corresponding to the first switch SW 1. A portion other than the first discharge switch 54A and the first discharge resistor 53A in the first discharge path Ldis1 includes a wiring pattern.

In addition, in the present embodiment, although an electrical path from the positive voltage source 50 to the gate of the first switch SW1 via the first charging switch 51A and the first charging resistor 52A is not illustrated, it corresponds to the first charging path Lch1 corresponding to the first switch SW 1. A portion of the first charging path Lch1 other than the first charging switch 51A and the first charging resistor 52A includes a wiring pattern.

The drive circuit Dr includes: a second charge switch 51B, a second charge resistor 52B, a second discharge resistor 53B, a second discharge switch 54B, and a second off hold switch 55B. In the present embodiment, a P-channel MOSFET is used as the second charge switch 51B, and an N-channel MOSFET is used as the second discharge switch 54B and the second off hold switch 55B. In the present embodiment, the emitter potential of the second switch SW2 is set to 0.

The positive voltage source 50 is connected to the source of the second charge switch 51B, and the gate of the second switch SW2 is connected to the drain of the second charge switch 51B via the second charge resistor 52B. A first end of the second discharge resistor 53B and a drain of the second off hold switch 55B are connected to a gate of the second switch SW 2. A second end of the second discharge resistor 53B is connected to a drain of the second discharge switch 54B. The gate of the second switch SW2 is connected to the source of the second discharge switch 54B and the source of the second off hold switch 55B.

In the present embodiment, an electrical path from the gate of the second switch SW2 to the drain of the second off hold switch 55B, between the drain and the source of the second off hold switch 55B, and from the source of the second off hold switch 55B to the source of the second switch SW2 is a second off hold path Loff2 corresponding to the second switch SW 2.

In the present embodiment, an electrical path from the gate of the second switch SW2 to the drain of the second discharge switch 54B via the second discharge resistor 53B, between the drain and the source of the second discharge switch 54B, and from the source of the second discharge switch 54B to the source of the second switch SW2 is a second discharge path Ldis2 corresponding to the second switch SW 2. A portion other than the second discharge switch 54B and the second discharge resistor 53B in the second discharge path Ldis2 includes a wiring pattern.

Further, in the present embodiment, although an electrical path from the positive voltage source 50 to the gate of the second switch SW2 via the second charging switch 51B and the second charging resistor 52B is not illustrated, it corresponds to the second charging path Lch2 corresponding to the second switch SW 2. A portion of the second charging path Lch2 other than the second charging switch 51B and the second charging resistor 52B includes a wiring pattern.

The drive circuit Dr includes a drive control section 56. When determining that the drive signal of first switch SW1 received from control device 40 is an on command, drive control unit 56 turns on first charge switch 51A and turns off first discharge switch 54A and first off hold switch 55A. In this case, the output voltage VP of the positive voltage source 50 is supplied to the gate of the first switch SW1, and the charging current is supplied from the positive voltage source 50 to the gate of the first switch SW 1. As a result, the gate voltage Vgs of the first switch SW1 becomes equal to or higher than the threshold voltage Vth1 of the first switch SW1, and the first switch SW1 is switched to the on state, thereby allowing a current to flow between the drain and the source of the first switch SW 1.

When determining that the acquired drive signal of first switch SW1 is an off command, drive control unit 56 turns first charge switch 51A off and first discharge switch 54A on. At this time, a discharge current flows from the gate of the first switch SW1 to the source side of the first switch SW1 via the first discharge resistor 53A and the first discharge switch 54A. As a result, the gate voltage Vgs of the first switch SW1 becomes lower than the threshold voltage Vth1, and the first switch SW1 is turned off, thereby preventing current from flowing from the drain to the source of the first switch SW 1.

When determining that the drive signal of second switch SW2 received from control device 40 is an on command, drive control unit 56 turns second charge switch 51B on and second discharge switch 54B and second off hold switch 55B off. In this case, the output voltage VP of the positive voltage source 50 is supplied to the gate of the second switch SW2, the gate voltage Vge of the second switch SW2 is equal to or higher than the threshold voltage Vth2 of the second switch SW2, and the second switch SW2 is switched to the on state, thereby allowing the current to flow from the collector to the emitter of the second switch SW 2.

When determining that the acquired drive signal of second switch SW2 is an off command, drive control unit 56 turns second charge switch 51B off and second discharge switch 54B on. In this case, the discharge current flows from the gate of the second switch SW2 to the emitter side of the second switch SW2 via the second discharge resistor 53B and the second discharge switch 54B. As a result, the gate voltage Vge of the second switch SW2 is lower than the threshold voltage Vth2, and the second switch SW2 is turned off, thereby blocking the current from flowing from the collector to the emitter of the second switch SW 2.

In the present embodiment, the logic of the drive signals of the first switch SW1 and the second switch SW2 input from the control device 40 to the drive control unit 56 is synchronized. Therefore, the first switch SW1 and the second switch SW2 are turned on and off in synchronization by the drive control unit 56.

The drive control section 56 has a function of monitoring the gate voltage Vgs of the first switch SW 1. When it is determined that the drive signal is the off command and the gate voltage Vgs of the first switch SW1 is equal to or lower than the first predetermined voltage, the drive control unit 56 turns the first off/hold switch 55A on, and otherwise performs the off/hold process of maintaining the first off/hold switch 55A off. The first predetermined voltage is set to a voltage equal to or lower than the threshold voltage Vth1 of the first switch SW1, and in the present embodiment, is set to the threshold voltage Vth 1.

The drive control unit 56 has a function of monitoring the gate voltage Vge of the second switch SW 2. When it is determined that the drive signal is an off command and the gate voltage Vge of the second switch SW2 is equal to or lower than the second predetermined voltage, the drive control unit 56 turns the second off hold switch 55B on, and otherwise performs an off hold process of maintaining the second off hold switch 55B in the off state. The second predetermined voltage is set to a voltage equal to or lower than the threshold voltage Vth2 of the second switch SW2, and in the present embodiment, is set to the threshold voltage Vth 2.

For example, as shown in fig. 7, the off hold process is a process for suppressing the switching noise generated when the switch on the lower arm side is switched to the on state from being transmitted to the gate of the switch on the upper arm side, and causing the switch on the upper arm side to be automatically turned on. In fig. 7, the second switch SW2 is exemplified as an upper arm side switch and a lower arm side switch, and also shows changes in the gate voltage of the switches. In fig. 7, the drive signal is switched to the off command at time t1, and the off hold process of the second switch SW2 on the upper arm side is started at time t 2.

The functions provided by the drive control unit 56 may be provided by software stored in a physical memory device, a computer that executes the software, hardware, or a combination thereof.

Next, a case where the first switch SW1 is more likely to be automatically turned on than the second switch SW2 will be described with reference to fig. 8 and 9.

First, the second switch SW2 will be described with reference to fig. 8. Fig. 8 (a) shows transition of the gate voltage Vge of the second switch SW2, fig. 8 (b) shows transition of the collector current Ice of the second switch SW2, and fig. 3 (c) shows transition of the collector-emitter voltage Vce of the second switch SW 2. When the gate potential is higher than the emitter potential, the gate voltage Vge is positive.

At time t1, the drive signal of the second switch SW2 is switched to the on command, and the gate voltage Vge starts to rise. Thereafter at time t2, the gate voltage Vge reaches the output voltage VP of the positive voltage source 50. Then, at time t3, the drive signal is switched to the off command, the gate voltage Vge starts to fall, and at time t4, the gate voltage Vge becomes 0. Thereafter, for example, the switch on the opposite arm side is switched to the on state, and the gate voltage Vge rises in accordance with this, in spite of the off command. However, since the threshold voltage Vth2 of the second switch SW2 is relatively high, even if the gate voltage Vge rises, the gate voltage Vge does not reach the threshold voltage Vth2 or more.

Next, the first switch SW1 will be described with reference to fig. 9. Fig. 9 (a) shows transition of the gate voltage Vgs of the first switch SW1, fig. 9 (b) shows transition of the drain Ids of the first switch SW1, and fig. 9 (c) shows transition of the voltage Vds between the drain and the source of the first switch SW 1. In addition, when the gate potential is higher than the source potential, the gate voltage Vgs is positive.

At time t1, the drive signal of the first switch SW1 is switched to an on command, and the gate voltage Vgs starts to rise. Thereafter at time t2, the gate voltage Vgs reaches the output voltage VP of the positive voltage source 50. Thereafter, at time t3, the drive signal is switched to the off command, the gate voltage Vgs starts to fall, and at time t4, the gate voltage Vgs becomes 0. Thereafter, for example, the switch on the opposite arm side is switched to the on state, and the gate voltage Vgs is increased in accordance with the on state in spite of the off command. The threshold voltage Vth1 of the first switch SW1 is lower than the threshold voltage Vth2 of the second switch SW 2. Therefore, the gate voltage Vgs reaches the threshold voltage Vth1 or more due to the rise of the gate voltage Vgs. As a result, automatic conduction of the first switch SW1 occurs.

A configuration for coping with the above problem will be described with reference to fig. 10. Fig. 10 is a view of the control board 41 viewed from the first surface. In fig. 10, the first charge switch 51A and the like are not shown.

A drive control unit 56 is provided on the first surface of the control substrate 41. On the control board 41, the terminals K1, a1, G1, SE1, and KE1 of the first module 101 are connected in a line at a position distant from the drive control unit 56. On the control board 41, the terminals K2, a2, G2, SE2, and KE2 of the second module 102 are connected in a line at a position distant from the drive control unit 56. The terminals K1, a1, G1, SE1, KE1 of the first module 101 and the terminals K2, a2, G2, SE2, KE2 of the second module 102 are connected in parallel.

On the first surface of the control substrate 41, first and second open hold switches 55A and 55B are provided between the terminals K1, a1, G1, SE1, and KE1 of the first module 101 and the terminals K2, a2, G2, SE2, and KE2 of the second module 102. The first disconnection holding switch 55A is provided on the gate terminal G1 side of the first module 101 in the first direction which is the opposing direction of the gate terminal G1 of the first module 101 and the gate terminal G2 of the second module 102. The second off hold switch 55B is provided on the gate terminal G2 side of the second module 102 in the first direction. The second off hold switch 55B is provided at a position closer to the drive controller 56 side than the first off hold switch 55A and the gate terminals G1 and G2 in a second direction which is a facing direction of the gate terminals G1 and G2 and the drive controller 56. In the present embodiment, the off hold switches 55A and 55B are separate components externally mounted.

On the first surface of the control substrate 41, a first a path 61A and a first B path 61B constituting a first off hold path Loff1 are provided. In the present embodiment, the first a path 61A and the first B path 61B are wiring patterns. The first a path 61A connects the gate terminal G1 of the first switch SW1 and the drain of the first disconnection holding switch 55A. The first B path 61B connects the source of the first open hold switch 55A and the source terminal KE1 short-circuited by the source of the first switch SW 1.

On the first surface of the control substrate 41, a first signal path 62 is provided for connecting the gate of the first off hold switch 55A and the drive control unit 56. The drive control unit 56 turns on/off the first off hold switch 55A via the first signal path 62.

On the first surface of the control board 41, a second a path 63A and a second B path 63B constituting a second off hold path Loff2 are provided. In the present embodiment, the second a path 63A and the second B path 63B are wiring patterns. The second a-path 63A connects the gate terminal G2 of the second switch SW2 and the drain of the second disconnection holding switch 55B. The second B path 63B connects the source of the second open hold switch 55B and the emitter terminal KE2 short-circuited by the emitter of the second switch SW 2.

A second signal path 64 for connecting the gate of the second off hold switch 55B and the drive control unit 56 is provided on the first surface of the control substrate 41. The drive control unit 56 turns on/off the second off hold switch 55B via the second signal path 64. In addition, when the first surface of the control substrate 41 is viewed from the front, the portion of the second signal path 64 that intersects the second a path 63A crosses the second a path 63A via the inner layer of the control substrate 41 and the via hole.

In the present embodiment, the impedance of the first off hold path Loff1 when the first off hold switch 55A is in the on state is lower than the impedance of the second off hold path Loff2 when the second off hold switch 55B is in the on state, according to the following configurations (a1) to (A3).

(A1) The distance between the gate terminal G1 of the first switch SW1 and the first off hold switch 55A is shorter than the distance between the gate terminal G2 of the second switch SW2 and the second off hold switch 55B.

(A2) The widths of the first a path 61A and the first B path 61B constituting the first open holding path Loff1 are larger than the widths of the second a path 63A and the second B path 63B constituting the second open holding path Loff 2.

(A3) The first a path 61A and the first B path 61B constituting the first open holding path Loff1 have respective lengths shorter than those of the second a path 63A and the second B path 63B constituting the second open holding path Loff 2.

In this way, in the present embodiment, the impedance of the first open hold path Loff1 of the first switch SW1 having a relatively low threshold voltage is lower than the impedance of the second open hold path Loff2 of the second switch SW2 having a relatively high threshold voltage. The smaller the impedance of the off-hold path, the degree of rise of the gate voltage is suppressed even if electric charge flows into the gate of the switch during the off-hold process. Therefore, according to the present embodiment, even if, for example, electric charges flow into the gate via the parasitic capacitance of the switch, it is possible for the first switch SW1 and the second switch SW2 to make the peak value of the gate voltage that rises due to the electric charges lower than the threshold voltage during the off-hold process. This can suppress the occurrence of automatic turning on of the first switch SW1 and the second switch SW 2.

< modification 1 of the first embodiment >

Instead of the configuration of fig. 6, the drive circuit Dr may include a negative voltage source 57 as shown in fig. 11. In fig. 11, for convenience, the same components as those shown in fig. 6 are denoted by the same reference numerals.

The negative voltage source 57 outputs a negative voltage Vn (< 0) lower than the source potential of the first switch SW1 and the emitter potential of the second switch SW 2. The sources of the first discharge switch 54A and the first off hold switch 55A are not connected to the source of the first switch SW1 but connected to the negative voltage source 57. The sources of the second discharge switch 54B and the second off hold switch 55B are not connected to the emitter of the second switch SW2 but connected to the negative voltage source 57.

The off hold path of the present embodiment will be described by taking the first switch SW1 as an example. The first off hold path Loff1 is an electrical path from the gate of the first switch SW1 to the drain of the first off hold switch 55A, between the drain and the source of the first off hold switch 55A, from the source of the first off hold switch 55A to the negative voltage source 57.

< modification 2 of the first embodiment >

As shown in fig. 12, the wiring pattern for disconnecting the holding path is not limited to the wiring pattern PT provided on the first surface 42a of the outer layer of the control substrate 41. For example, the wiring pattern of the off holding path may be configured as a parallel connection body of a wiring pattern provided on an outer layer and a wiring pattern provided on at least one inner layer of the control board 41. Fig. 13 shows an example in which the wiring patterns PTa provided on the first surface 42a and the second surface 42b of the outer layer and the wiring patterns PTb provided in the inner layer are connected in parallel via the vias 43. According to the structure shown in fig. 13, the impedance can be reduced to 1/4 as compared with the structure shown in fig. 12. In addition, fig. 12 and 13 show a combination of the gate terminal G1 and the first off hold switch 55A. The wiring pattern PT in fig. 12 corresponds to the first a path 61A in fig. 10.

< second embodiment >

Hereinafter, a second embodiment will be described focusing on differences from the first embodiment with reference to the drawings. In the present embodiment, as shown in fig. 14, the second off hold switch 55B is incorporated in the drive control unit 56. In fig. 14, for convenience, the same components as those shown in fig. 10 are denoted by the same reference numerals.

On the control substrate 41, the first off hold switch 55A is provided outside the drive control unit 56 in the same manner as in the first embodiment.

On the first surface of the control board 41, a second a path 65A and a second B path 65B constituting a second off hold path Loff2 are provided. The second a-path 65A connects the gate terminal G2 of the second switch SW2 and the drain of the second disconnection holding switch 55B. The second B path 65B connects the source of the second open hold switch 55B and the emitter terminal KE2 short-circuited by the emitter of the second switch SW 2. The respective lengths of the first a path 61A and the first B path 61B are shorter than the respective lengths of the second a path 65A and the second B path 65B. Further, the widths of the first a path 61A and the first B path 61B are larger than the widths of the second a path 65A and the second B path 65B.

According to the present embodiment, the first off hold switch 55A may be disposed near the gate terminal G1. Therefore, the first open holding path Loff1 may be made shorter than the second open holding path Loff2, and the impedance of the first open holding path Loff1 may be made smaller than the impedance of the second open holding path Loff 2.

Further, according to the present embodiment, the second off hold switch 55B is incorporated in the drive control unit 56. Therefore, the second off hold switch 55B does not need to be provided on the first surface of the control substrate 41, and therefore the configuration of the drive circuit Dr can be simplified.

< third embodiment >

Hereinafter, a third embodiment will be described focusing on differences from the second embodiment with reference to the drawings. In the present embodiment, as shown in fig. 15, the first off hold switch 55A is also incorporated in the drive control unit 56. In fig. 15, for convenience, the same components as those shown in fig. 14 are denoted by the same reference numerals.

On the first surface of the control substrate 41, a first a path 66A and a first B path 66B constituting a first off hold path Loff1 are provided. The first a path 66A connects the gate terminal G1 of the first switch SW1 and the drain of the first disconnection holding switch 55A. The first B path 66B connects the source of the first open hold switch 55A and the source terminal KE1 short-circuited by the source of the first switch SW 1.

On the first surface of the control substrate 41, a second a path 67A and a second B path 67B constituting a second off hold path Loff2 are provided. The second a path 67A connects the gate terminal G2 of the second switch SW2 and the drain of the second disconnection holding switch 55B. The second B path 67B connects the source of the second open hold switch 55B and the emitter terminal KE2 short-circuited by the emitter of the second switch SW 2. The respective lengths of the first a path 66A and the first B path 66B are shorter than the respective lengths of the second a path 67A and the second B path 67B. Further, the widths of the first a path 66A and the first B path 66B are larger than the widths of the second a path 67A and the second B path 67B.

On the control board 41, the drive control unit 56 is provided at a position close to the gate terminal G1 among the gate terminals G1 and G2. Therefore, the distance between the gate terminal G1 of the first switch SW1 and the drive control section 56 is shorter than the distance between the gate terminal G2 of the second switch SW2 and the drive control section 56.

According to the present embodiment described above, the off hold switches 55A and 55B are incorporated in the drive control unit 56, and therefore the drive circuit Dr can be further simplified.

< fourth embodiment >

Hereinafter, a fourth embodiment will be described focusing on differences from the first embodiment with reference to the drawings. In the present embodiment, as shown in fig. 16, the arrangement intervals of the terminals K1, a1, G1, SE1, and KE1 of the first module 101 and the terminals K2, a2, G2, SE2, and KE2 of the second module 102 are narrowed. Therefore, on the first surface of the control substrate 41, the off hold switch cannot be provided in the region between the terminals K1, a1, G1, SE1, KE1 of the first module 101 and the terminals K2, a2, G2, SE2, KE2 of the second module 102. Therefore, in the present embodiment, the method of arranging the off hold switch and the like on the control substrate 41 is changed. In fig. 16, for convenience, the same components as those shown in fig. 10 are denoted by the same reference numerals.

The drive control unit 56 is provided on the first surface of the control substrate 41 on the side opposite to the gate terminal G2 of the second module 102 in the second direction with the gate terminal G1 of the first module 101 interposed therebetween. The drive controller 56 is provided at a position apart from the cathode terminals K1 and K2 in the first direction. The drive control unit 56 incorporates a first off hold switch 55A.

A second off hold switch 55B is provided in the first surface of the control substrate 41 at a position apart from each of the cathode terminals K1, K2 in the first direction. On the first surface of the control substrate 41, a signal path 72 is provided for connecting the gate of the second off hold switch 55B and the drive control unit 56.

On the first surface of the control board 41, a first a path 68A and a first B path 68B constituting a first off hold path Loff1 are provided. The first a-path 68A connects the gate terminal G1 of the first switch SW1 and the drain of the first disconnection holding switch 55A. The first B path 68B connects the source of the first open hold switch 55A and the source terminal KE1 short-circuited by the source of the first switch SW 1. The first a path 68A is provided on the control substrate 41 at a position closer to the drive control unit 56 side than the gate terminal G1 of the first switch SW1 in the second direction. The first B path 68B is provided on the opposite side of the control substrate 41 in the second direction from the gate terminal G1 with the first a path 68A therebetween.

On the first surface of the control board 41, a second a path 69A and a second B path 69B constituting a second off hold path Loff2 are provided. The second a-path 69A connects the gate terminal G2 of the second switch SW2 and the drain of the second disconnection holding switch 55B. The second B path 69B connects the source of the second off hold switch 55B and the emitter terminal KE2 of the second switch SW 2. The second a path 69A is provided on the opposite side of the control substrate 41 in the second direction from the gate terminal G1 of the first switch SW1 across the gate terminal G2 of the second switch SW 2. The second B path 69B is provided in the control substrate 41 in a region between the terminals K1, a1, G1, SE1, KE1 of the first module 101 and the terminals K2, a2, G2, SE2, KE2 of the second module 102 in the second direction.

On the first surface of the control substrate 41, a first charging path Lch1, a second charging path Lch2, a first discharging path Ldis1, and a second discharging path Ldis2 are provided. In fig. 16, the switches and the like on the paths Lch1, Lch2, Ldis1, and Ldis2 are not shown.

The first discharge path Ldis1 is provided on the opposite side of the control substrate 41 from the first a path 68A across the first B path 68B. The first charging path Lch1 is provided on the opposite side of the control substrate 41 from the first B path 68B across the first discharging path Ldis 1.

The second charging path Lch2 and the second discharging path Ldis2 are provided in a region of the control substrate 41 on the opposite side of the second off hold switch 55B from the gate terminals G1 and G2 in the first direction and on the opposite side of the second off hold switch 55B from the drive control unit 56 in the first direction.

In addition, when the first surface of the control substrate 41 is viewed from the front, the portion of the signal path 72 that intersects with the second charging path Lch2, the second discharging path Ldis2, and the second a path 69A crosses over each of the paths Lch2, Ldis2, and 69A via the inner layer and the via hole of the control substrate 41. Further, when the first face of the control substrate 41 is viewed from the front, the first B path 68B is crossed by the first charging path Lch1 and the portion of the first discharging path Ldis1 that intersects with the first B path 68B via the inner layer of the control substrate 41 and the via hole.

The width of the first a-path 68A and the first B-path 68B is larger than the width of the second a-path 69A and the second B-path 69B. Thus, the impedance of the first open holding path Loff1 is lower than the impedance of the second open holding path Loff 2.

The length of the first charging path Lch1 is shorter than the length of the second charging path Lch 2. Further, the width of the wiring pattern constituting the first charging path Lch1 is larger than the width of the wiring pattern constituting the second charging path Lch 2. Thus, the impedance of the first charging path Lch1 when the first charging switch 51A is in the on state is lower than the impedance of the second charging path Lch2 when the second charging switch 51B is in the on state. This makes it possible to increase the charging speed of the gate of the first switch SW1 to be faster than the charging speed of the gate of the second switch SW2, and to increase the switching speed when the first switch SW1 is switched to the on state. As a result, switching loss can be reduced.

The length of the first discharge path Ldis1 is shorter than the length of the second discharge path Ldis 2. Further, the width of the wiring pattern constituting the first discharge path Ldis1 is larger than the width of the wiring pattern constituting the second discharge path Ldis 2. Thus, the impedance of the first discharge path Ldis1 when the first discharge switch 54A is in the on state is lower than the impedance of the second discharge path Ldis2 when the second discharge switch 54B is in the on state. This makes it possible to increase the discharge rate of the gate of the first switch SW1 to be higher than the discharge rate of the gate of the second switch SW2, and to increase the switching rate when the first switch SW1 is switched to the off state. As a result, switching loss can be reduced.

< fifth embodiment >

Hereinafter, a fifth embodiment will be described focusing on differences from the first embodiment with reference to the drawings. In the present embodiment, as shown in fig. 17, the on-resistance RonA of the first off hold switch 55A is smaller than the on-resistance RonB of the second off hold switch 55B. Thus, the impedance of the first off hold path Loff1 can be made lower than the impedance of the second off hold path Loff 2. In fig. 17, for convenience, the same components as those shown in fig. 10 are denoted by the same reference numerals. In the example shown in fig. 17, the first off hold switch 55A is larger than the second off hold switch 55B. This is generally because the larger the chip size of the component, the smaller its on-resistance.

< sixth embodiment >

Hereinafter, a sixth embodiment will be described focusing on differences from the first embodiment with reference to the drawings. In the present embodiment, as shown in fig. 18, the gate voltage VGA of the first off hold switch 55A for being turned on is higher than the gate voltage VGB of the second off hold switch 55B for being turned on. The gate voltage VGA of the first off hold switch 55A is above its threshold voltage, and the gate voltage VGB of the second off hold switch 55B is above its threshold voltage. The first off hold switch 55A corresponds to a low-side switch, and the second off hold switch 55B corresponds to a high-side switch. Note that, in fig. 18, for convenience, the same components as those shown in fig. 6 are denoted by the same reference numerals.

According to the present embodiment, the on-resistance of the first off hold switch 55A is lower than the on-resistance of the second off hold switch 55B. Therefore, the impedance of the first open holding path Loff1 can be made lower than the impedance of the second open holding path Loff 2.

If the impedance of the first off-hold path Loff1 can be made lower than the impedance of the second off-hold path Loff2, it is not always necessary to make the length of the wiring pattern of the first off-hold path Loff1 shorter than the length of the wiring pattern of the second off-hold path Loff2 or to make the width of the wiring pattern of the first off-hold path Loff1 wider than the width of the wiring pattern of the second off-hold path Loff 2.

< seventh embodiment >

Hereinafter, a seventh embodiment will be described focusing on differences from the first embodiment with reference to the drawings. In the present embodiment, the drive control unit 56 first switches the second switch SW2 to the on state and then switches the first switch SW1 to the on state. After that, the drive control unit 56 first switches the first switch SW1 to the off state, and then switches the second switch SW2 to the off state. This is to suppress as much as possible a decrease in reliability of the first switch SW1 when a state arm short circuit occurs in which the upper and lower arm switches of the inverter 20 are simultaneously in the on state. That is, the maximum value of the collector current Ice that can flow through the second switch SW2 is larger than the maximum value of the drain current Ids that can flow through the first switch SW 1. If a short circuit can be detected before the first switch SW1 is switched to the on state after the second switch SW2 is switched to the on state, the switching of the second switch SW2 to the on state can be inhibited. At this time, since the maximum value of the collector current Ice that can flow through the second switch SW2 is relatively large, a time for short circuit detection can be secured.

The effects of the present embodiment will be described with reference to fig. 19. Fig. 19 (a) shows transition of the driving state of the first switch SW1, fig. 19 (B) shows transition of the driving state of the second switch SW2, fig. 19 (c) shows transition of the driving state of the first off hold switch 55A, and fig. 19 (d) shows transition of the driving state of the second off hold switch 55B.

At time t1, the second charge switch 51B is in the on state, and the second discharge switch 54B and the second off hold switch 55B are in the off state. Thereby, the second switch SW2 is switched to the on state. With the switching of the second switch SW2 to the on state, charge flows into the gate of the first switch SW1, possibly resulting in automatic conduction of the first switch SW1 whose threshold voltage is relatively low. Here, in the present embodiment, the impedance of the first open holding path Loff1 is lower than the impedance of the second open holding path Loff 2. Therefore, the rise of the gate voltage Vgs accompanying the switching of the second switch SW2 to the on state can be suppressed, and the occurrence of the automatic on can be suppressed.

Thereafter, at time t2, the first charge switch 51A is in the on state, and the first discharge switch 54A and the first off hold switch 55A are in the off state. Thereby, the first switch SW1 is switched to the on state.

Thereafter, at time t3, first charge switch 51A is in the off state, and first discharge switch 54A is in the on state. Thereby, the gate voltage Vgs of the first switch SW1 is lower than the threshold voltage Vth1, and the first switch SW1 is switched to the off state. Further, the gate voltage Vgs of the first switch SW1 is equal to or lower than the first predetermined voltage, and the first off hold switch 55A is turned on.

Thereafter, at time t4, second charge switch 51B is turned off, and second discharge switch 54B is turned on. Thereby, the gate voltage Vge of the second switch SW2 is lower than the threshold voltage Vth2, and the second switch SW2 is switched to the off state. The gate voltage Vge of the second switch SW2 is equal to or lower than the second predetermined voltage, and the second off hold switch 55B is turned on. With the switching of the second switch SW2 to the off state, electric charge flows into the gate of the first switch SW1, possibly resulting in automatic conduction of the first switch SW1 whose threshold voltage is relatively low. Here, in the present embodiment, the impedance of the first off hold path Loff1 is made lower than the impedance of the second off hold path Loff 2. Therefore, the rise of the gate voltage Vgs accompanying the switching of the second switch SW2 to the off state can be suppressed, and the occurrence of the automatic on can be suppressed.

< eighth embodiment >

The eighth embodiment will be described below mainly focusing on differences from the first embodiment with reference to the drawings. In the present embodiment, as shown in fig. 20, the upper arm switch unit 20H and the lower arm switch unit 20L of the inverter 20 include a parallel connection body of the first switch SW1 to the third switch SW 3. In fig. 20, for convenience, the same components as those shown in fig. 6 are denoted by the same reference numerals.

The third switch SW3 is the same IGBT as the second switch SW 2. The threshold voltage Vth3 of the third switch SW3 is the same as the threshold voltage Vth2 of the second switch SW 2. The drive circuit Dr includes: a third charging switch 51C, a first charging resistor 52C, a third discharging resistor 53C, a third discharging switch 54C, and a third off-hold switch 55C.

In the present embodiment, an electrical path from the gate of the third switch SW3 to the drain of the third off hold switch 55C, between the drain and the source of the third off hold switch 55C, and from the source of the third off hold switch 55C to the source of the third switch SW3 is a third off hold path Loff3 corresponding to the third switch SW 3.

In the present embodiment, the impedance of the second open holding path Loff2 is the same as the impedance of the third open holding path Loff 3. Further, the impedance of the first open holding path Loff1 is lower than the impedances of the second and third open holding paths Loff2 and Loff 3.

According to the present embodiment described above, the same effects as those of the first embodiment can be obtained.

< modification 1 of the eighth embodiment

The impedance of the second open holding path Loff2 may be different from the impedance of the third open holding path Loff3, provided that the impedance of the first open holding path Loff1 is lower than the impedance of the second open holding path Loff2 and the impedance of the third open holding path Loff 3.

< modification 2 of the eighth embodiment

The threshold voltages Vth1 to Vth3 of the first switch SW1 to the third switch SW3 may be different from each other. Hereinafter, a case will be described as an example where the threshold voltage Vth1 of the first switch SW1 is lower than the threshold voltage Vth2 of the second switch SW2, and the threshold voltage Vth2 of the second switch SW2 is lower than the threshold voltage Vth3 of the third switch SW 3.

It is also possible that the impedance of the first open holding path Loff1 is lower than the impedance of the second open holding path Loff2, and the impedance of the second open holding path Loff2 is lower than the impedance of the third open holding path Loff 3.

Further, on the condition that the impedance of the first open holding path Loff1 is lower than the impedance of the second open holding path Loff2 and the impedance of the third open holding path Loff3, the impedance of the second open holding path Loff2 may be the same as the impedance of the third open holding path Loff3 or may be different from the impedance of the third open holding path Loff 3.

< ninth embodiment >

The ninth embodiment will be described below mainly focusing on differences from the first embodiment with reference to the drawings. In the present embodiment, as shown in fig. 21, the second off hold path Loff2 corresponding to the second switch SW2 having a relatively high threshold voltage is not provided in the drive circuit Dr. In fig. 21, for convenience, the same components as those shown in fig. 6 are denoted by the same reference numerals.

According to the present embodiment, the impedance of the first open hold path Loff1 corresponding to the first switch SW1 having a relatively low threshold voltage can be made lower than the impedance of the second discharge path Ldis2 corresponding to the second switch SW2 having a relatively high threshold voltage. Specifically, the impedance of the first off hold path Loff1 when the drive instruction of the first switch SW1 is an off instruction and the first off hold switch 55A becomes the on state can be made lower than the impedance of the second discharge path Ldis2 when the drive instruction of the second switch SW2 is an off instruction and the second discharge switch 54B becomes the on state.

< other embodiments >

The above embodiments may be modified as follows.

As shown in fig. 22, the terminals K1, a1, G1, SE1, KE1 of the first module 101 and the terminals K2, a2, G2, SE2, KE2 of the second module 102 may be aligned in the first direction.

The arrangement order of the terminals K1, a1, G1, SE1, KE1 of the first module 101 and the arrangement order of the terminals K2, a2, G2, SE2, KE2 of the second module 102 are not limited to the order shown in fig. 10, 22, and the like.

The drive control unit may be provided separately for each of the first switch SW1 and the second switch SW 2.

The off hold switch and the drive control unit may be incorporated in at least one of the first module 101 and the second module 102 without being provided in the control board 41. In this case, since the off hold switch and the drive control unit are close to the first switch SW1 and the second switch SW2, the impedance of the off hold path can be further reduced.

As shown in fig. 23, only the off hold switch and the off hold switch in the drive control unit may be incorporated in the module. When at least the OFF hold switch is built in the module, the first OFF hold terminal OFF1 and the second OFF hold terminal OFF2, which are short-circuited by the gates of the first OFF hold switch 55A and the second OFF hold switch 55B, protrude from the first module 101 and the second module 102 through the body portion. The OFF hold terminals OFF1 and OFF2 are electrically and mechanically connected to the control board 41. In this case, since the first and second off- hold switches 55A and 55B are close to the first and second switches SW1 and SW2, the impedance of the off-hold path can be further reduced.

In addition, only the off hold switch corresponding to either one of the first switch SW1 and the second switch SW2 may be incorporated in the module.

The module may include not only one switch but also a plurality of switches connected in parallel. Fig. 24 shows an example in which the first switch SW1 and the second switch SW2 are built in one module 200. In addition, the first and second power terminals T1 and T2 protrude from the body portion 200a of the module 200.

The switch group built in the module is not limited to the first switch SW1 and the second switch SW2 connected in parallel to each other. For example, the first switch SW1 of each of the upper arm switch unit 20H and the lower arm switch unit 20L in the same phase may be incorporated in one module, or the second switch SW2 of each of the upper arm switch unit 20H and the lower arm switch unit 20L in the same phase may be incorporated in one module.

The structure including the negative voltage source 57 shown in fig. 11 can be applied to embodiments other than the first embodiment.

The number of switches connected in parallel may be 4 or more.

The combination of switches connected in parallel is not limited to the combination of an N-channel MOSFET and an IGBT. Further, the power converter including the switch is not limited to the three-phase configuration.

Although the present invention has been described based on the embodiments, it should be understood that the present invention is not limited to the embodiments and the configurations described above. The present invention also includes various modifications and equivalent variations. In addition, various combinations and modes, and other combinations and modes including only one element, one or more elements, and one or less elements also belong to the scope and the idea of the present invention.