阅读说明：本技术 Nmos输出功率管的低压差稳压器 (Low dropout regulator of NMOS output power tube ) 是由 罗可欣 于 2020-06-23 设计创作，主要内容包括：本发明提供了一种NMOS输出功率管的低压差稳压器,包括低压差稳压单元和电流检测单元,电流检测单元包括第二NMOS管、第一PMOS管和第二PMOS管,所述第二NMOS管的栅极与所述第一NMOS管的栅极连接,所述第二NMOS管的源极与所述第一NMOS管的源极连接,所述第二NMOS管的漏极与所述第二PMOS管的漏极连接,所述第二PMOS管的源极接输入电压,所述第二PMOS管的栅极与所述第一PMOS管的栅极连接,所述第一PMOS管的源极接输入电压。所述NMOS输出功率管的低压差稳压器,能够检测出所述低压差稳压单元的输出电流大小,从而根据输出电流的大小,改善所述低压差稳压单元的负载调整率。(The invention provides a low dropout regulator of an NMOS (N-channel metal oxide semiconductor) output power tube, which comprises a low dropout regulator unit and a current detection unit, wherein the current detection unit comprises a second NMOS tube, a first PMOS tube and a second PMOS tube, the grid electrode of the second NMOS tube is connected with the grid electrode of the first NMOS tube, the source electrode of the second NMOS tube is connected with the source electrode of the first NMOS tube, the drain electrode of the second NMOS tube is connected with the drain electrode of the second PMOS tube, the source electrode of the second PMOS tube is connected with an input voltage, the grid electrode of the second PMOS tube is connected with the grid electrode of the first PMOS tube, and the source electrode of the first PMOS tube is connected with the input voltage. The low dropout regulator of the NMOS output power tube can detect the output current of the low dropout regulator unit, thereby improving the load regulation rate of the low dropout regulator unit according to the output current.)

1. A low dropout regulator of an NMOS output power tube is characterized by comprising:

the low-dropout voltage stabilizing unit comprises an error amplifying circuit, a first NMOS (N-channel metal oxide semiconductor) tube and a feedback network, wherein the output end of the error amplifying circuit is connected with the grid electrode of the first NMOS tube, the input end of the error amplifying circuit is connected with the output end of the feedback network, the drain electrode of the first NMOS tube is connected with an input voltage, the source electrode of the first NMOS tube is connected with the input end of the feedback network, and the grounding end of the feedback network is grounded;

the current detection unit comprises a second NMOS tube, a first PMOS tube and a second PMOS tube, wherein the grid electrode of the second NMOS tube is connected with the grid electrode of the first NMOS tube, the source electrode of the second NMOS tube is connected with the source electrode of the first NMOS tube, the drain electrode of the second NMOS tube is connected with the drain electrode of the second PMOS tube, the source electrode of the second PMOS tube is connected with an input voltage, the grid electrode of the second PMOS tube is connected with the grid electrode of the first PMOS tube, and the source electrode of the first PMOS tube is connected with the input voltage;

wherein the error amplifying circuit comprises one of an error amplifier or an error amplification adjusting circuit,

when the error amplifying circuit is the error amplifier, the drain electrode of the first PMOS tube is connected with the output end of the feedback network;

when the error amplifying circuit is the error amplifier, the low dropout regulator of the NMOS output power transistor further includes a reference voltage adjusting circuit, an output terminal of the reference voltage adjusting circuit is connected with an input terminal of the error amplifier, and an input terminal of the reference voltage adjusting circuit is connected with a drain electrode of the first PMOS transistor;

when the error amplifying circuit is an error amplifying and adjusting circuit, the drain electrode of the first PMOS tube is connected with the input end of the error amplifying and adjusting circuit.

2. The low dropout regulator of the NMOS output power transistor of claim 1, wherein the current detection unit further comprises a third PMOS transistor and a third NMOS transistor, wherein a source of the third PMOS transistor is connected to a gate of the first PMOS transistor and a gate of the second PMOS transistor and then connected to an input voltage, a drain of the third PMOS transistor is grounded, a gate of the third PMOS transistor is connected to a source of the third NMOS transistor and then grounded, a drain of the third NMOS transistor is connected to an input voltage, and a gate of the third NMOS transistor is connected to a drain of the second PMOS transistor.

3. The low dropout regulator of the NMOS output power transistor of claim 1 or 2, wherein the reference voltage adjusting circuit comprises a third resistor and a fourth resistor, one end of the third resistor is connected to the input voltage and the input terminal of the error amplifier, the other end of the third resistor is connected to one end of the fourth resistor and the output terminal of the current detecting unit, and the other end of the fourth resistor is grounded.

4. The low dropout regulator of an NMOS output power transistor according to claim 1 or 2, wherein the error amplification and adjustment circuit comprises a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a fourth NMOS transistor and a fifth NMOS transistor, wherein a source of the fourth PMOS transistor is connected to a source of the fifth PMOS transistor, a gate of the fourth PMOS transistor is connected to a reference voltage, a drain of the fourth PMOS transistor is connected to an output terminal of the current detection unit through a first line, a source of the fifth PMOS transistor is connected to an input voltage, a gate of the fifth PMOS transistor is connected to an output terminal of the feedback network, a drain of the fifth PMOS transistor is connected to a source of the fifth NMOS transistor, a source of the fifth NMOS transistor is grounded, a gate of the fifth NMOS transistor is connected to a gate of the fourth NMOS transistor, a source of the fourth NMOS transistor is grounded after being connected to the first line, the drain electrode of the fifth NMOS tube is connected with the drain electrode of a seventh PMOS tube and the grid electrode of the first NMOS tube, the source electrode of the seventh PMOS tube is connected with input voltage, the grid electrode of the seventh PMOS tube is connected with the grid electrode of the sixth PMOS tube, the source electrode of the sixth PMOS tube is connected with input voltage, the drain electrode of the sixth PMOS tube is connected with the drain electrode of the fourth NMOS tube, and the grid electrode and the drain electrode of the sixth PMOS tube are in short circuit.

5. The low dropout regulator of an NMOS output power transistor according to claim 1 or 2, wherein the error amplification adjustment circuit comprises a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor, wherein a source of the fourth PMOS transistor is connected to a source of the fifth PMOS transistor, a gate of the fifth PMOS transistor is connected to a reference voltage, a drain of the fourth PMOS transistor is connected to a drain of the seventh NMOS transistor, a drain of the seventh NMOS transistor is shorted to a gate, a gate of the seventh NMOS transistor is connected to a gate of the eighth NMOS transistor, a drain of the eighth NMOS transistor is connected to a source of the fourth NMOS transistor, a gate of the fourth NMOS transistor is connected to a gate of the fifth NMOS transistor, and a drain of the fourth NMOS transistor is connected to a drain of the sixth PMOS transistor, the source electrode of the sixth PMOS tube is connected with the input voltage, the drain electrode and the grid electrode of the sixth PMOS tube are in short circuit, the grid electrode of the sixth PMOS tube is connected with the grid electrode of the seventh PMOS tube, the source electrode of the seventh PMOS tube is connected with the input voltage, the drain electrode of the seventh PMOS tube is connected with the grid electrode of the first NMOS tube and the drain electrode of the fifth NMOS tube, the source electrode of the fifth NMOS tube is connected with the output end of the current detection unit and the drain electrode of the ninth NMOS tube, the grid electrode of the ninth NMOS tube is connected with the grid electrode of the sixth NMOS tube, the drain electrode and the grid electrode of the sixth NMOS tube are in short circuit, the drain electrode of the sixth NMOS tube is connected with the drain electrode of the fifth PMOS tube, the grid electrode of the fifth PMOS tube is connected with the output end of the feedback network, and the source electrodes of the sixth NMOS tube, the seventh NMOS tube, the eighth NMOS tube and the ninth NMOS tube are all grounded.

Technical Field

The invention relates to the technical field of low dropout regulators, in particular to a low dropout regulator of an NMOS output power tube.

Background

The low dropout regulator comprises an output power period, a feedback network and an error amplifier, and the output current of the low dropout regulator has a large variation range along with the load condition, so that the stability of a circuit, the working temperature, the stability of output voltage and the like are influenced.

The power output variation caused by the variation of the output current can be described by a load regulation (load regulation) index, and can be expressed by the following formula: load Regulation ═ Vfl-Vml |/Vhl x 100%, Vfl and Vml are output voltages at full Load and minimum Load, respectively, of the low dropout regulator, and Vhl is an output voltage at half Load. The load is increased, the output voltage is reduced, conversely, the load is reduced, and the output voltage is increased, so that the smaller the load regulation rate is, the stronger the capability of the low dropout voltage regulator for inhibiting load interference is. However, the current detection circuit and the load adjustment circuit of the low dropout regulator aiming at the NMOS output power tube are lacked in the prior art.

Therefore, there is a need to provide a new low dropout regulator of NMOS output power transistor to solve the above problems in the prior art.

Disclosure of Invention

The invention aims to provide a low dropout regulator of an NMOS (N-channel metal oxide semiconductor) output power tube, which detects the magnitude of output current so as to improve the load regulation rate of the low dropout regulator.

In order to achieve the above object, the low dropout regulator of the NMOS output power transistor of the present invention comprises:

the low-dropout voltage stabilizing unit comprises an error amplifying circuit, a first NMOS (N-channel metal oxide semiconductor) tube and a feedback network, wherein the output end of the error amplifying circuit is connected with the grid electrode of the first NMOS tube, the input end of the error amplifying circuit is connected with the output end of the feedback network, the drain electrode of the first NMOS tube is connected with an input voltage, the source electrode of the first NMOS tube is connected with the input end of the feedback network, and the grounding end of the feedback network is grounded;

the current detection unit comprises a second NMOS tube, a first PMOS tube and a second PMOS tube, wherein the grid electrode of the second NMOS tube is connected with the grid electrode of the first NMOS tube, the source electrode of the second NMOS tube is connected with the source electrode of the first NMOS tube, the drain electrode of the second NMOS tube is connected with the drain electrode of the second PMOS tube, the source electrode of the second PMOS tube is connected with an input voltage, the grid electrode of the second PMOS tube is connected with the grid electrode of the first PMOS tube, and the source electrode of the first PMOS tube is connected with the input voltage;

wherein the error amplifying circuit comprises one of an error amplifier or an error amplification adjusting circuit,

when the error amplifying circuit is the error amplifier, the drain electrode of the first PMOS tube is connected with the output end of the feedback network;

when the error amplifying circuit is the error amplifier, the low dropout regulator of the NMOS output power transistor further includes a reference voltage adjusting circuit, an output terminal of the reference voltage adjusting circuit is connected with an input terminal of the error amplifier, and an input terminal of the reference voltage adjusting circuit is connected with a drain electrode of the first PMOS transistor;

when the error amplifying circuit is an error amplifying and adjusting circuit, the drain electrode of the first PMOS tube is connected with the input end of the error amplifying and adjusting circuit.

The invention has the beneficial effects that: the current detection unit comprises a second NMOS tube, a first PMOS tube and a second PMOS tube, wherein a grid electrode of the second NMOS tube is connected with a grid electrode of the first NMOS tube, a source electrode of the second NMOS tube is connected with a source electrode of the first NMOS tube, a drain electrode of the second NMOS tube is connected with a drain electrode of the second PMOS tube, a source electrode of the second PMOS tube is connected with input voltage, a grid electrode of the second PMOS tube is connected with a grid electrode of the first PMOS tube, and a source electrode of the first PMOS tube is connected with the input voltage, so that the output current of the low-dropout voltage stabilization unit can be detected, and the load regulation rate of the low-dropout voltage stabilization unit is improved according to the output current.

Preferably, the current detection unit further includes a third PMOS transistor and a third NMOS transistor, a source of the third PMOS transistor is connected to the gate of the first PMOS transistor and the gate of the second PMOS transistor and then connected to the input voltage, a drain of the third PMOS transistor is grounded, a gate of the third PMOS transistor is connected to the source of the third NMOS transistor and then grounded, a drain of the third NMOS transistor is connected to the input voltage, and a gate of the third NMOS transistor is connected to the drain of the second PMOS transistor.

Further preferably, the reference voltage adjusting circuit includes a third resistor and a fourth resistor, one end of the third resistor is connected to the input voltage and the input terminal of the error amplifier, the other end of the third resistor is connected to one end of the fourth resistor and the output terminal of the current detecting unit, and the other end of the fourth resistor is grounded. The beneficial effects are that: the reference voltage adjusting circuit can adjust the reference voltage of the error amplifier according to the output current detected by the current detection unit, so that the load adjustment rate of the low dropout voltage stabilizing unit is improved.

Further preferably, the error amplification and adjustment circuit includes a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor, a source of the fourth PMOS transistor is connected to a source of the fifth PMOS transistor, a gate of the fourth PMOS transistor is connected to a reference voltage, a drain of the fourth PMOS transistor is connected to an output terminal of the current detection unit through a first line, a source of the fifth PMOS transistor is connected to an input voltage, a gate of the fifth PMOS transistor is connected to an output terminal of the feedback network, a drain of the fifth PMOS transistor is connected to a source of the fifth NMOS transistor, a source of the fifth NMOS transistor is grounded, a gate of the fifth NMOS transistor is connected to a gate of the fourth NMOS transistor, a source of the fourth NMOS transistor is grounded after being connected to the first line, a drain of the fifth NMOS transistor is connected to a drain of the seventh PMOS transistor and a gate of the first NMOS transistor, the source electrode of the seventh PMOS tube is connected with the input voltage, the grid electrode of the seventh PMOS tube is connected with the grid electrode of the sixth PMOS tube, the source electrode of the sixth PMOS tube is connected with the input voltage, the drain electrode of the sixth PMOS tube is connected with the drain electrode of the fourth NMOS tube, and the grid electrode and the drain electrode of the sixth PMOS tube are in short circuit. The beneficial effects are that: the error amplification adjusting circuit can adjust according to the output current detected by the current detection unit, and replaces an error amplifier in the prior art, so that the load adjustment rate of the low dropout voltage regulator unit can be improved.

Further preferably, the error amplification and adjustment circuit includes a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor, wherein a source of the fourth PMOS transistor is connected to a source of the fifth PMOS transistor, a gate of the fifth PMOS transistor is connected to a reference voltage, a drain of the fourth PMOS transistor is connected to a drain of the seventh NMOS transistor, a drain of the seventh NMOS transistor is shorted to a gate, a gate of the seventh NMOS transistor is connected to a gate of the eighth NMOS transistor, a drain of the eighth NMOS transistor is connected to a source of the fourth NMOS transistor, a gate of the fourth NMOS transistor is connected to a gate of the fifth NMOS transistor, a drain of the fourth NMOS transistor is connected to a drain of the sixth PMOS transistor, a source of the sixth PMOS transistor is connected to an input voltage, and a drain and a gate of the sixth PMOS transistor are shorted to a gate, the grid electrode of the sixth PMOS tube is connected with the grid electrode of the seventh PMOS tube, the source electrode of the seventh PMOS tube is connected with input voltage, the drain electrode of the seventh PMOS tube is connected with the grid electrode of the first NMOS tube and the drain electrode of the fifth NMOS tube, the source electrode of the fifth NMOS tube is connected with the output end of the current detection unit and the drain electrode of the ninth NMOS tube, the grid electrode of the ninth NMOS tube is connected with the grid electrode of the sixth NMOS tube, the drain electrode of the sixth NMOS tube is in short circuit with the grid electrode, the drain electrode of the sixth NMOS tube is connected with the drain electrode of the fifth PMOS tube, the grid electrode of the fifth PMOS tube is connected with the output end of the feedback network, and the source electrodes of the sixth NMOS tube, the seventh NMOS tube, the eighth NMOS tube and the ninth NMOS tube are all grounded. The beneficial effects are that: the error amplification adjusting circuit can adjust according to the output current detected by the current detection unit, and replaces an error amplifier in the prior art, so that the load adjustment rate of the low dropout voltage regulator unit can be improved.

Drawings

FIG. 1 is a schematic circuit diagram of a low dropout voltage regulator unit according to the present invention;

FIG. 2 is a schematic diagram of a low dropout regulator with an NMOS output power transistor according to some embodiments of the present invention;

FIG. 3 is a schematic diagram of a low dropout regulator with an NMOS output power transistor according to some embodiments of the present invention;

FIG. 4 is a schematic diagram of a low dropout regulator with an NMOS output power transistor according to some preferred embodiments of the present invention;

FIG. 5 is a schematic diagram of a low dropout regulator with an NMOS output power transistor according to some preferred embodiments of the present invention;

FIG. 6 is a schematic diagram of a low dropout regulator with an NMOS output power transistor according to some embodiments of the present invention;

FIG. 7 is a schematic diagram of a low dropout regulator with an NMOS output power transistor according to some preferred embodiments of the present invention;

FIG. 8 is a schematic diagram of a low dropout regulator with an NMOS output power transistor according to some embodiments of the present invention;

fig. 9 shows a low dropout regulator with NMOS output power transistors according to some preferred embodiments of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and similar words are intended to mean that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.

For solving the problems in the prior art, an embodiment of the present invention provides a low dropout regulator of an NMOS output power transistor, and referring to fig. 1 to fig. 9, the low dropout regulator of the NMOS output power transistor includes a low dropout regulator unit 10 and a current detection unit 20, the low dropout regulator unit 10 includes an error amplification circuit, 11 a first NMOS transistor 12 and a feedback network 13, an output terminal of the error amplification circuit 11 is connected to a gate of the first NMOS transistor 12, an input terminal of the error amplification circuit 11 is connected to an output terminal of the feedback network 13, a drain of the first NMOS transistor 12 is connected to an input voltage, a source of the first NMOS transistor 11 is connected to an input terminal of the feedback network 13, and a ground terminal of the feedback network 13 is grounded. Specifically, the feedback network 13 includes a first resistor 131 and a second resistor 132, one end of the first resistor 131 is connected to the source of the first NMOS transistor 12, the other end of the first resistor 131 is connected to the second resistor 132, and the other end of the second resistor 132 is grounded.

In some embodiments, referring to fig. 2 and 4, the error amplifying circuit is an error amplifier 14, and an output terminal of the current detecting unit 20 is connected to an output terminal of the feedback network 13. Specifically, the output terminal of the error amplifier 14 is connected to the gate of the first NMOS transistor 12, the positive phase of the error amplifier 14 is connected to the reference voltage, and the negative phase of the error amplifier 14 is connected to one end of the first resistor 131 and one end of the second resistor 132.

In some embodiments, referring to fig. 2, 3, 6 and 8, the current detection unit 20 includes a second NMOS transistor 21, a first PMOS transistor 22 and a second PMOS transistor 23, a gate of the second NMOS transistor 21 is connected to a gate of the first NMOS transistor 12, a source of the second NMOS transistor 21 is connected to a source of the first NMOS transistor 12, a drain of the second NMOS transistor 21 is connected to a drain of the second PMOS transistor 23, a source of the second PMOS transistor 23 is connected to an input voltage, a gate of the second PMOS transistor 23 is connected to a gate of the first PMOS transistor 22, a source of the first PMOS transistor 22 is connected to the input voltage, and a gate and a drain of the second PMOS transistor 21 are shorted.

In some preferred embodiments, referring to fig. 4 and 5, the current detection unit 20 further includes a third PMOS transistor 24 and a third NMOS transistor 25, a source of the third PMOS transistor 24 is connected to a gate of the first PMOS transistor 22 and a gate of the second PMOS transistor 22 and then connected to an input voltage, a drain of the third PMOS transistor 24 is grounded, a gate of the third PMOS transistor 24 is connected to a source of the third NMOS transistor 25 and then grounded, a drain of the third NMOS transistor 25 is connected to an input voltage, and a gate of the third NMOS transistor 25 is connected to a drain of the second PMOS transistor 23.

Specifically, referring to fig. 2 and 4, the drain of the first PMOS transistor 22 is connected to one end of the first resistor 131 and one end of the second resistor 132.

In some embodiments, the error amplifying circuit is an error amplifier, the low dropout regulator of the NMOS output power transistor further includes a reference voltage adjusting circuit, an output terminal of the reference voltage adjusting circuit is connected to an input terminal of the error amplifier, and an input terminal of the reference voltage adjusting circuit is connected to a drain of the first PMOS transistor.

In some embodiments, referring to fig. 3 and 5, the reference voltage adjusting circuit 30 includes a third resistor 31 and a fourth resistor 32, one end of the third resistor 31 is connected to the input voltage and the non-inverting input terminal of the error amplifier 14, the other end of the third resistor 31 is connected to one end of the fourth resistor 32 and the output terminal of the current detecting unit 20, and the other end of the fourth resistor 32 is connected to ground.

Specifically, referring to fig. 3 and 5, the drain of the first PMOS transistor 22 is connected to one end of the third resistor 31 and one end of the fourth resistor 32.

In some embodiments, the error amplifying circuit is an error amplifying and adjusting circuit, and the drain of the first PMOS transistor is connected to the input terminal of the error amplifying and adjusting circuit.

In some embodiments, referring to fig. 6 and 7, the error amplification and adjustment circuit 15 includes a fourth PMOS transistor 151, a fifth PMOS transistor 152, a sixth PMOS transistor 153, a seventh PMOS transistor 154, a fourth NMOS transistor 155, and a fifth NMOS transistor 156, a source of the fourth PMOS transistor 151 is connected to a source of the fifth PMOS transistor 152, a gate of the fourth PMOS transistor 151 is connected to a reference voltage, a drain of the fourth PMOS transistor 151 is connected to the output terminal of the current detection unit 20 through the first line 1511, a source of the fifth PMOS transistor 152 is connected to an input voltage, a gate of the fifth PMOS transistor 152 is connected to the output terminal of the feedback network 13, a drain of the fifth PMOS transistor 152 is connected to the source of the fifth NMOS transistor 156, a source of the fifth NMOS transistor 156 is connected to ground, a gate of the fifth NMOS transistor 156 is connected to the gate of the fourth NMOS transistor 155, a source of the fourth NMOS transistor 155 is connected to the first line 1511 and then connected to ground, the drain of the fifth NMOS transistor 156 is connected to the drain of the seventh PMOS transistor 154 and the gate of the first NMOS transistor 12, the source of the seventh PMOS transistor 154 is connected to the input voltage, the gate of the seventh PMOS transistor 154 is connected to the gate of the sixth PMOS transistor 153, the source of the sixth PMOS transistor 153 is connected to the input voltage, the drain of the sixth PMOS transistor 153 is connected to the drain of the fourth NMOS transistor 155, and the gate and the drain of the sixth PMOS transistor 153 are shorted.

Specifically, referring to fig. 6 and 7, the drain of the fourth PMOS transistor 151 is connected to the drain of the first PMOS transistor 22 through the first line 1511, and the gate of the fifth PMOS transistor 152 is connected to one end of the first resistor 131 and one end of the second resistor 132.

In some embodiments, referring to fig. 8 and 9, the error amplification and adjustment circuit includes a fourth PMOS transistor 151, a fifth PMOS transistor 152, a sixth PMOS transistor 153, a seventh PMOS transistor 154, a fourth NMOS transistor 155, a fifth NMOS transistor 156, a sixth NMOS transistor 157, a seventh NMOS transistor 158, an eighth NMOS transistor 159, and a ninth NMOS transistor 160, a source of the fourth PMOS transistor 151 and a source of the fifth PMOS transistor 152 are connected, a gate of the fifth PMOS transistor 152 is connected to a reference voltage, a drain of the fourth PMOS transistor 151 and a drain of the seventh NMOS transistor 158 are connected, a drain of the seventh NMOS transistor 158 is shorted with a gate, a gate of the seventh NMOS transistor 158 and a gate of the eighth NMOS transistor 159 are connected, a drain of the eighth NMOS transistor 159 and a source of the fourth NMOS transistor 155 are connected, a gate of the fourth NMOS transistor 155 and a gate of the fifth NMOS transistor 156 are connected, a drain of the fourth NMOS transistor 155 and a drain of the sixth PMOS transistor 155 and a drain of the sixth NMOS transistor 153 are connected, the source of the sixth PMOS transistor 153 is connected to the input voltage, the drain and the gate of the sixth PMOS transistor 153 are shorted, the gate of the sixth PMOS transistor 153 is connected to the gate of the seventh PMOS transistor 154, the source of the seventh PMOS transistor 154 is connected to the input voltage, the drain of the seventh PMOS transistor 154 is connected to the gate of the first NMOS transistor 12 and the drain of the fifth NMOS transistor 156, the source of the fifth NMOS transistor 156 is connected to the output of the current detection unit and the drain of the ninth NMOS transistor 160, the gate of the ninth NMOS transistor 160 is connected to the gate of the sixth NMOS transistor 157, the drain and the gate of the sixth NMOS transistor 157 are shorted, the drain of the sixth NMOS transistor 157 is connected to the drain of the fifth PMOS transistor 152, the gate of the fifth PMOS transistor 152 is connected to the output end of the feedback network, and the sources of the sixth NMOS transistor 157, the seventh NMOS transistor 158, the eighth NMOS transistor 159, and the ninth NMOS transistor 160 are all grounded.

Specifically, referring to fig. 8 and 9, the source of the fifth NMOS transistor 156 is connected to the drain of the first PMOS transistor, and the gate of the fifth PMOS transistor 152 is connected to one end of the first resistor 131 and one end of the second resistor 132.

Although the embodiments of the present invention have been described in detail hereinabove, it is apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention as described herein is capable of other embodiments and of being practiced or of being carried out in various ways.