阅读说明：本技术 一种动态延迟唤醒电路及乱序指令发射架构 (Dynamic delay wake-up circuit and out-of-order instruction transmitting architecture ) 是由 虞致国 马晓杰 魏敬和 顾晓峰 于 2020-04-07 设计创作，主要内容包括：本发明公开了一种动态延迟唤醒电路及乱序指令发射架构,属于处理器设计领域。所述动态延迟唤醒电路,包括比较器、指令执行辨别电路和寄存器,通过指令执行辨别电路识别待发射指令的执行周期,并输出待发射指令的周期数,寄存器通过待发射指令的周期数对将要送出的唤醒信号进行寄存,从而达到对唤醒信号顺序调整的目的,对执行周期短的指令延迟唤醒,对执行周期长的指令提前唤醒,从而保证了流水线上的指令能够背靠背执行,提高了流水线的效率。(The invention discloses a dynamic delay wake-up circuit and an out-of-order instruction transmitting framework, and belongs to the field of processor design. The dynamic delay awakening circuit comprises a comparator, an instruction execution distinguishing circuit and a register, wherein the instruction execution distinguishing circuit is used for identifying the execution period of an instruction to be transmitted and outputting the period number of the instruction to be transmitted, the register registers an awakening signal to be sent out according to the period number of the instruction to be transmitted, so that the aim of adjusting the sequence of the awakening signal is fulfilled, the instruction with a short execution period is awakened in a delayed mode, the instruction with a long execution period is awakened in advance, the instructions on a production line can be executed back to back, and the efficiency of the production line is improved.)

1. A wake-up circuit, comprising a comparator, an instruction execution discrimination circuit, a register;

the comparator is used for comparing whether the source register number of the instruction to be transmitted is equal to the destination register number of the transmitted instruction; if the two signals are equal, sending out a wake-up signal;

the instruction execution distinguishing circuit is used for identifying the execution period of the instruction to be transmitted and outputting the period number of the instruction to be transmitted;

the register is used for registering the wake-up signal to be sent according to the cycle number of the instruction to be transmitted, which is output by the instruction execution distinguishing circuit, so that the sequence of the wake-up signal of the instruction to be transmitted is determined, and the wake-up operation is carried out on the instruction to be transmitted according to the sequence of the wake-up signal.

2. The wake-up circuit of claim 1, wherein the instruction execution discrimination circuit is implemented by a read-only RAM, wherein the read-only RAM is pre-written with the number of execution cycles corresponding to different instructions, and the number of pre-stored cycles in the RAM is read out by inputting the class code of the instruction as an address, so as to obtain the operation cycle of the corresponding instruction.

3. The wake-up circuit of claim 2, wherein if the source register number of the instruction to be transmitted is equal to the destination register number of the transmitted instruction, the comparator outputs a high level as a wake-up signal indicating that the instruction is woken up; if not, a low level is output, which represents that the instruction is not awakened.

4. The wake-up circuit of claim 3, wherein the out-of-order instruction issue structure waits for the former instruction to be executed and then wakes up the latter instruction when the former instruction is issued in the sequential order during the wake-up instruction.

5. An instruction wake-up method, applied to the wake-up circuit of any one of claims 1 to 4, wherein the method determines a wake-up sequence of instructions to be issued according to the number of cycles of the instructions to be issued, delays wake-up for instructions with short execution cycles, and advances wake-up for instructions with long execution cycles, thereby ensuring that the instructions on the pipeline can be executed back-to-back.

6. Instruction wakeup method according to claim 5, characterized in that the method comprises:

acquiring the source register number of an instruction to be transmitted and the destination register number of a transmitted instruction, and comparing whether the source register number and the destination register number are equal;

and if the command is equal to the command, sending out the wake-up signal, simultaneously acquiring the execution period of the command to be transmitted, registering the wake-up signal to be sent out according to the period of the command to be transmitted, and determining the wake-up sequence of the command to be transmitted.

7. An out-of-order instruction issue architecture, wherein the wake-up circuit in the out-of-order instruction issue architecture is the wake-up circuit of any one of claims 1 to 4.

8. The out-of-order instruction issue architecture of claim 7, wherein the out-of-order instruction issue architecture further comprises instruction dispatch circuitry and instruction request circuitry;

the instruction distribution circuit is used for distributing a plurality of instructions sent by the physical register to idle table entries in the transmission queue;

the instruction request circuit is used for counting the total number of idle signals of the table entries in the transmission queue, encoding the number of the idle signals by using special codes, and if the total number of the idle signals subjected to encoding is smaller than the instruction transmission width subjected to encoding, sending an instruction request signal to the physical register file.

9. The out-of-order instruction issue architecture of claim 8, wherein the instruction request circuit is comprised of two parts: an addition-like layer and a post log2(n/2) layer are used for shifting a logic layer, wherein n is the instruction emission width of the processor;

when the total number of idle signals of the table entries is counted, inputting the idle signal sequence of the table entries into a similar addition layer, and performing special coding on the number of the idle signals to obtain the total number of the idle signals subjected to the special coding, wherein the idle signal sequence of the table entries is a string of binary sequences with n bits, n is the number of the table entries in a transmitting queue, each bit of the idle signal sequence represents whether each table entry in the transmitting queue is idle or not, and if the idle signal sequence is idle, the idle signal sequence is 0, and if the idle signal sequence is not idle, the idle signal sequence is 1; and (3) sending the output of the similar addition layer into a post log2(n/2) layer shift logic layer, connecting the shift logic layers layer by layer, and outputting a statistical result in a tree structure. The statistical result is compared to the instruction issue width, which is also specially encoded, to determine whether an instruction request signal needs to be sent.

10. The out-of-order instruction issue architecture of claim 8, wherein the add-like layer is comprised of an add-like compute unit; inputting the idle signal sequence of the table entry into the quasi-addition layer, and performing special coding on the number of the idle signals to obtain the total number of the idle signals subjected to the special coding, wherein the method comprises the following steps:

when the total number of idle signals of the table entry is counted, the idle signal sequence of the table entry is input into a class addition layer, each class addition unit inputs two binary numbers in the idle signal sequence and respectively performs AND operation and XOR operation, and then the calculation results of the two are compared:

if equal, and the and operation result is 1, then the code representing 1 is output: "01", representing the sum of the two-level system number inputs of the class add unit is 1, and is encoded as "01"

If equal, and the AND operation results in bit 0, then the code representing 0 is output: "10", representing the sum of the two-level system number inputs of the class add unit is 0, and is encoded as "10";

if not, the output represents the code of 2: "00", representing the sum of the two-level system number inputs of the class add unit is 2, and encoded as "00";

the number of coded bits is n;

the post log2(n/2) level shift logic level is composed of right shift shifters; inputting the output result of the total number of the encoded idle signals to a post-log 2(n/2) layer shift logic layer, and comparing the output result with the instruction transmission width which is also specially encoded to determine whether an instruction request signal needs to be sent, wherein the method comprises the following steps:

the right shift shifter takes the output of one type of addition unit as the input of data to be shifted, and the output of the other type of addition unit as the input of shift digits, and the number of bits to be shifted is shifted to the right by n bits through the right shift shifter, wherein n is the decimal number corresponding to the shift digits.

Technical Field

The invention relates to a dynamic delay wake-up circuit and an out-of-order instruction transmitting framework, and belongs to the field of processor design.

Background

The working process of a transmitting circuit in the processor is a process of continuously transmitting instructions, so that an instruction transmitting architecture is one of important architectures for realizing high performance of the processor; in order to achieve high performance, the instruction issue architecture must implement high IPC (Instructions per cycle) with low latency, and the instruction issue architecture is required to include an instruction allocation circuit, an instruction request circuit, and a wake-up circuit to implement low latency as much as possible in order to implement low latency.

The wake-up circuit is used as a constituent part of the instruction transmitting architecture and is used for waking up an instruction to be transmitted; the traditional wake-up circuit wakes up the instruction which can be woken up without delay, or wakes up the instruction which can be woken up with a fixed delay period. In a modern superscalar out-of-order emission processor, execution cycles of all instructions are greatly different, the instructions are awakened according to logic of a traditional awakening circuit, and the condition that the next instruction is awakened and emitted when the previous instruction is not executed is generated.

This situation can cause delayed bubbles in the pipeline, reducing pipeline efficiency and affecting IPC of the processor. Therefore, it is very urgent to provide a design of a dynamic delay wake-up circuit for the above requirements and challenges, low latency, high IPC, and so on.

Disclosure of Invention

In order to solve the problems that bubbles exist among instructions and the pipeline efficiency is not high when a traditional wake-up circuit is applied, the invention provides a dynamic delay wake-up circuit and an out-of-order instruction transmitting framework, and the technical scheme is as follows:

a wake-up circuit comprises a comparator, an instruction execution discrimination circuit, and a register;

the comparator is used for comparing whether the source register number of the instruction to be transmitted is equal to the destination register number of the transmitted instruction; if the two signals are equal, sending out a wake-up signal;

the instruction execution distinguishing circuit is used for identifying the execution period of the instruction to be transmitted and outputting the period number of the instruction to be transmitted;

the register is used for registering the wake-up signal to be sent according to the cycle number of the instruction to be transmitted, which is output by the instruction execution distinguishing circuit, so that the sequence of the wake-up signal of the instruction to be transmitted is determined, and the wake-up operation is carried out on the instruction to be transmitted according to the sequence of the wake-up signal.

Optionally, the instruction execution discrimination circuit is implemented by a read-only RAM, where the read-only RAM is pre-written with the number of execution cycles corresponding to different instructions, and the number of cycles pre-stored in the RAM is read out by inputting the class code of the instruction as an address, so as to obtain the operation cycle of the corresponding instruction.

Optionally, if the source register number of the instruction to be transmitted is equal to the destination register number of the transmitted instruction, the comparator outputs a high level as a wake-up signal to represent that the instruction is woken up; if not, a low level is output, which represents that the instruction is not awakened.

Optionally, when the wake-up circuit wakes up the instruction, after the preceding instruction in the instructions having the sequence is transmitted, the processor waits for the preceding instruction to be executed and then wakes up the following instruction.

The invention also provides an instruction awakening method, which is applied to the awakening circuit and determines the awakening sequence of the instruction to be transmitted according to the period number of the instruction to be transmitted, and the instruction with short execution period is awakened in a delayed mode and the instruction with long execution period is awakened in advance, so that the instructions on the production line can be executed back to back.

Optionally, the method includes:

acquiring the source register number of an instruction to be transmitted and the destination register number of a transmitted instruction, and comparing whether the source register number and the destination register number are equal;

and if the command is equal to the command, sending out the wake-up signal, simultaneously acquiring the execution period of the command to be transmitted, registering the wake-up signal to be sent out according to the period of the command to be transmitted, and determining the wake-up sequence of the command to be transmitted.

The invention also provides an out-of-order instruction transmitting architecture, which comprises the wake-up circuit

Optionally, the out-of-order instruction issuing architecture further includes an instruction allocating circuit and an instruction requesting circuit;

the instruction distribution circuit is used for distributing a plurality of instructions sent by the physical register to idle table entries in the transmission queue;

the instruction request circuit is used for counting the total number of idle signals of the table entries in the transmission queue, encoding the number of the idle signals by using special codes, and if the total number of the idle signals subjected to encoding is smaller than the instruction transmission width subjected to encoding, sending an instruction request signal to the physical register file.

Optionally, the instruction request circuit is composed of two parts: an addition-like layer and a post log2(n/2) layer shift logic layer, wherein n is the instruction transmitting width of the out-of-order instruction transmitting architecture;

when the total number of idle signals of the table entries is counted, inputting the idle signal sequence of the table entries into a similar addition layer, and performing special coding on the number of the idle signals to obtain the total number of the idle signals subjected to the special coding, wherein the idle signal sequence of the table entries is a string of binary sequences with n bits, n is the number of the table entries in a transmitting queue, each bit of the idle signal sequence represents whether each table entry in the transmitting queue is idle or not, and if the idle signal sequence is idle, the idle signal sequence is 0, and if the idle signal sequence is not idle, the idle signal sequence is 1; and (3) sending the output of the similar addition layer into a post log2(n/2) layer shift logic layer, connecting the shift logic layers layer by layer, and outputting a statistical result in a tree structure. The statistical result is compared to the instruction issue width, which is also specially encoded, to determine whether an instruction request signal needs to be sent.

Optionally, the class addition layer is composed of a class addition calculation unit; inputting the idle signal sequence of the table entry into the quasi-addition layer, and performing special coding on the number of the idle signals to obtain the total number of the idle signals subjected to the special coding, wherein the method comprises the following steps:

when the total number of idle signals of the table entry is counted, the idle signal sequence of the table entry is input into a class addition layer, each class addition unit inputs two binary numbers in the idle signal sequence and respectively performs AND operation and XOR operation, and then the calculation results of the two are compared:

if equal, and the and operation result is 1, then the code representing 1 is output: "01", representing the sum of the two-level system number inputs of the class add unit is 1, and is encoded as "01"

If equal, and the AND operation results in bit 0, then the code representing 0 is output: "10", representing the sum of the two-level system number inputs of the class add unit is 0, and is encoded as "10";

if not, the output represents the code of 2: "00", representing the sum of the two-level system number inputs of the class add unit is 2, and encoded as "00";

the number of coded bits is n;

the post log2(n/2) level shift logic level is composed of right shift shifters; inputting the output result of the total number of the encoded idle signals to a post-log 2(n/2) layer shift logic layer, and comparing the output result with the instruction transmission width which is also specially encoded to determine whether an instruction request signal needs to be sent, wherein the method comprises the following steps:

the right shift shifter takes the output of one type of addition unit as the input of data to be shifted, and the output of the other type of addition unit as the input of shift digits, and the number of bits to be shifted is shifted to the right by n bits through the right shift shifter, wherein n is the decimal number corresponding to the shift digits.

The invention has the beneficial effects that:

the invention provides a dynamic delay wake-up circuit, which comprises a comparator, an instruction execution distinguishing circuit and a register, wherein the instruction execution distinguishing circuit is used for identifying the execution period of an instruction to be transmitted and outputting the period number of the instruction to be transmitted, the register is used for registering a wake-up signal to be sent out according to the period number of the instruction to be transmitted, so that the aim of adjusting the sequence of the wake-up signal is fulfilled, the instruction with a short execution period is awakened in a delay mode, the instruction with a long execution period is awakened in advance, so that the instructions on a production line can be executed back to back, and the efficiency of the production line is improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic diagram of the wake-up circuit according to the present invention.

FIG. 2 is a schematic diagram of a pipeline for adjusting a wake-up sequence via a wake-up circuit.

FIG. 3 is a block diagram of the multi-instruction out-of-order issue architecture.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.