阅读说明：本技术 锗探测器及其制造方法 (Germanium detector and manufacturing method thereof ) 是由 唐波 张鹏 李志华 李彬 刘若男 于 2020-01-20 设计创作，主要内容包括：本发明公开了一种锗探测器及其制造方法,所述锗探测器的制造方法包括：在半导体衬底的上表面形成第一介质层；对所述第一介质层进行刻蚀,直至暴露出所述半导体衬底的部分上表面,以形成第一凹槽；在所述第一凹槽的底部生长第一探测层,所述第一探测层的材料为锗硅；在所述第一探测层的上表面生长第二探测层,所述第二探测层的材料为锗；在所述第二探测层的上表面生长第三探测层,所述第三探测层的材料为锗；对所述第三探测层进行表面平坦化处理,使所述第三探测层的上表面和所述第一介质层的上表面位于同一平面内。本发明提供的锗探测器及其制造方法,采用锗硅作为缓冲层,可以达到减小锗探测器暗电流的目的。(The invention discloses a germanium detector and a manufacturing method thereof, wherein the manufacturing method of the germanium detector comprises the following steps: forming a first dielectric layer on the upper surface of the semiconductor substrate; etching the first dielectric layer until part of the upper surface of the semiconductor substrate is exposed to form a first groove; growing a first detection layer at the bottom of the first groove, wherein the first detection layer is made of germanium-silicon; growing a second detection layer on the upper surface of the first detection layer, wherein the second detection layer is made of germanium; growing a third detection layer on the upper surface of the second detection layer, wherein the third detection layer is made of germanium; and carrying out surface planarization treatment on the third detection layer to enable the upper surface of the third detection layer and the upper surface of the first medium layer to be positioned in the same plane. According to the germanium detector and the manufacturing method thereof, germanium silicon is used as the buffer layer, and the purpose of reducing dark current of the germanium detector can be achieved.)

1. A method of fabricating a germanium detector, comprising:

forming a first dielectric layer on the upper surface of the semiconductor substrate;

etching the first dielectric layer until part of the upper surface of the semiconductor substrate is exposed to form a first groove;

growing a first detection layer at the bottom of the first groove, wherein the first detection layer is made of germanium-silicon, and the thickness of the first detection layer is smaller than that of the first dielectric layer;

growing a second detection layer on the upper surface of the first detection layer, wherein the second detection layer is made of germanium, and the sum of the thickness of the first detection layer and the thickness of the second detection layer is smaller than that of the first medium layer;

growing a third detection layer on the upper surface of the second detection layer, wherein the third detection layer is made of germanium, and the growth temperature of the third detection layer is higher than that of the second detection layer;

and carrying out surface planarization treatment on the third detection layer to enable the upper surface of the third detection layer and the upper surface of the first medium layer to be positioned in the same plane.

2. The method of claim 1, wherein the semiconductor substrate is an SOI substrate, and further comprising, before forming the first dielectric layer on the upper surface of the semiconductor substrate:

forming the SOI substrate, wherein the SOI substrate comprises a silicon substrate, a buried oxide layer and a top silicon layer which are sequentially stacked from bottom to top;

and carrying out doping treatment on the top silicon layer to form an intrinsic region, an N-type lightly doped region positioned on one side of the intrinsic region, a P-type lightly doped region positioned on the other side of the intrinsic region, an N-type heavily doped region positioned on one side of the N-type lightly doped region far away from the intrinsic region and a P-type heavily doped region positioned on one side of the P-type lightly doped region far away from the intrinsic region, wherein the first groove is positioned right above the intrinsic region.

3. The method of claim 2, further comprising, after the surface planarization of the third detection layer:

forming a second medium layer on the upper surface of the third detection layer and the upper surface of the first medium layer;

forming a first through hole and a second through hole which penetrate through the first dielectric layer and the second dielectric layer, wherein the lower bottom surface of the first through hole is abutted against the N-type heavily doped region, and the lower bottom surface of the second through hole is abutted against the P-type heavily doped region;

filling a conductive material into the first through hole and the second through hole to form a first conductive plug and a second conductive plug;

and depositing a metal film on the upper surfaces of the first conductive plug and the second conductive plug to form a first contact electrode and a second contact electrode.

4. The method of claim 3, wherein the second dielectric layer is made of silicon dioxide and has a thickness of 200nm to 1000 nm;

the forming a second medium layer on the upper surface of the third detection layer and the upper surface of the first medium layer includes:

and forming the second medium layer on the upper surface of the third detection layer and the upper surface of the first medium layer by adopting a chemical vapor deposition process.

5. The method of claim 1, wherein the first dielectric layer is made of silicon dioxide and has a thickness of 1 to 4 microns;

the forming of the first dielectric layer on the upper surface of the semiconductor substrate comprises:

and forming the first dielectric layer on the upper surface of the semiconductor substrate by adopting a plasma enhanced chemical vapor deposition or low-pressure chemical vapor deposition process.

6. The method of claim 1, wherein etching the first dielectric layer comprises:

etching the first dielectric layer by adopting a dry etching process to form a second groove, wherein the depth of the second groove is smaller than the thickness of the first dielectric layer;

and etching the bottom of the second groove by adopting a wet etching process until the part of the upper surface of the semiconductor substrate is exposed.

7. The method of claim 6, wherein the wet etching process has an etching depth of 5 nm to 100 nm.

8. The method of claim 1, wherein the first probe layer is grown at a temperature of 300 to 400 degrees celsius, the second probe layer is grown at a temperature of 300 to 400 degrees celsius, and the third probe layer is grown at a temperature of 600 to 700 degrees celsius.

9. A germanium detector, comprising:

a semiconductor substrate;

the first dielectric layer is arranged on the upper surface of the semiconductor substrate;

the first groove is arranged in the first medium layer, and the depth of the first groove is matched with the thickness of the first medium layer;

the first detection layer is arranged at the bottom of the first groove, the first detection layer is made of germanium-silicon, and the thickness of the first detection layer is smaller than that of the first dielectric layer;

the second detection layer is arranged on the upper surface of the first detection layer, the second detection layer is made of germanium, and the sum of the thickness of the first detection layer and the thickness of the second detection layer is smaller than that of the first medium layer;

the third detection layer is arranged on the upper surface of the second detection layer and made of germanium, the growth temperature of the third detection layer is higher than that of the second detection layer, and the upper surface of the third detection layer and the upper surface of the first medium layer are located in the same plane.

10. The germanium detector as claimed in claim 9, wherein the first detection layer has a thickness of 10 nm to 50 nm, the second detection layer has a thickness of 10 nm to 50 nm, the third detection layer has a thickness of 300 nm to 3000 nm, and the germanium content in the silicon germanium is 30% to 70%.

Technical Field

The invention relates to the technical field of semiconductors, in particular to a germanium detector and a manufacturing method thereof.

Background

Nowadays, the technology fields such as information industry and biomedicine are more and more concerned, and novel photoelectron and optical communication technologies are inevitably developed at a faster speed. The silicon-based photoelectronic integration adopts a mature and cheap microelectronic processing technology to integrate an optical device with a microelectronic circuit with multiple functions, and is an effective way for realizing popularization and development of optical communication and optical interconnection. The silicon-based photoelectric detector is one of key devices of a silicon-based optical communication system, and with the breakthrough development of silicon-based germanium material epitaxy technology in recent years, the germanium detector becomes a hot spot of current research because of taking silicon-based photoelectron integration and efficient detection of optical communication wave bands into consideration.

In conventional germanium detectors, the germanium layer is grown directly on the substrate silicon layer, but since silicon and germanium have a 4.2% lattice mismatch, germanium is more prone to defects when grown on silicon, resulting in large dark current of the germanium detector, which affects the performance of the germanium detector.

Disclosure of Invention

The invention aims to solve the problem that a germanium detector manufactured by the prior art has large dark current.

The invention is realized by the following technical scheme:

a method of fabricating a germanium detector, comprising:

forming a first dielectric layer on the upper surface of the semiconductor substrate;

etching the first dielectric layer until part of the upper surface of the semiconductor substrate is exposed to form a first groove;

growing a first detection layer at the bottom of the first groove, wherein the first detection layer is made of germanium-silicon, and the thickness of the first detection layer is smaller than that of the first dielectric layer;

growing a second detection layer on the upper surface of the first detection layer, wherein the second detection layer is made of germanium, and the sum of the thickness of the first detection layer and the thickness of the second detection layer is smaller than that of the first medium layer;

growing a third detection layer on the upper surface of the second detection layer, wherein the third detection layer is made of germanium, and the growth temperature of the third detection layer is higher than that of the second detection layer;

and carrying out surface planarization treatment on the third detection layer to enable the upper surface of the third detection layer and the upper surface of the first medium layer to be positioned in the same plane.

Optionally, the semiconductor substrate is an SOI substrate, and before forming the first dielectric layer on the upper surface of the semiconductor substrate, the method further includes:

forming the SOI substrate, wherein the SOI substrate comprises a silicon substrate, a buried oxide layer and a top silicon layer which are sequentially stacked from bottom to top;

and carrying out doping treatment on the top silicon layer to form an intrinsic region, an N-type lightly doped region positioned on one side of the intrinsic region, a P-type lightly doped region positioned on the other side of the intrinsic region, an N-type heavily doped region positioned on one side of the N-type lightly doped region far away from the intrinsic region and a P-type heavily doped region positioned on one side of the P-type lightly doped region far away from the intrinsic region, wherein the first groove is positioned right above the intrinsic region.

Optionally, after the performing the surface planarization process on the third detection layer, the method further includes:

forming a second medium layer on the upper surface of the third detection layer and the upper surface of the first medium layer;

forming a first through hole and a second through hole which penetrate through the first dielectric layer and the second dielectric layer, wherein the lower bottom surface of the first through hole is abutted against the N-type heavily doped region, and the lower bottom surface of the second through hole is abutted against the P-type heavily doped region;

filling a conductive material into the first through hole and the second through hole to form a first conductive plug and a second conductive plug;

and depositing a metal film on the upper surfaces of the first conductive plug and the second conductive plug to form a first contact electrode and a second contact electrode.

Optionally, the second dielectric layer is made of silicon dioxide, and the thickness of the second dielectric layer is 200nm to 1000 nm;

the forming a second medium layer on the upper surface of the third detection layer and the upper surface of the first medium layer includes:

and forming the second medium layer on the upper surface of the third detection layer and the upper surface of the first medium layer by adopting a chemical vapor deposition process.

Optionally, the first dielectric layer is made of silicon dioxide, and the thickness of the first dielectric layer is 1 to 4 micrometers;

the forming of the first dielectric layer on the upper surface of the semiconductor substrate comprises:

and forming the first dielectric layer on the upper surface of the semiconductor substrate by adopting a plasma enhanced chemical vapor deposition or low-pressure chemical vapor deposition process.

Optionally, the etching the first dielectric layer includes:

etching the first dielectric layer by adopting a dry etching process to form a second groove, wherein the depth of the second groove is smaller than the thickness of the first dielectric layer;

and etching the bottom of the second groove by adopting a wet etching process until the part of the upper surface of the semiconductor substrate is exposed.

Optionally, the etching depth of the wet etching process is 5 nm to 100 nm.

Optionally, the growth temperature of the first detection layer is 300 to 400 degrees celsius, the growth temperature of the second detection layer is 300 to 400 degrees celsius, and the growth temperature of the third detection layer is 600 to 700 degrees celsius.

Based on the same inventive concept, the present invention also provides a germanium detector, comprising:

a semiconductor substrate;

the first dielectric layer is arranged on the upper surface of the semiconductor substrate;

the first groove is arranged in the first medium layer, and the depth of the first groove is matched with the thickness of the first medium layer;

the first detection layer is arranged at the bottom of the first groove, the first detection layer is made of germanium-silicon, and the thickness of the first detection layer is smaller than that of the first dielectric layer;

the second detection layer is arranged on the upper surface of the first detection layer, the second detection layer is made of germanium, and the sum of the thickness of the first detection layer and the thickness of the second detection layer is smaller than that of the first medium layer;

the third detection layer is arranged on the upper surface of the second detection layer and made of germanium, the growth temperature of the third detection layer is higher than that of the second detection layer, and the upper surface of the third detection layer and the upper surface of the first medium layer are located in the same plane.

Optionally, the thickness of the first detection layer is 10 nm to 50 nm, the thickness of the second detection layer is 10 nm to 50 nm, the thickness of the third detection layer is 300 nm to 3000 nm, and the content of germanium in the silicon germanium is 30% to 70%.

Compared with the prior art, the invention has the following advantages and beneficial effects:

according to the germanium detector and the manufacturing method thereof provided by the invention, when the detection layer is formed, firstly, germanium silicon is used as a buffer layer, then, the low-temperature germanium detection layer is formed on the germanium silicon detection layer, and finally, the high-temperature germanium detection layer is formed on the low-temperature germanium detection layer. Because germanium and silicon heteroepitaxy have 4.2% of lattice mismatch, the germanium is directly epitaxial on the silicon surface and the high dislocation defect is inevitably caused by the lattice mismatch, the germanium-silicon detection layer can be used for buffering, and the low-temperature germanium detection layer is used for limiting the defect on the low-temperature germanium detection layer, so that the high-quality epitaxy with the low dislocation defect is obtained, and the aim of reducing the dark current of the germanium detector is fulfilled.

Drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:

fig. 1 to 13 are schematic structural diagrams illustrating a manufacturing process of a germanium detector according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and accompanying drawings, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not meant to limit the present invention.