阅读说明：本技术 放大器及放大方法 (Amplifier and amplifying method ) 是由 林嘉亮 管继孔 于 2019-09-18 设计创作，主要内容包括：本申请涉及放大器和放大方法。放大器包括：第一类型的第一电流源、共源极增益装置、负载、第二类型的第二电流源、第一共模网络及第二共模网络。第一类型的第一电流源依据第一偏压从源极节点拉入第一偏压电流。共源极增益装置用以接收输入电压,并依据第一偏压电流以输出输出电流至漏极节点。负载用以提供终端于漏极节点。第二类型的第二电流源依据第二偏压以输出第二偏压电流至漏极节点。第一共模网络依据固定转导参考电流以输出第一偏压。第二共模网络依据漏极节点的电压平均值与调节参考电压之间的差值以输出第二偏压。(The present application relates to an amplifier and an amplifying method. The amplifier includes: the current source circuit comprises a first current source of a first type, a common source gain device, a load, a second current source of a second type, a first common mode network and a second common mode network. A first current source of a first type pulls a first bias current from the source node in accordance with a first bias voltage. The common-source gain device is used for receiving an input voltage and outputting an output current to a drain node according to a first bias current. The load is used for providing a terminal at the drain node. The second current source of the second type outputs a second bias current to the drain node according to a second bias voltage. The first common mode network outputs a first bias voltage according to a fixed transconductance reference current. The second common mode network outputs a second bias voltage according to a difference between the average voltage value of the drain node and the regulated reference voltage.)

1. An amplifier, comprising:

a first current source of a first type drawing a first bias current from a source node in accordance with a first bias voltage;

a common source gain device for receiving an input voltage and outputting an output current to a drain node according to the first bias current outputted from the source node;

a load for providing a terminal at the drain node;

a second current source of a second type for outputting a second bias current to the drain node according to a second bias voltage;

a first common mode network for outputting the first bias voltage according to a fixed transconductance reference current; and

a second common mode network for outputting the second bias voltage according to a difference between a voltage average value of the drain node and an adjustment reference voltage adjusted by a bandgap reference voltage.

2. The amplifier of claim 1, wherein the first common mode network comprises:

a diode-connected transistor for establishing the first bias voltage in a current-to-voltage conversion manner according to the constant transconductance current.

3. The amplifier of claim 1, wherein the first common mode network comprises:

a common source transistor including a gate terminal and a first drain terminal;

a cascode transistor including a second drain terminal, the cascode transistor configured to deliver the fixed transconductance reference current to the common-source transistor and to establish the first bias voltage according to a feedback signal from the second drain terminal of the cascode transistor to the gate terminal of the common-source transistor; and

an operational amplifier for outputting a control voltage to control the gate terminal of the cascode transistor according to a difference between a voltage at the first drain terminal of the common-source transistor and a second average voltage value at the source node.

4. The amplifier of claim 1, wherein the second common mode network comprises:

a voltage regulating circuit for receiving the bandgap reference voltage and outputting the regulated reference voltage; and

a first operational amplifier for outputting the second bias voltage according to a difference between the regulated reference voltage and the average voltage value of the drain node.

5. The amplifier of claim 4, wherein the voltage regulation circuit comprises:

a transistor, comprising:

a source terminal;

a drain terminal; and

a gate terminal;

a first resistor for coupling the source terminal of the transistor to a first DC node;

a second resistor for coupling the drain terminal of the transistor to a second DC node; and

a second operational amplifier for outputting a control voltage to control the gate terminal of the transistor according to a difference between the bandgap reference voltage and a voltage of the source terminal of the transistor.

6. The amplifier of claim 5, wherein the regulated reference voltage is obtained from the drain terminal of the transistor.

7. The amplifier of claim 1, wherein the first current source of the first type comprises: a transistor of a first type, the transistor of the first type comprising:

a gate terminal controlled by the first bias voltage; and

a drain terminal coupled to the source node.

8. The amplifier of claim 1, wherein the second current source of the second type comprises:

a second transistor of a second type; and

an isolation resistor.

9. The amplifier of claim 8, wherein the second transistor of the second type comprises:

a gate terminal controlled by the second bias voltage; and

a drain terminal coupled to the drain node through the isolation resistor.

10. A method of amplification, comprising:

conducting a first bias current from a source node using a first current source of a first type in accordance with a first bias voltage;

converting an input voltage to an output current delivered to a drain node using a common source gain device based on the first bias current output from the source node;

using a load as a terminal of the drain node;

conducting a second bias current to a drain node using a second current source of a second type according to a second bias voltage;

adjusting the first bias voltage in a current-to-voltage conversion manner according to a fixed transduction reference current;

generating a regulated reference voltage according to regulation of a bandgap reference voltage; and

the second bias voltage is adjusted according to a difference between the regulated reference voltage and a voltage average of the drain node.

Technical Field

The present disclosure relates to amplifiers, and more particularly, to amplifiers and methods thereof that maintain both gain and effective output swing stability over temperature variations.

Background

Referring to fig. 1A, a conventional high-speed amplifier 100 includes: current source 110, gain device 120, load 130. The current source 110 includes two N-type transistors 111p, 111N. N-type transistors 111p, 111N are based onBias voltage V_bcmTwo bias currents I are respectively drawn from two source nodes 101p, 101n_bp、I_bn. The gain device 120 includes two N-type transistors 121p, 121N and two source-degeneration resistors 122p, 122N. The gain device 120 is used for receiving two input voltages V_ip、V_inAnd according to the bias current I_bp、I_bnThe determined bias conditions output two output voltages V at the two drain nodes 102p, 102n, respectively_op、V_on. The load 130 includes two pull-up resistors (pull-up resistors) 131p, 131 n. Pull-up resistors 131p, 131n for respectively pulling up the voltages of the two drain nodes 102p, 102n to the power supply node V_DD。

Functionally, the amplifier 100 receives an input signal V_iInput signal V_iIs a differential signal comprising two input voltages Vip and Vin. And the amplifier 100 outputs an output signal V_oOutput signal V_oIs a voltage converter comprising two output voltages V_op、V_onThe differential signal of (2). The gain device 120 is based on a common-source layout (topology) and depends on two bias currents I_bp、I_bnProviding a gain. Herein, gain refers to the output signal V_oAnd an input signal V_iAmplitude ratio therebetween. The amplifier 100 is well known in the art and will not be described in detail herein.

The two voltages included in the differential signal are denoted by two subscripts "p" and "n", respectively. For example an input signal V_iComprising two input voltages V_ip、V_inAnd output signal V_oComprising two output voltages V_op、V_on. Amplifier 100 includes two portions, a first half and a second half. All voltages, currents, elements, and nodes in the first half are represented by the subscript "n". And all voltages, currents, elements, and nodes in the second half are represented by the subscript "p". The two halves are nominally identical and perform the same function, except that the first half receives an input voltage V_ipAnd outputs an output voltage V_opAnd the second half receives an input voltage V_inAnd outputs an output voltage V_on. In addition, two nodes labeled "101 cm", "102 cm" are shared by the first and second halves, and these two nodes are referred to as "common mode nodes" and are represented by the subscript "cm". And, a bias voltage V_bcmAlso shared by the first and second halves, which is why the subscript "cm" is also used. Because the two halves are identical, it is convenient to represent both halves with only one of the halves. By representing both halves with only one of them and removing the subscripts "p" and "n" but leaving the subscript "cm", the result is an amplifier 100h, as shown in fig. 1B. Fig. 1B is a diagram showing a half circuit of the amplifier 100 in fig. 1A.

Referring to fig. 1B, the function of the half circuit is further explained. The amplifier 100h includes: the current source 110h includes an N-type transistor 111, a gain device 120h, and a load 130 h. The N-type transistor 111 is biased according to a bias voltage V_bcmPulling in bias current I from source node 101_b. The gain device 120h includes an N-type transistor 121 and a source degeneration resistor 122. The gain device 120h is used for receiving an input signal V_iAnd according to the bias current I_bOutput signal V at drain node 102_o. The load 130h includes a pull-up resistor 131. Pull-up resistor 131 is used to pull up drain node 102 to power supply node V_DDAnd thus provides a terminal at drain node 102.

Amplifier 100h has two important characteristics, gain and effective output swing, respectively. The gain is determined by the product of the transconductance of the common-source gain device 120h and the impedance of the load 130 h. Effective output swing is provided by power supply node V_DDAnd an output signal V_oIs determined by the difference between the mean values of (a) and (b). It is desirable that amplifier 100h maintain substantially the same gain and effective output swing even when circuit temperature changes. Unfortunately, the transconductance of gain device 120h is highly temperature dependent and can be scaled by a factor of two for the same bias current as the temperature is increased from-40 degrees celsius (c) to 125 degrees celsius. To maintain the same gain, the bias current I_bMust be based onThe temperature is adjusted. On the other hand, if the bias current I_bAdjusted to maintain the same gain, the effective output swing will vary with temperature.

Therefore, it is desirable to have an amplifier that maintains gain and effective output swing over temperature variations.

Disclosure of Invention

According to some embodiments, an amplifier includes a first current source of a first type, a common-source gain device, a load, a second current source of a second type, a first common-mode network, and a second common-mode network. A first current source of a first type pulls a first bias current from the source node in accordance with a first bias voltage. The common-source gain device is used for receiving an input voltage and outputting an output current to a drain node according to a first bias current. The load is used for providing a terminal at the drain node. The second current source of the second type outputs a second bias current to the drain node according to a second bias voltage. The first common mode network outputs a first bias voltage according to a fixed transconductance reference current. The second common mode network outputs a second bias voltage according to a difference between the average voltage value of the drain node and the regulated reference voltage.

According to some embodiments, the amplification method comprises the steps of: conducting a first bias current from the source node using a first current source of a first type in dependence on the first bias voltage; converting an input voltage into an output current delivered to a drain node using a common source gain device according to a first bias current output from a source node; a terminal using a load as a drain node; conducting a second bias current to the drain node using a second current source of a second type in accordance with a second bias voltage; adjusting a first bias voltage in a current-to-voltage conversion manner according to the fixed transduction reference current; generating an adjustment reference voltage according to the adjustment of the energy gap reference voltage; and adjusting the second bias voltage according to a difference between the regulated reference voltage and the average value of the voltages of the drain nodes.

Drawings

Various aspects of the disclosure may be better understood with reference to the following drawings. The components in the figures are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present disclosure, both in construction and in operation. And like reference numerals designate corresponding parts throughout the several views of the drawings.

Fig. 1A is a schematic diagram of a conventional amplifier.

Fig. 1B is a schematic diagram of a half-circuit diagram of the conventional amplifier of fig. 1A.

Fig. 2A is a schematic diagram of an amplifier in a half-circuit representation according to some embodiments of the present disclosure.

Fig. 2B is a schematic diagram of an amplifier represented by a half-circuit of the alternate embodiment of fig. 2A.

Fig. 3 is a flow chart of a magnification method of some embodiments of the present disclosure.

Description of the symbols

100. 100h amplifier 110, 110h current source

120. 120h gain device 130, 130h load

111. 111p, 111n, 121p, 121n N type transistor

122. 122p, 122n source degeneration resistance

102. 102p, 102n drain node

131. 131p, 131n pull-up resistor

101cm and 102cm common mode node

101. 101p, 101n source node

200A Amplifier 200B Amplifier

210h first current source 220h common source gain device

230h load 240h second current source

250cm tile 260cm tile

251cm shunt capacitor 261cm shunt capacitor

270cm first common mode network 280cm second common mode network

201 source node 202 drain node

201cm first common mode node 202cm second common mode node

211N-type transistor 221N-type transistor

222 source degeneration resistor 231 pull-up resistor

232 common mode sense resistor 241P-type transistor

242 isolation resistor 271N-type transistor

272N type transistor 273N type transistor

275cm substitute common mode network for 274 operational amplifier

281 operational amplifier 282 operational amplifier

283N type transistor 286 voltage regulating circuit

R₁Resistor R₂Resistor with a resistor element

V_b1cmA first bias voltage V_b2cmSecond bias voltage

V_scmA first common mode voltage V_dcmSecond common mode voltage

V_DD1Power supply node V_DD2Second power supply node

V_bgrefEnergy gap reference voltage V_refRegulating a reference voltage

V_dTerminal voltage V of drain electrode_sVoltage at source terminal

V_gInput voltage V_midVoltage at the second drain terminal

V_ctlControl voltage V_bcmBias voltage

V_ip、V_inInput voltage V_op、V_onOutput voltage

V_iInput signal V_oOutput signal

V_DDPower supply node I_cgrefFixed transduction reference current

I_b1A first bias current I_b2Second bias current

I_dOutput current I_b、I_bp、I_bnBias current

310-370 step

Detailed Description

The present disclosure relates to amplifiers. While several preferred modes of carrying out the disclosure are described in the specification, it is to be understood that the disclosure may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth below or to specific ways to practice the features described below. In other instances, well-known details will not be set forth or discussed in order to avoid obscuring the focus of the present disclosure.

Those skilled in the art should understand the terms and basic concepts related to microelectronics used in the present disclosure, such as "node", "circuit node", "signal", "voltage", "current", "transconductance", "amplifier", "differential signal", "common-mode", "current mirror", "bandgap reference", "fixed-gm current", "bias voltage", "capacitor", "capacitance", "resistor", "resistance", "complementary metal oxide semiconductor", "P-type transistor", "N-type transistor (NMOS)", "channel length modulation (channel length modulation)", "impedance", "common-source amplifier", "series (channel)", and the like, "source degeneration", "operational amplifier", and "negative feedback". Terms and basic concepts like those described above are well known to those skilled in the art and will not be explained in detail herein. One skilled in the art can also recognize the circuit symbols for the P-type transistor and the N-type transistor and can distinguish which is the "source", "gate" and "drain".

The present disclosure is expressed from an engineering perspective (i.e., from the perspective of one skilled in the art), rather than from a strict mathematical perspective. For example, "X equals Y" means "the difference between X and Y is less than a certain engineering/practical tolerance error" rather than requiring a theoretical/mathematical absolute equality. "X is significantly less than Y" means that the ratio between X and Y is less than a specified engineering/practical tolerance.

In the present disclosure, the power supply node is considered to be a dc node because the voltage of the power supply node is substantially fixed. Likewise, the ground node is also a dc node.

In this disclosure, the word "coupled" and its derivatives may be used. In some embodiments, "coupled" may be used to indicate that two or more elements are in direct physical or electrical contact with each other, or may also mean that two or more elements are in direct electrical contact with each other. The term "coupled" may still be used to indicate that two or more elements co-operate or interact with each other.

In the present disclosure, a differential signal is used, wherein the voltage signal includes a first voltage and a second voltage, and the current signal includes a first current and a second current. Also, differential circuits are used in some embodiments of the present disclosure. The differential circuit comprises a first half part, a second half part and a common mode network shared by the first half part and the second half part. The first and second halves are identical except that they process a first portion of the signal (voltage or current) and a second portion of the signal (voltage or current), respectively. For the sake of brevity, the description will be made using half-circuits of differential circuits, where the circuit blocks associated with the half-circuits are represented by the subscript "h", the circuit blocks associated with the common-mode network are represented by the subscript "cm", and the subscripts "p" and "n" are not used. For example, the amplifier 100h in fig. 1B represents a half circuit of the amplifier 100 in fig. 1A. The gain device 120h in fig. 1B represents a half circuit of the gain device 120 in fig. 1A. The load 130h in fig. 1B represents a half circuit of the load 130 of fig. 1A.

Fig. 2A is a schematic diagram of an amplifier 200A in a half-circuit representation of some embodiments of the present disclosure. Referring to fig. 2A, in some embodiments, the amplifier 200A includes a first current source 210h, a common source gain device 220h, a load 230h, a second current source 240h, a first common mode network 270cm, and a second common mode networkCollaterals are 280 cm. Wherein the first current source 210h includes an N-type transistor 211. The first current source 210h is biased according to a first bias voltage V_b1cmPulling a first bias current I from source node 201_b1. In some embodiments, common-source gain device 220h includes an N-type transistor 221 and a source degeneration resistor 222. The common source gain device 220h is used for receiving an input voltage V_gAnd according to the first bias current I outputted from the source node 201_b1Determined bias condition, pulling output current I from drain node 202_d. Wherein the source degeneration resistor 222 is used for coupling the source node 201 to the first common mode node 201cm and obtaining a first common mode voltage V at the first common mode node 201cm_scm. Load 230h is used to provide a terminal at drain node 202. The load 230h includes a pull-up resistor 231 and a common mode sense resistor 232. Pull-up resistor 231 for pulling up the voltage of drain node 202 to power supply node V_DD1. The common mode sense resistor 232 is used to couple the drain node 202 to a second common mode node 202cm, and obtain a second common mode voltage V at the second common mode node 202cm_dcm. The second current source 240h includes a P-type transistor 241 and an isolation resistor 242. The second current source 240h is biased according to a second bias voltage V_b2cmFrom the second supply node V_DD2Output a second bias current I_b2To drain node 202. The first common mode network 270cm is based on a constant-gm reference current (I)_cgrefTo establish a first bias voltage V_b1cm. The second common mode network 280cm is used for receiving a second common mode voltage V at a second common mode node 202cm_dcmAnd according to the bandgap reference voltage V_bgrefOutput a second bias voltage V_b2cm。

In some embodiments, the amplifier 200A also includes a shunt capacitor 251cm (shown in block 250 cm). Shunt capacitor 251cm for voltage V at first common mode_scmProviding low pass filtering such that the first common mode voltage V_scmSubstantially equal to the voltage V at the source terminal_sAverage value of (a). In one embodiment, shunt capacitor 251cm comprises a parasitic capacitor.

In some embodiments, the amplifier 200A also includes a shunt capacitor 261cm (shown in block 260 cm). Shunt capacitor 261cm for second common modeVoltage V_dcmProviding low pass filtering so that the second common mode voltage V_dcmSubstantially equal to the drain terminal voltage V_dAverage value of (a). In one embodiment, the shunt capacitor 261cm comprises a parasitic capacitor.

In some embodiments, an isolation resistor 242 is employed to provide isolation between the drain terminal of the P-type transistor 241 and the drain node 202 to mitigate the effect of the parasitic capacitance of the P-type transistor 241 on the drain node 202. Otherwise, the parasitic capacitance may introduce an undesirably large capacitive load at drain node 202.

In some embodiments, the bandgap reference voltage V_bgrefAbout 1.23V and is highly accurate and insensitive to temperature. This part is well known in the art and will not be described in detail herein.

In some embodiments, the second common mode network 280cm includes a voltage regulation circuit 286 and an operational amplifier 282. The voltage regulating circuit 286 is used for receiving the bandgap reference voltage V_bgrefAnd outputs a regulated reference voltage V_ref. The operational amplifier 282 is based on the second common mode voltage V_dcmAnd regulating the reference voltage V_refThe difference therebetween to output a second bias voltage V_b2cm. The load 230h, the second common mode network 280cm and the second current source 240h form a negative feedback loop. When the second common mode voltage V_dcmAbove the regulation reference voltage V_refWhile the operational amplifier 282 will force the second bias voltage V_b2cmRises to cause the P-type transistor 241 to reduce the second bias current I_b2And thus the drain terminal voltage V_dAnd a second common mode voltage V_dcmAnd (4) descending. When the second common mode voltage V_dcmBelow the regulated reference voltage V_refWhile the operational amplifier 282 will force the second bias voltage V_b2cmDecreases to cause the P-type transistor 241 to increase the second bias current I_b2And thus the drain terminal voltage V_dAnd a second common mode voltage V_dcmAnd (4) rising. Thus, the negative feedback loop may force the second common mode voltage V_dcmFollowed by regulation of the reference voltage V_refFor example:

V_dcm＝V_ref。 (1)

the voltage regulating circuit 286 includes an operational amplifier 281, an N-type transistor 283, and two resistors R1, R2. The resistors R1, R2 are laid out in negative feedback such that:

the voltage regulating circuit 286 is an operational amplifier type feedback circuit widely used in the former case, and how to derive the equation (2) is well known to those skilled in the art, so it is not explained in detail herein.

Combining equation (1) and equation (2) yields:

as mentioned above, the second common mode voltage V_dcmIs equal to the drain terminal voltage V_dAverage value of (a). Due to the drain terminal voltage V_dCan swing up to power supply node V_DD1Thus "V_DD1-V_dcmIs the drain terminal voltage V_dThe effective swing of (a). Due to the energy gap reference voltage V_bgrefIs highly accurate and temperature insensitive, as in the aforementioned "R₂/R₁", the effective output swing of amplifier 200A may be highly accurate and insensitive to temperature.

The fixed transconductance current is a current used to bias a transistor, which may have a transconductance with high accuracy and insensitive to temperature. The first common mode network 270cm includes an N-type transistor 271. The N-type transistor 271 is used for receiving the constant transconductance reference current I in the diode-connected layout_cgrefAnd converting it into a first bias voltage V_b1cmTo control the N-type transistor 211. The N-type transistor 271 and the N-type transistor 211 form a current mirror to make the first bias current I_b1By fixing the transduction reference current I_cgrefThe scaling factor of the adjusted current is determined by the ratio of the width-to-length ratio of the N-type transistor 211 to the width-to-length ratio of the N-type transistor 271. Thus, the first bias current I_b1Also fixed transduction current. Since the common-source gain device 220h is biased by a fixed transconductance current, the common-source gain device 220h can have a transconductance with high accuracy and insensitive to temperature. The gain of the amplifier 200A can be highly accurate and insensitive to temperature.

Overall, the gain of the amplifier 200A may be highly accurate and insensitive to temperature due to the use of the first common mode network 270 m. While the effective output swing of amplifier 200A may be highly accurate and temperature insensitive due to the use of the second common mode network 280 m.

In some embodiments, the P-type transistor 241 is replaced by an N-type transistor and the input polarities of the operational amplifier 282 are swapped. In such a configuration, the load 230h, the second common mode network 280cm, and the second current source 240h still constitute a negative feedback loop, and the effective output swing of the amplifier 200A may still be highly accurate and temperature insensitive.

Note that the source degeneration resistor 222 may also perform the function of common mode sensing. Also, in a special case, the source degeneration resistor 222 is 0 ohm, i.e., short-circuited.

Fig. 2B is a schematic diagram of an amplifier 200B in half-circuit representation of the alternate embodiment of fig. 2A. Referring to fig. 2B, in some embodiments, the accuracy of the current mirror implemented with N-type transistors 271 and 211 is degraded by the channel length modulation effect of N-type transistor 211. For example, the voltage at the source terminal V_sIs lower than the first bias voltage V_b1cmWhile a first bias current I_b1Will be lower than the expected ideal current mirror because the drain-to-source voltage difference of the N-type transistor 211 is lower than that of the N-type transistor 271. Or, the voltage at the source terminal V_sIs higher than the first bias voltage V_b1cmWhile a first bias current I_b1Will be higher than the expected ideal current mirror because the difference in drain-to-source voltages of the N-type transistor 211 is higher than the difference in drain-to-source voltages of the N-type transistor 271. Voltage at source terminal V_sIs sensed by the source degeneration resistor 222 and is supplied by a first common mode voltage V at a first common mode node 201cm_scmAnd (4) representing. To reduceThe channel length modulation effect of the light N-type transistor 211 may use an alternative embodiment of the amplifier 200B as shown in fig. 2B. Amplifier 200B is similar to amplifier 200A of fig. 2, except that the common mode network 270cm in fig. 2A is replaced by the alternate common mode network 275cm in fig. 2B. The alternative common mode network 275cm includes: an N-type transistor 272 in a common source configuration, an N-type transistor 273 in a series configuration, and an operational amplifier 274. The N-type transistor 272 is used for establishing a first bias voltage V_b1cmAnd constitutes a current mirror together with the N-type transistor 211. The N-type transistor 273 is a cascode device and is used to conduct a constant transconductance reference current I_cgrefTo the N-type transistor 272. The operational amplifier 274 according to the voltage V of the second drain terminal_mid(i.e., the voltage at the drain terminal of the N-type transistor 272) and a first common mode voltage V_scmDifference between them to output a control voltage V_ctlWherein the voltage V is controlled_ctlThe gate terminal of the N-type transistor 273 is controlled. When the voltage at the source terminal V_sIs higher than the second drain terminal voltage V_midWhile, the operational amplifier 274 will force the control voltage V_ctlAnd (4) descending. The first bias voltage V is caused by the inverting function of the N-type transistor 273_b1cmAnd (4) rising. And due to the inverting function of the N-type transistor 211, the source terminal voltage V is caused_sThe average voltage of (2) decreases. Or, when the source terminal voltage V_sIs lower than the second drain terminal voltage V_midWhile, the operational amplifier 274 will force the control voltage V_ctlAnd (4) rising. The first bias voltage V is caused by the inverting function of the N-type transistor 273_b1cmAnd (4) descending. And due to the inverting function of the N-type transistor 211, the source terminal voltage V is caused_sThe average voltage of (2) rises. Thus, the first bias voltage V is adjusted with negative feedback instead of a 275cm implementation of the common mode network_b1cmAnd making the voltage V at the source terminal_sIs equal to the second drain terminal voltage V_mid. Therefore, the N-type transistor 272 and the N-type transistor 211 not only have the same gate-to-source voltage difference, but also have the same drain-to-source voltage difference, thereby eliminating the current mirror inaccuracy caused by the channel length modulation effect and allowing high accuracy current mirror.

Fig. 3 is a flow chart of a magnification method of some embodiments of the present disclosure. Referring to fig. 3, in some embodiments, a magnification method includes the steps of: according to a first bias voltage V_b1cmConducting a first bias current I from a source node using a first current source of a first type_b1(step 310); according to a first bias current I output from a source node_b1Using a common source gain device to convert an input voltage V_gConverted to an output current I delivered to drain node 202_d(step 320); using the load as a terminal of drain node 202 (step 330); according to a second bias voltage V_b2cmConducting a second bias current I using a second current source of a second type_b2To drain node 202 (step 340); according to a fixed transduction reference current I_cgrefAdjusting the first bias voltage V in a current-to-voltage conversion manner_b1cm(step 350); according to the bandgap reference voltage V_bgrefGenerating a regulated reference voltage V_ref(step 360); and, adjusting the reference voltage V_refThe difference between the average voltage of the drain node 202 to adjust the second bias voltage V_b2cm(step 370).

Although the present disclosure has been described with reference to the preferred embodiments, it should be understood that various changes and modifications can be made without departing from the spirit and scope of the disclosure as defined by the appended claims.