阅读说明：本技术 一种igbt器件结构及其制备方法 (IGBT device structure and preparation method thereof ) 是由 程炜涛 程庆彪 潘克学 于 2020-07-03 设计创作，主要内容包括：本发明提供一种IGBT器件结构及其制备方法,属于半导体功率器件与工艺制造技术领域。该IGBT器件结构及其制备方法包括N-衬底、超结区、元胞、FS层、P+层、N+层、填充层。本发明中的N-衬底、超结区、元胞、FS层、P+层、N+层可以保障器件耐压,还通过在N-衬底上设置第一安装槽,并在第一安装槽内填充第一绝缘层,第一绝缘层通过高K绝缘材料制成,从而起到在器件开通时,提高FS层中空穴载流子密度,有效地隔离了IGBT区域和MOSFET区域,从而有效降低器件导通电阻,抑制器件开通时的snapback现象。(The invention provides an IGBT device structure and a preparation method thereof, belonging to the technical field of semiconductor power devices and process manufacturing. The IGBT device structure and the preparation method thereof comprise an N-substrate, a super junction region, a cell, an FS layer, a P + layer, an N + layer and a filling layer. The N-substrate, the super junction region, the cellular, the FS layer, the P + layer and the N + layer can guarantee the voltage resistance of the device, the first installation groove is formed in the N-substrate, the first installation groove is filled with the first insulation layer, and the first insulation layer is made of high-K insulation materials, so that when the device is switched on, the hole carrier density in the FS layer is improved, an IGBT (insulated gate bipolar transistor) region and an MOSFET (metal oxide semiconductor field effect transistor) region are effectively isolated, the on-resistance of the device is effectively reduced, and the snapback phenomenon when the device is switched on is restrained.)

1. An IGBT device structure characterized in that: the solar cell super junction structure comprises an N-substrate (1), a super junction area arranged on the N-substrate (1), a cell arranged at the upper end of the super junction area, an FS layer (11) arranged at the lower end of the N-substrate (1), a P + layer (12) arranged at the lower end of the N-substrate (1), an N + layer (14) arranged at the lower end of the N-substrate (1) and a filling layer arranged on the N-substrate (1), wherein the filling layer comprises a first mounting groove (15) arranged on the N-substrate (1) and a first insulating layer (13) filled in the first mounting groove (15).

2. An IGBT device structure as claimed in claim 1, characterized in that: the number of the first mounting grooves (15) is 2, the 2 first mounting grooves (15) are arranged in parallel, and the 2 first mounting grooves (15) are symmetrically arranged on two sides of the central line of the N-substrate (1).

3. An IGBT device structure as claimed in claim 1 or 2, characterized in that: the super junction region is a P/N super junction region formed by P-type regions (2) and N-type regions (3) alternately.

4. An IGBT device structure as claimed in claim 3, characterized in that: the P/N surpasses knot district and sets up in the middle part of N-substrate (1), FS layer (11) set up in the lower extreme of P/N surpasses knot district, P + layer (12) set up in the middle part of FS layer (11) lower extreme, N + layer (14) set up in the both sides of FS layer (11) lower extreme, first mounting groove (15) top sets up in P/N surpasses knot district, the bottom sets up in the bottom of N-substrate (1), P + layer (12) and N + layer (14) set up respectively in the both sides of first mounting groove (15).

5. An IGBT device structure as claimed in claim 4, characterized in that: the cell comprises a second mounting groove (4) arranged at the upper end of the P/N super-junction area, a gate electrode (6) arranged in the second mounting groove (4), a P-type body area (7) arranged at the upper end of the P/N super-junction area, a P + area (8) arranged at the upper end of the P/N super-junction area, an N + source area (9) arranged at the upper end of the second mounting groove (4), and a metal layer (10) arranged on the N + source area (9).

6. An IGBT device structure as claimed in claim 5, characterized in that: and a second insulating layer (5) is arranged on the inner side of the second mounting groove (4), and the gate electrode (6) is arranged on the inner side of the second insulating layer (5).

7. An IGBT device structure as claimed in claim 5, characterized in that: second mounting groove (4) set up in the middle part of P/N super junction district upper end, the central line of second mounting groove (4) and the coincidence of the central line of N-substrate (1), the central line of N + source district (9) and the coincidence of the central line of second mounting groove (4), P type somatic region (7) are 2, 2P type somatic region (7) symmetry sets up in the both sides of second mounting groove (4), P + region (8) are 2, P + region (8) bottom is connected in P type somatic region (7), one end is connected in N + source district (9).

8. The preparation method of the IGBT device structure of claim 1, characterized by comprising the following steps:

s1: preparing an N-substrate (1) by adopting an N semiconductor material;

s2: preparing a P/N super junction area formed by alternately forming a P type area (2) and an N type area (3) in the middle of an N-substrate (1);

s3: preparing a first mounting groove (15) on the back surface of the N-substrate (1) at the part from the P/N super junction area to the bottom end, and filling a first insulating layer (13) in the first mounting groove (15);

s4: respectively preparing an FS layer, a P + layer, an N + layer and a unit cell on an N-substrate.

9. The method for manufacturing an IGBT device structure according to claim 8, characterized in that: step S4 specifically includes: and injecting an N + to prepare an FS layer (11) at the lower end of the P/N super junction region on the N-substrate (1), and injecting an N + to prepare a P + layer (12) and an N + layer (14) respectively at the lower end of the FS layer (11) on the N-substrate (1).

10. The method for manufacturing an IGBT device structure according to claim 8 or 9, wherein the step of manufacturing the unit cell in step S4 specifically includes the steps of: preparing a second mounting groove (4) on the N-substrate (1); depositing a second insulating layer (5) on the inner side wall of the second mounting groove (4); filling polycrystalline silicon into the second mounting groove (4) positioned on the inner side of the second insulating layer (5) to form a gate electrode (6); respectively preparing a P-type body region (7), an N + source region (9) and a P + region (8) on the N-substrate (1) at the upper end of the P/N super junction region; depositing different interlayer media, and forming a contact hole through photoetching and dry etching; and depositing a metal layer (10) on the upper end of the N + source region (9), and photoetching and dry etching the metal layer (10) to form a pattern.

Technical Field

The invention belongs to the technical field of semiconductor power devices and process manufacturing, and relates to an IGBT device structure and a preparation method thereof.

Background

The IGBT is named as an insulated gate bipolar transistor in Chinese, is a Darlington structure formed by combining a field effect transistor MOSFET and a bipolar power transistor BJT, has the advantages of high input impedance, simple driving and high switching speed of the MOSFET, has the advantages of high current density, low saturation voltage and strong current processing capacity of the BJT, is an ideal fully-controlled device, has frequency characteristics between the MOSFET and the power transistor, and can normally work in a frequency range of dozens of kHz. Since the invention, the insulated Bipolar Transistor igbtacross Gate Bipolar Transistor has become the mainstream switching device in the field of medium and high power electronics due to its superior switching characteristics, and is widely applied to the fields of consumer electronics, industry, rail transit, new energy vehicles, energy power generation and the like. Compared with a common trench IGBT, the existing semi-super-junction IGBT structure has better voltage withstanding property. Since the reverse withstand voltage capability of the IGBT is weak, in practical applications, it is necessary to connect a diode in anti-parallel to play a freewheeling role when the IGBT is turned off. Clearly, if the IGBT and the diode can be designed in the same device structure, the cost will be greatly saved, and the IGBT and the FRD will have better matching property, but such a structure will usually cause the negative resistance snapback phenomenon at the time of turning on.

Disclosure of Invention

Aiming at the problems in the prior art, the invention provides an IGBT device structure and a preparation method thereof, and the technical problems to be solved by the invention are as follows: how to provide an IGBT device structure and a preparation method thereof.

The purpose of the invention can be realized by the following technical scheme:

an IGBT device structure comprises an N-substrate, a super junction area arranged on the N-substrate, a cellular arranged at the upper end of the super junction area, an FS layer arranged at the lower end of the N-substrate, a P + layer arranged at the lower end of the N-substrate, an N + layer arranged at the lower end of the N-substrate and a filling layer arranged on the N-substrate, wherein the filling layer comprises a first mounting groove arranged on the N-substrate and a first insulating layer filled in the first mounting groove.

Preferably, the number of the first installation grooves is 2, 2 first installation grooves are arranged in parallel, and the 2 first installation grooves are symmetrically arranged on two sides of the center line of the N-substrate.

Preferably, the super junction region is a P/N super junction region alternately formed of a P-type region and an N-type region.

Preferably, the P/N super-junction area is arranged in the middle of the N-substrate, the FS layer is arranged at the lower end of the P/N super-junction area, the P + layer is arranged in the middle of the lower end of the FS layer, the N + layer is arranged on two sides of the lower end of the FS layer, the top end of the first mounting groove is arranged in the P/N super-junction area, the bottom end of the first mounting groove is arranged at the bottom end of the N-substrate, and the P + layer and the N + layer are respectively arranged on two sides of the first mounting groove.

Preferably, the cell comprises a second mounting groove arranged at the upper end of the P/N super-junction region, a gate electrode arranged in the second mounting groove, a P-type body region arranged at the upper end of the P/N super-junction region, a P + region arranged at the upper end of the P/N super-junction region, an N + source region arranged at the upper end of the second mounting groove, and a metal layer arranged on the N + source region.

Preferably, a second insulating layer is arranged on the inner side of the second mounting groove, and the gate electrode is arranged on the inner side of the second insulating layer.

Preferably, the second mounting groove is arranged in the middle of the upper end of the P/N super-junction area, the center line of the second mounting groove coincides with the center line of the N-substrate, the center line of the N + source area coincides with the center line of the second mounting groove, the number of the P-type body areas is 2, 2P-type body areas are symmetrically arranged on two sides of the second mounting groove, the number of the P + area is 2, the bottom end of the P + area is connected with the P-type body area, and one end of the P + area is connected with the N + source area.

The method for preparing an IGBT device structure according to claim 1, comprising the steps of:

s1: preparing an N-substrate by adopting an N semiconductor material;

s2: preparing a P/N super junction region formed by alternately forming a P type region and an N type region in the middle of an N-substrate;

s3: preparing a first mounting groove on the back surface of the N-substrate from the P/N super junction region to the bottom end, and filling a first insulating layer in the first mounting groove;

s4: respectively preparing an FS layer, a P + layer, an N + layer and a unit cell on an N-substrate.

Preferably, step S4 specifically includes: and injecting an N + preparation FS layer at the lower end of the P/N super junction region on the N-substrate, and injecting an N + preparation P + layer and an N + preparation N + layer at the lower end of the FS layer on the N-substrate.

Preferably, the preparation of the unit cell in the step S4 specifically includes the following steps: preparing a second mounting groove on the N-substrate; depositing a second insulating layer on the inner side wall of the second mounting groove; filling polysilicon on the inner side of the second insulating layer in the second mounting groove to form a gate electrode; respectively preparing a P-type body region, an N + source region and a P + region on the N-substrate at the upper end of the P/N super junction region; depositing different interlayer media, and forming a contact hole through photoetching and dry etching; and depositing a metal layer at the upper end of the N + source region, and photoetching and dry etching the metal layer to form a pattern.

The invention has the following beneficial effects: 1. the N-substrate, the super junction region, the cellular, the FS layer, the P + layer and the N + layer can guarantee the voltage resistance of the device, a first mounting groove is formed in the N-substrate, a first insulating layer is filled in the first mounting groove, and the first insulating layer is made of high-K insulating materials, so that when the device is switched on, the hole carrier density in the FS layer is improved, an IGBT (insulated gate bipolar transistor) region and an MOSFET (metal oxide semiconductor field effect transistor) region are effectively isolated, the on-resistance of the device is effectively reduced, and the snapback phenomenon when the device is switched on is inhibited;

2. the number of the first mounting grooves is 2, the 2 first mounting grooves are arranged in parallel, the 2 first mounting grooves are symmetrically arranged on two sides of the central line of the N-substrate, the first mounting grooves are convenient to prepare on the N-substrate, meanwhile, the number of the first insulating layers is 2, the insulativity of the filling layer is further improved, the on-resistance of the device is effectively reduced, and the snapback phenomenon of the device when the device is switched on is inhibited;

3. the super junction region is a P/N super junction region formed by P-type regions and N-type regions alternately, one P-type region can be arranged at one end of one N-type region, and one P-type region can also be arranged between the two N-type regions, so that a plurality of pairs of PN junctions can be formed on the device, and the wide usability of the device is improved;

4. firstly, a P/N super junction area is arranged in the middle of an N-substrate, then an FS layer is arranged at the lower end of the P/N super junction area, then a P + layer is arranged in the middle of the lower end of the FS layer, N + layers are arranged on two sides of the lower end of the FS layer, the top end of a first mounting groove is arranged in the P/N super junction area, the bottom end of the first mounting groove is arranged at the bottom end of the N-substrate, and the P + layer and the N + layer are respectively arranged on two sides of the first mounting groove, so that the area of the first mounting groove is increased, the area of a first insulating layer is further increased, the on-resistance of a device is more;

5. a second insulating layer is arranged in the second mounting groove, and the gate electrode is arranged on the inner side of the second insulating layer, so that the insulativity of the second mounting groove is improved;

6. the method comprises the steps of firstly preparing an N-substrate by adopting an N semiconductor material, then preparing a P/N super junction area formed by a P type area and an N type area alternately in the middle of the N-substrate, forming multiple pairs of PN junctions on a device, improving the wide usability of the device, then preparing a first mounting groove on the back surface of the N-substrate from the P/N super junction area to the bottom end, filling a first insulating layer in the first mounting groove, wherein the first insulating layer is made of a high-K insulating material, so that the hole carrier density in an FS layer is improved when the device is switched on, an IGBT area and an MOSFET area are effectively isolated, the on-resistance of the device is effectively reduced, the snapback phenomenon when the device is switched on is inhibited, and finally preparing the FS layer, the P + layer, the N + layer and the cellular on the N-substrate respectively, and the voltage resistance of the device is guaranteed.

Drawings

FIG. 1 is a schematic diagram of the structure of the present invention;

FIG. 2 is a schematic flow diagram of the present invention.

In the figure: 1: n-substrate, 2: p-type region, 3: n-type region, 4: second mounting groove, 5: second insulating layer, 6: gate electrode, 7: p-type body region, 8: p + region, 9: n + source region, 10: metal layer, 11: FS layer, 12: p + layer, 13: first insulating layer, 14: n + layer, 15: a first mounting groove.

Detailed Description

The following are specific embodiments of the present invention and are further described with reference to the drawings, but the present invention is not limited to these embodiments.

Referring to fig. 1-2, the IGBT device structure in this embodiment includes an N-substrate 1, a super junction region disposed on the N-substrate 1, a cell disposed at an upper end of the super junction region, an FS layer 11 disposed at a lower end of the N-substrate 1, a P + layer 12 disposed at a lower end of the N-substrate 1, an N + layer 14 disposed at a lower end of the N-substrate 1, and a filling layer disposed on the N-substrate 1, wherein the filling layer includes a first mounting groove 15 disposed on the N-substrate 1 and a first insulating layer 13 filled in the first mounting groove 15.

Here, the N-substrate 1, the super junction region, the cell, the FS layer 11, the P + layer 12, and the N + layer 14 may ensure withstand voltage of the device, the first mounting groove 15 is further disposed on the N-substrate 1, the first mounting groove 15 is filled with the first insulating layer 13, and the first insulating layer 13 is made of a high-K insulating material, so that when the device is turned on, a cavity carrier density in the FS layer 11 is increased, an IGBT region and a MOSFET region are effectively isolated, thereby effectively reducing on-resistance of the device, and suppressing a snapback phenomenon when the device is turned on.

The number of the first installation grooves 15 can be 2, wherein 2 first installation grooves 15 are arranged in parallel, and the 2 first installation grooves 15 are symmetrically arranged on two sides of the central line of the N-substrate 1. The number of the first mounting grooves 15 is 2, the 2 first mounting grooves 15 are arranged in parallel, the 2 first mounting grooves 15 are symmetrically arranged on two sides of the central line of the N-substrate 1, the first mounting grooves 15 are convenient to prepare on the N-substrate 1, meanwhile, the number of the first insulating layers 13 is 2, the insulativity of the filling layer is further improved, the on-resistance of the device is effectively reduced, and the snapback phenomenon when the device is switched on is restrained. There is no connection between the 2 first mounting grooves 15.

The super junction region can be a P/N super junction region formed by P type regions 2 and N type regions 3 alternately, one P type region 2 can be arranged at one end of one N type region 3, one P type region 2 can also be arranged between two N type regions 3, a plurality of pairs of PN junctions can be formed on the device, and the wide application of the device is improved. The P/N super junction region may include an N-type region 3 disposed in the middle, one P-type region 2 disposed at one end of the N-type region 3, and another P-type region 2 disposed at the other end of the N-type region 3, where the N-type region 3 and the P-type region 2 may both be square regions, the length of the N-type region 3 may be equal to the length of the P-type region 2, and the width of the N-type region 3 may be greater than the width of the P-type region 2. The central line of the first installation groove 15 can be linearly overlapped with the connecting position of the N-type area 3 and the P-type area 2, and the first installation groove 15 can be a square installation groove.

The P/N super-junction area can be arranged in the middle of the N-substrate 1, the FS layer 11 is arranged at the lower end of the P/N super-junction area, the P + layer 12 is arranged in the middle of the lower end of the FS layer 11, the N + layer 14 is arranged on two sides of the lower end of the FS layer 11, the top end of the first mounting groove 15 is arranged in the P/N super-junction area, the bottom end of the first mounting groove is arranged at the bottom end of the N-substrate 1, and the P + layer 12 and the N + layer 14 are respectively arranged on two. First set up P/N super junction area in the middle part of N-substrate 1, then set up FS layer 11 at P/N super junction area lower extreme, set up P + layer 12 in the middle part of FS layer 11 lower extreme, set up N + layer 14 in the both sides of FS layer 11 lower extreme, 15 tops of first mounting groove set up in P/N super junction area, the bottom sets up in the bottom of N-substrate 1, P + layer 12 and N + layer 14 set up respectively in the both sides of first mounting groove 15, thereby increase the area of first mounting groove 15, and then improve the area of first insulating layer 13, reduce the device on-resistance more effectively and restrain the snapback phenomenon when the device opens. The top end of the first mounting groove 15 is arranged at 1/3-1/2 of the length of the P/N, so that the area of the first insulating layer 13 is increased, the normal use of a P/N super junction region is not influenced, the on-resistance of the device is effectively reduced, and the snapback phenomenon of the device when the device is turned on is restrained. The FS layer 11 may be square, the FS layer 11 may be separated from the P/N super junction region, the FS layer 11 is not connected to the P/N super junction region bottom end, and the FS layer 11 may include three portions, one portion is disposed between the two first mounting grooves 15, one portion is disposed on one side of one first mounting groove 15, and one portion is disposed on one side of the other first mounting groove 15. The P + layer 12 and the N + layer 14 can be square layers respectively, the length of the P + layer 12 and the length of the N + layer 14 can be equal, the horizontal center line of the P + layer 12 and the horizontal center line of the N + layer 14 coincide, the P + layer 12 can be arranged between the two first mounting grooves 15, the N + layer 14 can be 2, one N + layer 14 is arranged on one side of one first mounting groove 15, and the other N + layer 14 is arranged on one side of the other first mounting groove 15.

The cell may include a second mounting groove 4 disposed at an upper end of the P/N super junction region, a gate electrode 6 disposed in the second mounting groove 4, a P-type body region 7 disposed at an upper end of the P/N super junction region, a P + region 8 disposed at an upper end of the P/N super junction region, an N + source region 9 disposed at an upper end of the second mounting groove 4, and a metal layer 10 disposed on the N + source region 9. The gate electrode 6 may be a polysilicon gate electrode 6. The metal layer 10 may be a Source pole metal layer 10. The P-type body region 7 and the N + source region 9 constitute a conductive channel.

The second insulating layer 5 is provided inside the second mounting groove 4, and the gate electrode 6 is provided inside the second insulating layer 5. A second insulating layer 5 is provided in the second mounting groove 4, and a gate electrode 6 is provided inside the second insulating layer 5, thereby improving the insulation of the second mounting groove 4.

Second mounting groove 4 sets up in the middle part of P/N super junction district upper end, the central line of second mounting groove 4 and the coincidence of the central line of N-substrate 1, the central line of N + source district 9 and the coincidence of the central line of second mounting groove 4, P type somatic region 7 is 2, 2P type somatic region 7 symmetries set up in the both sides of second mounting groove 4, P + region 8 is 2, P + 8 bottom end connection in P type somatic region 7, one end is connected in N + source district 9. The second mounting groove 4 may be a square groove. The metal layer 10 may be a rectangular metal layer 10. The P type body district 7 one end is connected in second mounting groove 4, top one end is connected in N + source district 9, the top other end is connected in P + region 8, P type body district 7 can be square P type body district 7, P + region 8 can be square P + region 8, N + source district 9 can be square N + source district 9, N + source district 9 can be 2, 2N + source districts 9 respectively the symmetry set up in the both sides of second mounting groove 4.

Referring to fig. 1-2, a method for fabricating an IGBT device structure according to claim 1 includes the following steps:

s1: preparing an N-substrate 1 by adopting an N semiconductor material;

s2: preparing a P/N super junction region formed by alternately forming a P type region 2 and an N type region 3 in the middle of an N-substrate 1;

s3: preparing a first mounting groove 15 on the back surface of the N-substrate 1 from the P/N super junction region to the bottom end, and filling a first insulating layer 13 in the first mounting groove 15;

s4: the FS layer 11, the P + layer 12, the N + layer 14, and the unit cells are prepared on an N-substrate, respectively.

Firstly, N-substrate 1 is prepared by N semiconductor material, then P/N super junction area formed by P type area 2 and N type area 3 is prepared in the middle of N-substrate 1, multiple PN junction pairs can be formed on the device, the wide use of the device is improved, a first mounting groove 15 is then prepared on the back surface of the N-substrate 1 at a portion from the P/N super junction region to the bottom end, the first mounting groove 15 is filled with a first insulation layer 13, the first insulation layer 13 is made of a high-K insulation material, thereby improving the hole carrier density in the FS layer 11 when the device is switched on, effectively isolating the IGBT area and the MOSFET area, therefore, the on-resistance of the device is effectively reduced, the snapback phenomenon of the device during opening is inhibited, and finally the FS layer 11, the P + layer 12, the N + layer 14 and the cells are respectively prepared on the N-substrate, so that the voltage resistance of the device is guaranteed. In step S3, the back of the N-substrate 1 is first thinned, then a deep trench is etched in a portion of the back of the N-substrate 1 from the P/N super junction region to the bottom to form a first mounting trench 15, the first mounting trench 15 penetrates through a portion of the N-substrate 1 and penetrates into the P/N super junction region, and the first mounting trench 15 is filled with a high-K insulating layer material, that is, the first mounting trench 15 is filled with the first insulating layer 13.

Step S4 specifically includes: injecting an N + into the lower end of the P/N super junction region on the N-substrate 1 to prepare an FS layer 11, injecting an N + into the lower end of the FS layer 11 on the N-substrate 1 to respectively prepare a P + layer 12 and an N + layer 14, and injecting an N + into the back of the N-substrate 1 to form the P + layer 12 and the N + layer 14, so as to realize back metallization.

The preparation of the unit cell in the step S4 specifically includes the following steps: preparing a second mounting groove 4 on the N-substrate 1; depositing a second insulating layer 5 on the inner side wall of the second mounting groove 4; filling polysilicon into the second mounting groove 4 at the inner side of the second insulating layer 5 to form a gate electrode 6; respectively preparing a P type body region 7, an N + source region 9 and a P + region 8 on the N-substrate 1 at the upper end of the P/N super junction region; depositing different interlayer media, and forming a contact hole through photoetching and dry etching; and depositing a metal layer 10 at the upper end of the N + source region 9, and carrying out photoetching and dry etching on the metal layer 10 to form a pattern, thereby forming a required pattern on the metal layer 10. The insulating layer can be an insulating film layer, the medium can be a conductive medium film, the deposition can be film deposition, and various conductive film layers and insulating film layers can be grown on the silicon chip through a deposition process. After forming an insulating film between different dielectric layers, a contact hole is formed by photolithography and dry etching, and conductive ion implantation is performed after opening the hole in order to reduce contact resistance of the contact hole and offset in the photolithography process.

The specific embodiments described herein are merely illustrative of the spirit of the invention. Various modifications or additions may be made to the described embodiments or alternatives may be employed by those skilled in the art without departing from the spirit or ambit of the invention as defined in the appended claims.