阅读说明：本技术 增强型GaN HEMT器件及其制备方法 (Enhanced GaN HEMT device and preparation method thereof ) 是由 郁发新 莫炯炯 王志宇 于 2020-05-28 设计创作，主要内容包括：本发明提供一种增强型GaN HEMT器件及制备方法,该器件包括：依次层叠的半导体衬底层、AlGaN缓冲层、GaN沟道层、Al<Sub>x</Sub>Ga<Sub>1-x</Sub>N势垒层及Al<Sub>y</Sub>Ga<Sub>1-y</Sub>N势垒补充层；形成于Al<Sub>x</Sub>Ga<Sub>1-x</Sub>N势垒层上的栅电极,形成于Al<Sub>y</Sub>Ga<Sub>1-y</Sub>N势垒补充层上且分居于栅电极的两端的源电极及漏电极；栅电极包括形成于Al<Sub>x</Sub>Ga<Sub>1-x</Sub>N势垒层上的p-GaN栅电极、包覆p-GaN栅电极的高k介质层及环绕高k介质层上表面及两个侧面的金属栅电极,其中,0.2<x<0.3,0.2<y<0.4。本发明通过调整刻蚀条件使p-GaN耗尽层与Al<Sub>x</Sub>Ga<Sub>1-x</Sub>N势垒层的刻蚀选择比介于20～30之间,准确控制刻蚀深度；通过源、漏二次外延势垒补充层,增强2DEG极化；另外,栅电极采用环形栅设计,使金属栅电极包覆p-GaN栅电极的上表面及两个侧面,增强了栅控能力；最后,利用ALD沉积形成高k栅介质层,降低了栅极漏电风险。(The invention provides an enhanced GaN HEMT device and a preparation method thereof, wherein the device comprises: a semiconductor substrate layer, an AlGaN buffer layer, a GaN channel layer, and Al stacked in sequence x Ga 1‑x N barrier layer and Al y Ga 1‑y An N-barrier supplemental layer; formed on Al x Ga 1‑x A gate electrode on the N barrier layer and formed on Al y Ga 1‑y A source electrode and a drain electrode on the N barrier supplement layer and respectively arranged at two ends of the gate electrode; the gate electrode is formed of Al x Ga 1‑x A p-GaN gate electrode on the N barrier layer, a high-k dielectric layer wrapping the p-GaN gate electrode, and a metal gate electrode surrounding the upper surface and two side surfaces of the high-k dielectric layer, wherein 0.2<x<0.3，0.2<y<0.4. The invention adjusts the etching condition to ensure that the p-GaN depletion layer and the Al are in contact x Ga 1‑x The etching selection ratio of the N barrier layer is between 20 and 30, and the etching depth is accurately controlled; 2DEG polarization is enhanced through a source and drain secondary epitaxial barrier supplementing layer; in addition, the gate electrode adopts a ring-shaped gate design, so that the upper surface and two side surfaces of the p-GaN gate electrode are coated by the metal gate electrode, and the gate control capability is enhanced; and finally, the high-k gate dielectric layer is formed by ALD deposition, so that the gate leakage risk is reduced.)

1. A preparation method of an enhanced GaN HEMT device is characterized by comprising the following steps:

providing enhancementsThe GaN device thin film structure comprises a semiconductor substrate layer, an AlGaN buffer layer, a GaN channel layer and Al in sequence along the growth direction_xGa_1-xAn N barrier layer and a p-GaN depletion layer of 0.2<x<0.3；

Defining a p-GaN gate electrode region by using a photoetching mask plate, and etching the p-GaN depletion layer by adopting an ICP (inductively coupled plasma) dry etching process to form a p-GaN gate electrode in the p-GaN gate electrode region, wherein the etching selection ratio of the p-GaN depletion layer to the AlGaN barrier layer is between 20 and 30;

the Al at both ends of the p-GaN gate electrode_xGa_1-xForming Al on the N barrier layer_yGa_1-yN barrier supplement layer of which 0.2<y<0.4；

In the presence of Al_yGa_1-yForming a source electrode and a drain electrode which are respectively arranged at two ends of the p-GaN gate electrode on the N potential barrier supplement layer;

forming a high-k gate dielectric layer on the surface of the p-GaN gate electrode, wherein the high-k gate dielectric layer covers the whole surface of the p-GaN gate electrode;

and forming a metal gate electrode on the high-k gate dielectric layer, wherein the metal gate electrode covers the upper surface and two side surfaces of the high-k gate dielectric layer to form an annular metal gate electrode.

2. The method for manufacturing an enhanced GaN HEMT device according to claim 1, wherein when the p-GaN depletion layer is etched by adopting an ICP dry etching process, the etching conditions are as follows:

by BCl₃And SF₆As an etching gas source, the etching parameters are selected as follows: BCl₃The flow rate of the gas is between 10sccm and 15sccm, SF₆The flow rate of the gas is between 5sccm and 10sccm, the pressure is between 30mTorr and 40mTorr, the RF power is between 50W and 60W, and the ICP power is between 180W and 200W; or

By Cl₂、N₂And O₂As an etching gas source, the etching parameters are selected as follows: cl₂The flow rate of (2) is between 25sccm and 30sccm, N₂The flow rate of (A) is between 5sccm and 10sccm, O₂Has a flow rate of 1sccm-5 sccm, pressure between 30 mTorr-35 mTorr, RF power between 30W-35W, and ICP power between 550W-600W.

3. The method of manufacturing an enhanced GaN HEMT device according to claim 1, wherein: forming the Al by MOCVD process_yGa_1-yThe growth temperature of the N barrier supplement layer is between 900 ℃ and 1000 ℃.

4. The method of manufacturing an enhanced GaN HEMT device according to claim 1, wherein: the Al is_xGa_1-xThe thickness of the N barrier layer is between 10nm and 15nm, and the Al is_yGa_1-yThe thickness of the N barrier supplement layer is between 10nm and 20 nm.

5. The method of manufacturing an enhanced GaN HEMT device according to claim 1, wherein: forming the source electrode and the drain electrode by adopting an electron beam evaporation process, and then performing a rapid thermal annealing process to form ohmic contacts of the source electrode and the drain electrode; wherein the source electrode and the drain electrode are of a laminated structure of Ti/Al/Ti/Au, and the thickness of the laminated structure is 30nm/120nm/40nm/60nm in sequence; the parameter of the rapid thermal annealing process is N with the temperature between 800 ℃ and 900 DEG C₂And performing rapid thermal annealing in the environment for 10-60 seconds.

6. The method of manufacturing an enhanced GaN HEMT device according to claim 1, wherein: forming the high-k gate dielectric layer by using an ALD (atomic layer deposition) deposition process, wherein the material of the high-k gate dielectric layer comprises Al₂O₃，HfO₂，ZrO₂At least one of the group consisting of.

7. The method of manufacturing an enhanced GaN HEMT device according to claim 1, wherein: and forming the metal gate electrode by adopting a thermal evaporation deposition process, wherein the metal gate electrode is of a Ni/Au laminated structure, and the thickness of the laminated structure is 30nm/120nm in sequence.

8. The method of manufacturing an enhanced GaN HEMT device according to claim 1, wherein: and before the high-k gate dielectric layer is formed, the method also comprises the step of cleaning the surface of the etched surface by adopting oxygen plasma oxidation and acid etching.

9. The method of manufacturing an enhanced GaN HEMT device according to claim 1, wherein: and after the metal gate electrode is formed, depositing a passivation layer on the surface of the structure formed in the step, etching the passivation layer to form electrode contact windows of the source electrode, the drain electrode and the metal gate electrode, and finally depositing metal to form interconnection.

10. An enhanced GaN HEMT device, comprising:

a semiconductor substrate layer, an AlGaN buffer layer, a GaN channel layer, and Al stacked in sequence_xGa_1-xN barrier layer and Al_yGa_1-yAn N-barrier supplemental layer;

formed on the Al_xGa_1-xA gate electrode on the N barrier layer and formed on the Al_yGa_1-yA source electrode and a drain electrode on the N barrier supplement layer, wherein the source electrode and the drain electrode are respectively arranged at two ends of the gate electrode; the gate electrode comprises Al formed on the substrate_xGa_1-xA p-GaN gate electrode on the N barrier layer, a high-k dielectric layer wrapping the p-GaN gate electrode, and a metal gate electrode surrounding the upper surface and two side surfaces of the high-k dielectric layer, wherein 0.2<x<0.3，0.2<y<0.4。

11. The enhanced GaN HEMT device of claim 8, wherein: the source electrode and the drain electrode are of a Ti/Al/Ti/Au laminated structure, and the thickness of the laminated structure is 30nm/120nm/40nm/60nm in sequence; the material of the high-k gate dielectric layer comprises Al₂O₃，HfO₂，ZrO₂At least one member of the group consisting of; the metal gate electrode is a stack of Ni/AuA layer structure, the thickness of the laminated structure is 30nm/120nm in sequence.

12. The enhanced GaN HEMT device of claim 8, wherein: the surface of the enhancement mode GaN HEMT device is provided with a passivation layer, the passivation layer is provided with electrode contact windows of the source electrode, the drain electrode and the metal gate electrode, and metal interconnection lines are formed in the electrode contact windows.

Technical Field

The invention belongs to the field of semiconductor device manufacturing, and particularly relates to an enhanced GaN HEMT device and a preparation method thereof.

Background

The third generation Semiconductor material, i.e. the Wide Band Gap Semiconductor (WBGS) Semiconductor material, is developed following the first generation silicon, germanium, the second generation gallium arsenide, indium phosphide, etc. Among the third generation semiconductor materials, gallium nitride (GaN) has superior properties such as wide band gap, direct band gap, high breakdown electric field, lower dielectric constant, high electron saturation drift velocity, strong radiation resistance, and good chemical stability, and becomes a key semiconductor material for manufacturing a new generation of microelectronic devices and circuits following germanium, silicon, and gallium arsenide. Especially, the material has the advantages of unique thickness in the aspects of high-temperature, high-power, high-frequency and anti-radiation electronic devices and full-wavelength and short-wavelength photoelectric devices, and is an ideal material for realizing the high-temperature, high-power, high-frequency, anti-radiation and full-wavelength photoelectric devices.

The High Electron Mobility Transistor (HEMT) based on the AlGaN/GaN heterojunction has the advantages of low on resistance, High breakdown voltage, High switching frequency and the like, so that the HEMT can be used as a core device in various power conversion systems, and has an important application prospect in the aspects of energy conservation and consumption reduction. However, due to the polarization effect of the iii-nitride material system, generally, HEMTs based on AlGaN/GaN heterojunction are depletion type (normally on), and when the devices of this type are applied to a circuit-level system, a negative-polarity gate driving circuit needs to be designed to realize the on-off control of the devices, which greatly increases the complexity and cost of the circuit. Furthermore, depletion mode devices have a drawback in fail safe capabilities and therefore cannot be truly commercially implemented. To solve this problem, it is feasible to fabricate enhancement mode HEMTs based on p-type gate technology, whereas in AlGaN/GaN HFETs the 2DEG (two-dimensional electron gas) carrier density is determined by the composition and thickness of the AlGaN barrier layer, which consumes as much 2DEG as possible, but to ensure that the 2DEG is fully depleted at zero gate bias, i.e. to obtain enhancement mode devices (or enhancement mode devices with a larger threshold, e.g. greater than 1V threshold voltage), the AlGaN barrier layer must be sufficiently thin, which limits the carrier density in the ungated access region. Therefore, a compromise epitaxial design must be made between the normally-off operating mode of the device and the low on-resistance RON. From the process point of view, the carrier density of an access region can be greatly reduced by etching the AlGaN barrier layer in the p-GaN etching process, so that the performance of a device is reduced, and the problem of insufficient grid control capability caused by the fact that the grid size is smaller than the p-GaN size exists in the traditional process for preparing the planar strip-shaped metal grid through photoetching alignment.

Disclosure of Invention

In view of the above drawbacks of the prior art, an object of the present invention is to provide an enhancement mode GaN HEMT device and a method for manufacturing the same, which are used to solve the problems in the prior art that the carrier density of an access region is greatly reduced by etching an AlGaN barrier layer in a p-GaN etching process of the enhancement mode GaN HEMT device, so that the device performance is reduced.

In order to achieve the above and other related objects, the present invention provides a method for manufacturing an enhanced GaN HEMT device, the method comprising:

providing an enhanced GaN device thin film structure, and sequentially comprising a semiconductor substrate layer, an AlGaN buffer layer, a GaN channel layer and Al along the growth direction_xGa_1-xAn N barrier layer and a p-GaN depletion layer of 0.2<x<0.3；

Defining a p-GaN gate electrode region by using a photoetching mask plate, and etching the p-GaN depletion layer by adopting an ICP (inductively coupled plasma) dry etching process to form a p-GaN gate electrode in the p-GaN gate electrode region, wherein the etching selection ratio of the p-GaN depletion layer to the AlGaN barrier layer is between 20 and 30;

the Al at both ends of the p-GaN gate electrode_xGa_1-xForming Al on the N barrier layer_yGa_1-yN barrier supplement layer of which 0.2<y<0.4；

In the presence of Al_yGa_1-yForming a source electrode and a drain electrode which are respectively arranged at two ends of the p-GaN gate electrode on the N potential barrier supplement layer;

forming a high-k gate dielectric layer on the surface of the p-GaN gate electrode, wherein the high-k gate dielectric layer covers the whole surface of the p-GaN gate electrode;

and forming a metal gate electrode on the high-k gate dielectric layer, wherein the metal gate electrode covers the upper surface and two side surfaces of the high-k gate dielectric layer to form an annular metal gate electrode.

Optionally, when the p-GaN depletion layer is etched by using an ICP dry etching process, the etching conditions are as follows:

by BCl₃And SF₆As an etching gas source, the etching parameters are selected as follows: BCl₃The flow rate of the gas is between 10sccm and 15sccm, SF₆The flow rate of the gas is between 5sccm and 10sccm, the pressure is between 30mTorr and 40mTorr, the RF power is between 50W and 60W, and the ICP power is between 180W and 200W; or

By Cl₂、N₂And O₂As an etching gas source, the etching parameters are selected as follows: cl₂The flow rate of (2) is between 25sccm and 30sccm, N₂The flow rate of (A) is between 5sccm and 10sccm, O₂The flow rate of (1) sccm to (5) sccm, the pressure between 30mTorr to (35 mTorr), the RF power between 30W to (35W), and the ICP power between 550W to (600W).

Optionally, the Al is formed using a MOCVD process_yGa_1-yThe growth temperature of the N barrier supplement layer is between 900 ℃ and 1000 ℃.

Alternatively, the Al_xGa_1-xThe thickness of the N barrier layer is between 10nm and 15nm, and the Al is_yGa_1-yThe thickness of the N barrier supplement layer is between 10nm and 20 nm.

Optionally, forming the source electrode and the drain electrode by using an electron beam evaporation process, and then performing a rapid thermal annealing process to form ohmic contacts of the source electrode and the drain electrode; wherein the source electrode and the drain electrode are of a laminated structure of Ti/Al/Ti/Au, and the thickness of the laminated structure is 30nm/120nm/40nm/60nm in sequence; the parameter of the rapid thermal annealing process is N with the temperature between 800 ℃ and 900 DEG C₂And performing rapid thermal annealing in the environment for 10-60 seconds.

Optionally, the high-k gate dielectric layer is formed by using an ALD deposition process, and the material of the high-k gate dielectric layer includes Al₂O₃，HfO₂，ZrO₂At least one of the group consisting of.

Optionally, the metal gate electrode is formed by a thermal evaporation deposition process, and the metal gate electrode is a laminated structure of Ni/Au, and the thickness of the laminated structure is 30nm/120nm in sequence.

Optionally, before forming the high-k gate dielectric layer, a step of cleaning an etched surface by using oxygen plasma oxidation and acid etching is further included.

Optionally, after the metal gate electrode is formed, depositing a passivation layer on the surface of the structure formed in the above step, etching the passivation layer to form electrode contact windows of the source electrode, the drain electrode and the metal gate electrode, and finally depositing metal to form an interconnection.

The invention also provides an enhanced GaN HEMT device, comprising:

a semiconductor substrate layer, an AlGaN buffer layer, a GaN channel layer, and Al stacked in sequence_xGa_1-xN barrier layer and Al_yGa_1-yAn N-barrier supplemental layer;

formed on the Al_xGa_1-xA gate electrode on the N barrier layer and formed on the Al_yGa_1-yA source electrode and a drain electrode on the N barrier supplement layer, wherein the source electrode and the drain electrode are respectively arranged at two ends of the gate electrode; the gate electrode comprises Al formed on the substrate_xGa_1-xA p-GaN gate electrode on the N barrier layer, a high-k dielectric layer wrapping the p-GaN gate electrode, and a metal gate electrode surrounding the upper surface and two side surfaces of the high-k dielectric layer, wherein 0.2<x<0.3，0.2<y<0.4。

Optionally, the source electrode and the drain electrode are of a laminated structure of Ti/Al/Ti/Au, and the thickness of the laminated structure is 30nm/120nm/40nm/60nm in sequence; the material of the high-k gate dielectric layer comprises Al₂O₃，HfO₂，ZrO₂At least one member of the group consisting of; the metal gate electrode is a Ni/Au laminated junctionThe thickness of the laminated structure is 30nm/120nm in sequence.

Optionally, a passivation layer is disposed on the surface of the enhancement-type GaN HEMT device, an electrode contact window of the source electrode, the drain electrode and the metal gate electrode is formed on the passivation layer, and a metal interconnection line is formed in the electrode contact window.

As described above, according to the enhanced GaN HEMT device and the preparation method thereof, the p-GaN depletion layer and the Al are enabled to be formed by adjusting the etching conditions_xGa_1-xThe etching selection ratio of the N barrier layer is between 20 and 30, the etching depth is accurately controlled, and the etching of the p-GaN depletion layer is stopped at Al_xGa_1-xThe surface of the N barrier layer; secondary epitaxy of Al through source and drain_yGa_1-yAn N-barrier supplemental layer to enhance 2DEG polarization; in addition, the gate electrode adopts a ring-shaped gate design, so that the upper surface and two side surfaces of the p-GaN gate electrode are coated by the metal gate electrode, and the gate control capability is enhanced; and finally, the high-k gate dielectric layer is formed by ALD deposition, so that the gate leakage risk is reduced.

Drawings

Fig. 1 is a process flow diagram of a method for manufacturing an enhancement-mode GaN HEMT device according to an embodiment of the present invention.

Fig. 2 is a schematic structural view of the step S1 in the method for manufacturing an enhancement-mode GaN HEMT device according to the first embodiment of the present invention.

Fig. 3 is a schematic structural view of a p-GaN gate electrode region formed in step S2 of the method for manufacturing an enhancement-type GaN HEMT device according to the first embodiment of the present invention.

Fig. 4 is a schematic structural view of a p-GaN gate electrode formed in step S2 of the method for manufacturing an enhancement-type GaN HEMT device according to the first embodiment of the present invention.

Fig. 5 is a schematic structural view of the step S3 in the method for manufacturing an enhancement-mode GaN HEMT device according to the first embodiment of the present invention.

Fig. 6 is a schematic structural view of the step S4 in the method for manufacturing an enhancement-mode GaN HEMT device according to the first embodiment of the present invention.

Fig. 7 is a schematic structural view of the step S5 in the method for manufacturing an enhancement-mode GaN HEMT device according to the first embodiment of the present invention.

Fig. 8 is a schematic structural view of the step S6 in the method for manufacturing an enhancement-mode GaN HEMT device according to the first embodiment of the present invention, and fig. 8 is a schematic structural view of the enhancement-mode GaN HEMT device according to the second embodiment of the present invention.

Fig. 9 is a schematic structural view of a conventional enhancement MIS p-GaN HEMT device.

Description of the element reference numerals

100 enhancement mode GaN device thin film structure

101 semiconductor substrate layer

102 AlGaN buffer layer

103 GaN channel layer

104 Al_xGa_1-xN barrier layer

105 p-GaN depletion layer

106 p-GaN gate electrode

107 source electrode

108 drain electrode

109 high-k gate dielectric layer

110 metal gate electrode

111 gate electrode

112 patterned photoresist layer

113 Al_yGa_1-yN-barrier supplemental layer

A p-GaN gate electrode region

B area with difficulty in opening

L1 Metal Gate electrode Length

L2 p-GaN gate electrode length

Distance between side wall of L3 metal gate electrode and side wall of p-GaN gate electrode

S1-S5

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 1 to 9. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed according to specific needs, and the layout of the components may be more complicated.