Operational amplifier with output clamping function

文档序号：1275296 发布日期：2020-08-25 浏览：7次中文

阅读说明：本技术 一种带输出箝位功能的运算放大器 (Operational amplifier with output clamping function ) 是由周泽坤金正扬王佳文王卓张波于 2020-06-15 设计创作，主要内容包括：一种带输出箝位功能的运算放大器,能够应用于Buck变换器中,当Buck变换器工作在正常状态的时候,运算放大模块的输出小于预设的上限箝位电压且大于预设的下限箝位电压,上限箝位模块和下限箝位模块都工作在比较器状态,不会对运放的正常工作造成影响。当运算放大模块的输出大于上限箝位电压的时候,上限箝位电路会对运放的输出进行箝位,脱离比较器状态,上限箝位电路进入运放状态。当运算放大模块的输出小于下限箝位电压的时候,下限箝位电路会对运放的输出进行箝位,脱离比较器状态,下限箝位电路进入运放状态。本发明在运放中加入了输出上限箝位和下限箝位功能,能够加快Buck变换器的响应速度,节约功耗。(The utility model provides an operational amplifier of area output clamping function, can be applied to the Buck converter, when the work of Buck converter is in normal condition, the output of operational amplification module is less than predetermined upper limit clamping voltage and is greater than predetermined lower limit clamping voltage, and upper limit clamping module and lower limit clamping module all work in the comparator state, can not cause the influence to the normal work of fortune putting. When the output of the operational amplification module is larger than the upper limit clamping voltage, the upper limit clamping circuit clamps the output of the operational amplifier, the operational amplifier is separated from the state of the comparator, and the upper limit clamping circuit enters the operational amplifier state. When the output of the operational amplification module is smaller than the lower limit clamping voltage, the lower limit clamping circuit clamps the output of the operational amplifier, the operational amplifier is separated from the state of the comparator, and the lower limit clamping circuit enters the state of the operational amplifier. According to the invention, the output upper limit clamping function and the output lower limit clamping function are added in the operational amplifier, so that the response speed of the Buck converter can be increased, and the power consumption is saved.)

1. An operational amplifier with output clamping function comprises an operational amplification module, a first resistor, a first capacitor, a bias module, an upper limit clamping module and a lower limit clamping module,

the bias module is used for providing bias for the operational amplification module, the upper limit clamping module and the lower limit clamping module and comprises a first PMOS (P-channel metal oxide semiconductor) tube, the grid drain of the first PMOS tube is in short circuit and is connected with bias current, and the source electrode of the first PMOS tube is connected with power supply voltage;

the positive input end of the operational amplification module is used as the positive input end of the operational amplifier, the negative input end of the operational amplification module is used as the negative input end of the operational amplifier, and the output end of the operational amplification module is grounded after passing through the first resistor and the first capacitor in sequence; the connection point of the first resistor and the first capacitor is used as the output end of the operational amplifier;

the upper limit clamping module comprises a fifth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a fifth NMOS tube, a sixth NMOS tube, a ninth NMOS tube, a third resistor and a third capacitor,

the grid electrode of the fifth PMOS tube is connected with the grid electrode of the first PMOS tube, the drain electrode of the fifth PMOS tube is connected with the source electrodes of the tenth PMOS tube and the eleventh PMOS tube, and the source electrode of the fifth PMOS tube is connected with the power supply voltage;

the grid electrode of the tenth PMOS tube is connected with the upper limit clamping voltage, and the drain electrode of the tenth PMOS tube is connected with the drain electrode of the fifth NMOS tube and the grid electrode of the ninth NMOS tube;

the grid electrode of the eleventh PMOS tube is connected with the output end of the operational amplification module and the drain electrode of the ninth NMOS tube, and the drain electrode of the eleventh PMOS tube is connected with the grid electrode and the drain electrode of the sixth NMOS tube and the grid electrode of the fifth NMOS tube;

the source electrodes of the fifth NMOS transistor, the sixth NMOS transistor and the ninth NMOS transistor are grounded;

one end of the third resistor is connected with the output end of the operational amplification module, and the other end of the third resistor is connected with the grid electrode of the ninth NMOS tube after passing through the third capacitor;

the lower limit clamping module comprises a third PMOS tube, a fourth PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a seventh NMOS tube, an eighth NMOS tube, a second resistor and a second capacitor,

the grid electrode of the fourth PMOS tube is connected with the grid electrode of the third PMOS tube and the grid electrode of the first PMOS tube, the drain electrode of the fourth PMOS tube is connected with the source electrodes of the twelfth PMOS tube and the thirteenth PMOS tube, and the source electrode of the fourth PMOS tube is connected with the source electrode of the third PMOS tube and is connected with power supply voltage;

the grid electrode of the thirteenth PMOS tube is connected with the lower limit clamping voltage, and the drain electrode of the thirteenth PMOS tube is connected with the drain electrode of the eighth NMOS tube and the grid electrode of the fifteenth PMOS tube;

the grid electrode of the twelfth PMOS tube is connected with the output end of the operational amplification module and the drain electrode of the fourteenth PMOS tube, and the drain electrode of the twelfth PMOS tube is connected with the grid electrode and the drain electrode of the seventh NMOS tube and the grid electrode of the eighth NMOS tube;

the source electrodes of the seventh NMOS transistor and the eighth NMOS transistor and the drain electrodes of the fifteenth PMOS transistor are grounded;

the grid electrode of the fourteenth PMOS tube is connected with the drain electrode of the third PMOS tube and the source electrode of the fifteenth PMOS tube, the source electrode of the fourteenth PMOS tube is connected with power supply voltage or bias signals, the bias signals are provided by the sixteenth PMOS tube which forms a current mirror with the first PMOS tube, the grid electrode of the sixteenth PMOS tube is connected with the grid electrode of the first PMOS tube, the source electrode of the sixteenth PMOS tube is connected with the power supply voltage, and the drain electrode of the sixteenth PMOS tube generates the bias signals;

one end of the second resistor is connected with the grid electrode of the fifteenth PMOS tube, and the other end of the second resistor is connected with the output end of the operational amplification module after passing through the second capacitor.

2. The operational amplifier with output clamping function as claimed in claim 1, wherein said operational amplifier module comprises a second PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor,

the grid electrode of the second PMOS tube is connected with the grid electrode of the first PMOS tube, the source electrode of the second PMOS tube is connected with power supply voltage, and the drain electrode of the second PMOS tube is connected with the source electrodes of the sixth PMOS tube and the seventh PMOS tube;

the grid electrode of the seventh PMOS tube is used as the positive input end of the operational amplification module, and the drain electrode of the seventh PMOS tube is connected with the source electrode of the ninth PMOS tube;

a grid electrode of the sixth PMOS tube is used as a negative input end of the operational amplification module, and a drain electrode of the sixth PMOS tube is connected with a source electrode of the eighth PMOS tube;

the grid electrode of the eighth PMOS tube is connected with the grid electrode and the bias voltage of the ninth PMOS tube, and the drain electrode of the eighth PMOS tube is connected with the drain electrode of the first NMOS tube and serves as the output end of the operational amplification module;

the grid drain of the third NMOS tube is in short circuit connection with the drain of the ninth PMOS tube and the grid of the first NMOS tube, and the source of the third NMOS tube is connected with the grid and the drain of the fourth NMOS tube and the grid of the second NMOS tube;

the drain electrode of the second NMOS tube is connected with the source electrode of the first NMOS tube, and the source electrode of the second NMOS tube is connected with the source electrode of the fourth NMOS tube and grounded.

3. The operational amplifier with output clamping function as claimed in claim 2, wherein said sixteenth PMOS transistor is a second PMOS transistor in said operational amplifier module.

4. The operational amplifier with output clamping function as claimed in claim 2 or 3, wherein the eighth PMOS transistor and the ninth PMOS transistor are low threshold PMOS transistors.

Technical Field

The invention belongs to the technical field of electronics, and relates to an operational amplifier with an output clamping function, which can be suitable for a Buck type DC-DC converter.

Background

In a Buck type DC-DC converter, a large capacitor is usually needed for compensation, the stability of a system is ensured, and when the Buck converter jumps to no load from a heavy load or the input voltage is suddenly lower than a preset output voltage, a loop enters a 0-duty ratio state or a 100-percent duty ratio state, so that the output of an operational amplifier is slowly reduced to 0 or increased to the power supply voltage. If the load is increased or the input voltage returns to normal at this time, the operational current charges and discharges the compensation capacitor, a long time is needed for returning to the normal level, and the output voltage of the Buck converter is in an abnormal state for a long time. In order to increase the response speed of the Buck converter, the operational amplifier current can be increased, and although the recovery time can be shortened, the power consumption can also be increased by increasing the operational amplifier current.

Disclosure of Invention

Aiming at the defect of overlarge recovery time in the response process of the Buck converter, the invention provides the operational amplifier with the output clamping function, and the output upper limit clamping function and the output lower limit clamping function are added in the operational amplifier, so that the response speed of the Buck converter can be accelerated, the power consumption is saved, and the problem of overlarge recovery time in the response process of the Buck converter is solved.

The technical scheme of the invention is as follows:

an operational amplifier with output clamping function comprises an operational amplification module, a first resistor, a first capacitor, a bias module, an upper limit clamping module and a lower limit clamping module,

the upper limit clamping module comprises a fifth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a fifth NMOS tube, a sixth NMOS tube, a ninth NMOS tube, a third resistor and a third capacitor,

the source electrodes of the fifth NMOS transistor, the sixth NMOS transistor and the ninth NMOS transistor are grounded;

the source electrodes of the seventh NMOS transistor and the eighth NMOS transistor and the drain electrodes of the fifteenth PMOS transistor are grounded;

Specifically, the operational amplification module comprises a second PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube,

Specifically, the sixteenth PMOS transistor is the second PMOS transistor in the operational amplification module.

Specifically, the eighth PMOS transistor and the ninth PMOS transistor are low-threshold PMOS transistors.

The invention has the beneficial effects that: the invention adds the output upper limit clamping and lower limit clamping functions in the operational amplifier, and can be suitable for the Buck converter; when the Buck converter works normally, the upper limit clamping circuit and the lower limit clamping circuit work in a comparator state, and the normal work of the operational amplifier is not affected; when the output VO1 of the operational amplification module is greater than the upper limit clamping voltage VH, the limit clamping circuit clamps the output of the operational amplifier, and when the output VO1 of the operational amplification module is less than the lower limit clamping voltage VL, the lower limit clamping circuit clamps the output VO1 of the operational amplifier.

Drawings

Fig. 1 is a specific circuit diagram of an operational amplifier with an output clamping function according to an embodiment of the present invention.

Detailed Description

The invention is further illustrated with reference to the figures and the specific examples.

The invention provides an operational amplifier with an output clamping function, which mainly comprises an operational amplification module and a clamping circuit, wherein a bias module provides bias for the operational amplification circuit and the clamping circuit, the bias module comprises a first PMOS (P-channel metal oxide semiconductor) tube MP1, the grid-drain short circuit of the first PMOS tube MP1 is connected with a bias current IBIAS, and the source electrode of the first PMOS tube MP1 is connected with a power supply voltage VDD; all branches of the present invention are powered by the mirror bias current of the first PMOS transistor MP 1.

The operational amplifier module is used to implement the operational amplifier function, and in this embodiment, a single-stage sleeve-type structure is taken as an example for description, but operational amplifiers with other structures are also applicable to the present invention. As shown in fig. 1, the operational amplifier module in this embodiment includes a second PMOS transistor MP2, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, and a fourth NMOS transistor MN4, a gate of the second PMOS transistor MP2 is connected to a gate of the first PMOS transistor, a source of the second PMOS transistor MP2 is connected to a power supply voltage VDD, and a drain of the second PMOS transistor MP6 is connected to sources of the seventh PMOS transistor MP 7; the gate of the seventh PMOS transistor MP7 is used as the positive input terminal of the operational amplifier module, and the drain thereof is connected to the source of the ninth PMOS transistor MP 9; the gate of the sixth PMOS transistor MP6 is used as the negative input terminal of the operational amplifier module, and the drain thereof is connected to the source of the eighth PMOS transistor MP 8; the gate of the eighth PMOS transistor MP8 is connected to the gate of the ninth PMOS transistor MP9 and the bias voltage VB, and the drain thereof is connected to the drain of the first NMOS transistor MN1 and serves as the output terminal VO1 of the operational amplifier module; the gate-drain short circuit of the third NMOS transistor MN3 is connected with the drain of the ninth PMOS transistor MP9 and the gate of the first NMOS transistor MN1, and the source of the third NMOS transistor MN3 is connected with the gate and the drain of the fourth NMOS transistor MN4 and the gate of the second NMOS transistor MN 2; the drain of the second NMOS transistor MN2 is connected to the source of the first NMOS transistor MN1, and the source thereof is connected to the source of the fourth NMOS transistor MN4 and is grounded to GND.

The second PMOS transistor MP2 is a tail current source, the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 are input pair transistors, the eighth PMOS transistor MP8 and the ninth PMOS transistor MP9 are common-gate transistors, the eighth PMOS transistor MP8 and the ninth PMOS transistor MP9 preferably use low-threshold transistors, and particularly when the power supply voltage VDD is low, the common-mode input range and the output swing amplitude of the operational amplifier can be improved, and VB is the bias voltage of the common-gate transistors. The first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are cascode current mirror loads. The first resistor R1 and the first capacitor C1 are compensation resistors and compensation capacitors, and filter the output VO1 of the operational amplifier module to obtain the final output signal EA _ OUT of the operational amplifier.

The clamping circuit comprises an upper limit clamping module and a lower limit clamping module.

As shown in fig. 1, the upper limit clamping module includes a fifth PMOS transistor MP5, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a ninth NMOS transistor MN9, a third resistor R3, and a third capacitor C3, a gate of the fifth PMOS transistor MP5 is connected to a gate of the first PMOS transistor MP1, a drain of the fifth PMOS transistor MP5 is connected to sources of the tenth PMOS transistor MP10 and the eleventh PMOS transistor MP11, and a source of the fifth PMOS transistor MP 3652 is connected to a power supply voltage VDD; the grid electrode of the tenth PMOS pipe MP10 is connected with the upper limit clamping voltage VH, and the drain electrode thereof is connected with the drain electrode of the fifth NMOS pipe MN5 and the grid electrode of the ninth NMOS pipe MN 9; the gate of the eleventh PMOS transistor MP11 is connected to the output terminal VO1 of the operational amplification module and the drain of the ninth NMOS transistor MN9, and the drain is connected to the gate and the drain of the sixth NMOS transistor MN6 and the gate of the fifth NMOS transistor MN 5; the sources of the fifth NMOS transistor MN5, the sixth NMOS transistor MN6 and the ninth NMOS transistor MN9 are grounded; one end of the third resistor R3 is connected to the output terminal VO1 of the operational amplifier module, and the other end is connected to the gate of the ninth NMOS transistor MN9 through the third capacitor C3.

The upper limit clamping module adopts a two-stage structure, the first-stage structure of the upper limit clamping module comprises a fifth PMOS tube MP5, a tenth PMOS tube MP10, an eleventh PMOS tube MP11, a fifth NMOS tube MN5 and a sixth NMOS tube MN6, wherein the fifth PMOS tube MP5 is a tail current source, the tenth PMOS tube MP10 and the eleventh PMOS tube MP11 are input pair tubes, the fifth NMOS tube MN5 and the sixth NMOS tube MN6 are current mirror loads, and the output of the first stage is VO 2. The second stage of the upper limit clamping module is a common source structure, the ninth NMOS transistor MN9 is a common source transistor, and the output VO1 of the operational amplification module is used as a load of the ninth NMOS transistor MN 9. The positive input end of the upper limit clamping module, namely the grid electrode of the tenth PMOS tube, is connected with the preset upper limit clamping voltage VH, and the negative input end of the upper limit clamping module is connected with the output VO1 of the operational amplification module to form negative feedback. When the Buck converter works in a normal state, the VO1 is smaller than VH, the upper limit clamping circuit works in a comparator state, the VO2 is at a low level, and the ninth NMOS transistor MN9 is turned off, so that the normal work of the operational amplifier is not influenced. When VO1> VH, the upper limit clamp circuit will clamp the output of the operational amplifier, and leave the comparator state, and the upper limit clamp circuit enters the operational amplifier state.

When the upper limit clamping module works in a small signal state, two low-frequency poles exist, the third resistor R3 and the third capacitor C3 are needed to be used as Miller compensation to separate the two poles, stability is guaranteed, and the loop gain of the upper limit clamping circuit can be expressed as follows:

wherein, g_mR is transconductance of corresponding MOS tube_oIs the equivalent resistance of the corresponding MOS tube. The Miller effect is generated at the gate of the ninth NMOS transistor MN9The capacitor is large, and a low-frequency dominant pole is formed. The gate leakage of the ninth NMOS transistor MN9 is shorted by the compensation capacitor in the high frequency band, and the secondary pole is pushed high. Meanwhile, the feedforward action of the Miller capacitor, namely the third capacitor C3 introduces a right half-plane zero point, and the zero point is pushed to high frequency by adjusting the position of the zero point through the zero adjusting resistor, namely the third resistor R3.

As shown in fig. 1, the lower limit clamping module includes a third PMOS transistor MP3, a fourth PMOS transistor MP4, a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a fourteenth PMOS transistor MP14, a fifteenth PMOS transistor MP15, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a second resistor R2, and a second capacitor C2, wherein a gate of the fourth PMOS transistor MP4 is connected to a gate of the third PMOS transistor MP3 and a gate of the first PMOS transistor, drains of the fourth PMOS transistor MP4 are connected to sources of the twelfth PMOS transistor MP12 and the thirteenth PMOS transistor MP13, and a source of the fourth PMOS transistor MP3 is connected to the source of the third PMOS transistor MP3 and the power supply voltage VDD; the gate of the thirteenth PMOS transistor MP13 is connected to the lower limit clamping voltage VL, and the drain thereof is connected to the drain of the eighth NMOS transistor MN8 and the gate of the fifteenth PMOS transistor MP 15; the grid electrode of the twelfth PMOS tube MP12 is connected with the output end VO1 of the operational amplification module and the drain electrode of the fourteenth PMOS tube MP14, and the drain electrode of the twelfth PMOS tube MP12 is connected with the grid electrode and the drain electrode of the seventh NMOS tube MN7 and the grid electrode of the eighth NMOS tube MN 8; the sources of the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 and the drain of the fifteenth PMOS transistor MP15 are grounded GND; the gate of the fourteenth PMOS transistor MP14 is connected to the drain of the third PMOS transistor MP3 and the source of the fifteenth PMOS transistor MP15, the source thereof is connected to the power voltage or the bias signal, one end of the second resistor R2 is connected to the gate of the fifteenth PMOS transistor MP15, and the other end is connected to the output end of the operational amplifier module through the second capacitor C2. The bias signal is provided by a sixteenth PMOS tube which forms a current mirror with the first PMOS tube, the grid electrode of the sixteenth PMOS tube is connected with the grid electrode of the first PMOS tube, the source electrode of the sixteenth PMOS tube is connected with power supply voltage, and the drain electrode of the sixteenth PMOS tube generates the bias signal. In some embodiments, the second PMOS transistor in the operational amplifier module may also be used as a sixteenth PMOS transistor for providing the bias signal, as shown in fig. 1.

The lower limit clamping module is of a three-stage structure, and the first stage comprises a tail current source fourth PMOS tube MP4, an input geminate transistor twelfth PMOS tube MP12, an input geminate transistor thirteenth PMOS tube MP13, a current mirror load seventh NMOS tube MN7 and an eighth NMOS tube MN 8. The second stage of the lower limit clamping circuit comprises a fifteenth PMOS tube MP15 and a third PMOS tube MP3 which are used as level shift circuits, the output level of the first stage of the lower limit clamping module is raised, and the second stage output signal VO3 of the lower limit clamping circuit. The third stage of the lower limit clamping module uses the fourteenth PMOS transistor MP14 as a common source transistor and uses the output VO1 of the operational amplification module as a load. The positive input end of the lower limit clamp circuit, i.e. the gate of the thirteenth PMOS transistor MP13, is connected to the preset lower limit clamp voltage VL, and the negative input end of the lower limit clamp circuit, i.e. the gate of the twelfth PMOS transistor MP12, is connected to the output VO1 of the operational amplifier, forming negative feedback. When the Buck converter works in a normal state, the voltage VO1 is larger than VL, the lower limit clamping circuit works in a comparator state, the voltage VO3 is at a high level, and the fourteenth PMOS tube MP14 is turned off, so that the normal operation of the operational amplifier is not influenced. When VO1< VL, the lower limit clamp clamps the output VO1 of the op-amp, leaving the comparator state, and the lower limit clamp enters the op-amp state. The second resistor R2 and the second capacitor C2 are compensation resistors and capacitors of the lower limit clamp circuit.

When the clamp circuit operates in the comparator state, VO2 and VO3 can be considered as ac ground, and miller capacitors, i.e., the second capacitor C2 and the third capacitor C3, become load capacitors of the main operational amplifier, which introduces the secondary pole. Regardless of the internal high frequency parasitic pole and mirror zero pole, the transfer function of the operational amplifier can be expressed as:

the miller capacitance of the clamp circuit, the secondary pole introduced by the second capacitor C2 and the third capacitor C3 is at high frequency and does not have too great an effect on the loop. The whole system can be kept stable, so that the normal work of the operational amplifier and the output clamping in a response state are realized.

To sum up, the invention provides an operational amplifier with an output clamping function, which can be applied to a Buck converter, when the Buck converter works in a normal state, the output VO1 of an operational amplification module is smaller than a preset upper limit clamping voltage VH, the output VO1 of the operational amplification module is larger than a preset lower limit clamping voltage VL, an upper limit clamping circuit and a lower limit clamping circuit work in a comparator state, the output VO2 of the upper limit clamping circuit is at a low level, a ninth NMOS transistor MN9 is turned off, the output VO3 of the lower limit clamping circuit is at a high level, and a fourteenth PMOS transistor MP14 is turned off, so that the normal work of the operational amplifier is not affected. When the output VO1 of the operational amplification module is greater than the upper limit clamping voltage VH, the upper limit clamping circuit clamps the output of the operational amplifier, the operational amplifier is separated from the comparator state, and the upper limit clamping circuit enters the operational amplifier state. When the output VO1 of the operational amplification module is smaller than the lower limit clamping voltage VL, the lower limit clamping circuit clamps the output VO1 of the operational amplifier, the operational amplifier is separated from the comparator state, and the lower limit clamping circuit enters the operational amplifier state. Therefore, the invention adds the output upper limit clamping function and the output lower limit clamping function in the operational amplifier, can accelerate the response speed of the Buck converter and save the power consumption.

Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.

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