阅读说明：本技术 一种时钟串扰消除电路和电子设备 (Clock crosstalk elimination circuit and electronic equipment ) 是由 皮德义 郑慧 于 2020-06-01 设计创作，主要内容包括：本发明提供一种时钟串扰消除电路和电子设备,电路通过在频率综合器对初始时钟信号频率调节结束后,通过第一频率调节器对频率综合器调节后的初始时钟信号进行还原,然后再通过鉴相器将还原后的初始时钟信号与未处理过的初始时钟信号进行比较,得到两者的相位差,然后再通过带通滤波器对所述鉴相器的输出信号进行滤波处理,即可得到频率综合器对初始时钟信号进行频率调节时所引入的串扰信号的大小,采用第一相位差值器基于带通滤波器的输出信号对所述频率综合器调节后的初始时钟信号进行相位补偿,即可消除频率综合器对初始时钟信号进行频率调节时所引入的串扰信号。(The invention provides a clock crosstalk elimination circuit and an electronic device, after the frequency synthesizer finishes the frequency adjustment of an initial clock signal, the initial clock signal adjusted by the frequency synthesizer is restored through the first frequency adjuster, then the restored initial clock signal is compared with the unprocessed initial clock signal through a phase discriminator to obtain the phase difference between the restored initial clock signal and the unprocessed initial clock signal, then the output signal of the phase discriminator is filtered through a band-pass filter, the size of the crosstalk signal introduced when the frequency synthesizer performs frequency adjustment on the initial clock signal can be obtained, the initial clock signal adjusted by the frequency synthesizer is subjected to phase compensation by adopting a first phase difference device based on the output signal of the band-pass filter, i.e. eliminating the crosstalk signal introduced when the frequency synthesizer performs frequency adjustment on the initial clock signal.)

1. A clock crosstalk cancellation circuit, comprising:

the frequency synthesizer has an input end for inputting an initial clock signal, and an output end for outputting the initial clock signal regulated by the frequency synthesizer and having a frequency increased to a first desired value, and recording the initial clock signal as a first clock signal;

the input end of the first frequency regulator is connected with the output end of the frequency synthesizer, and the frequency regulation multiple of the first frequency regulator is in inverse proportion to the frequency regulation multiple of the frequency synthesizer;

a first input end of the phase detector is used for acquiring an initial clock signal, a second input end of the phase detector is used for inputting the first clock signal processed by the first frequency regulator, and an output end of the phase detector is used for outputting the phase difference between the initial clock signal and the first clock signal processed by the first frequency regulator;

the input end of the band-pass filter is connected with the output end of the phase discriminator and is used for filtering the output signal of the phase discriminator;

and the first input end of the first phase difference device is connected with the output end of the frequency synthesizer, the second input end of the first phase difference device is connected with the output end of the band-pass filter, and the output end of the first phase difference device is used for outputting a first clock signal which is regulated by the output signal of the band-pass filter and is marked as a second clock signal.

2. The clock crosstalk cancellation circuit of claim 1, comprising:

and the input end of the first frequency divider is connected with the output end of the first phase difference value device, and the output end of the first frequency divider is used for outputting the clock signal obtained by frequency division of the second clock signal.

3. The clock crosstalk cancellation circuit of claim 1, wherein the first frequency adjuster is a phase difference adjuster.

4. The clock crosstalk cancellation circuit of claim 1, wherein said first frequency adjuster comprises:

the input end of the second phase difference device is connected with the output end of the frequency synthesizer;

and the input end of the second frequency divider is connected with the output end of the second phase difference value device, the output end of the second frequency divider is used for carrying out frequency division processing on the first clock signal regulated by the second phase difference value device to obtain a third clock signal, and the product of the frequency regulation multiples of the second phase difference value device and the second frequency divider and the frequency regulation multiple of the frequency synthesizer are in inverse proportion relation.

5. An electronic device, characterized in that the clock crosstalk cancellation circuit according to any one of claims 1 to 4 is applied.

Technical Field

The invention relates to the technical field of electronic circuits, in particular to a clock crosstalk elimination circuit and electronic equipment.

Background

With the increasing data transmission speed in a communication system and the decreasing volume of communication equipment, the routing density of circuits on a PCB is higher and higher, and if a circuit board has a plurality of high-speed signals, the physical intervals of the high-speed signals are very close, so that the problem of crosstalk between the high-speed signals is more and more obvious. Also, there is power supply crosstalk in the communication system that distorts the clean high-speed signal, causing distortion of the high-speed signal.

Therefore, how to eliminate the interference signals in these high-speed signals becomes one of the technical problems that those skilled in the art need to solve.

Disclosure of Invention

In view of the above, embodiments of the present invention provide a clock crosstalk elimination circuit and an electronic device to eliminate an interference signal in a high-speed signal.

In order to achieve the above purpose, the embodiments of the present invention provide the following technical solutions:

a clock crosstalk cancellation circuit, comprising:

the frequency synthesizer has an input end for inputting an initial clock signal, and an output end for outputting the initial clock signal regulated by the frequency synthesizer and having a frequency increased to a first desired value, and recording the initial clock signal as a first clock signal;

the input end of the first frequency regulator is connected with the output end of the frequency synthesizer, and the frequency regulation multiple of the first frequency regulator is in inverse proportion to the frequency regulation multiple of the frequency synthesizer;

a first input end of the phase detector is used for acquiring an initial clock signal, a second input end of the phase detector is used for inputting the first clock signal processed by the first frequency regulator, and an output end of the phase detector is used for outputting the phase difference between the initial clock signal and the first clock signal processed by the first frequency regulator;

the input end of the band-pass filter is connected with the output end of the phase discriminator and is used for filtering the output signal of the phase discriminator;

and the first input end of the first phase difference device is connected with the output end of the frequency synthesizer, the second input end of the first phase difference device is connected with the output end of the band-pass filter, and the output end of the first phase difference device is used for outputting a first clock signal which is regulated by the output signal of the band-pass filter and is marked as a second clock signal.

Optionally, the clock crosstalk elimination circuit includes:

and the input end of the first frequency divider is connected with the output end of the first phase difference value device, and the output end of the first frequency divider is used for outputting the clock signal obtained by frequency division of the second clock signal.

Optionally, in the clock crosstalk elimination circuit, the first frequency adjuster is a phase difference adjuster.

Optionally, in the clock crosstalk elimination circuit, the first frequency adjustor includes:

the input end of the second phase difference device is connected with the output end of the frequency synthesizer;

and the input end of the second frequency divider is connected with the output end of the second phase difference value device, the output end of the second frequency divider is used for carrying out frequency division processing on the first clock signal regulated by the second phase difference value device to obtain a third clock signal, and the product of the frequency regulation multiples of the second phase difference value device and the second frequency divider and the frequency regulation multiple of the frequency synthesizer are in inverse proportion relation.

An electronic device to which the clock crosstalk elimination circuit according to any one of the above is applied.

Based on the above technical solution, in the above solution provided in the embodiment of the present invention, after the frequency synthesizer finishes adjusting the frequency of the initial clock signal, the initial clock signal adjusted by the frequency synthesizer is restored through the first frequency adjuster, then the restored initial clock signal is compared with the unprocessed initial clock signal through a phase discriminator to obtain the phase difference between the restored initial clock signal and the unprocessed initial clock signal, then the output signal of the phase discriminator is filtered through a band-pass filter, the size of the crosstalk signal introduced when the frequency synthesizer performs frequency adjustment on the initial clock signal can be obtained, the initial clock signal adjusted by the frequency synthesizer is subjected to phase compensation by adopting a first phase difference device based on the output signal of the band-pass filter, i.e. eliminating the crosstalk signal introduced when the frequency synthesizer performs frequency adjustment on the initial clock signal.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a clock crosstalk cancellation circuit disclosed in an embodiment of the present application;

fig. 2 is a schematic structural diagram of a clock crosstalk cancellation circuit according to another embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The present application provides a clock crosstalk elimination circuit capable of eliminating interference in a high-speed signal, and referring to fig. 1, the circuit may include:

a frequency synthesizer 100, wherein an initial clock signal is input to an input terminal of the frequency synthesizer 100, and an output terminal of the frequency synthesizer 100 is configured to output the initial clock signal, which is adjusted by the frequency synthesizer 100 and has a frequency raised to a first desired value, and is marked as a first clock signal Clk₂In this embodiment, the input terminal of the frequency synthesizer 100 is connected to the initial clock signal Clk₁For converting said initial clock signal Clk₁Is increased to a first desired value to obtain a first clock signal Clk₂Wherein the frequency synthesizer 100 introduces crosstalk V during the frequency adjustment process_cThe interference V_cIs that of this applicationPlease the interference signal to be eliminated;

a first frequency regulator 200, an input end of the first frequency regulator 200 is connected with an output end of the frequency synthesizer 100, a frequency regulation multiple of the first frequency regulator 200 is in an inverse proportion relation with a frequency regulation multiple of the frequency synthesizer 100, and an output signal thereof is marked as Clk₄For example, the frequency synthesizer 100 adjusts the initial clock signal Clk₁Is amplified by a factor of 2, the first frequency adjustor 200 functions to adjust the first clock signal Clk₂Is reduced to 1/2 times.

A phase detector 300, a first input terminal of the phase detector 300 is used for obtaining an initial clock signal, a second input terminal of the phase detector 300 is used for inputting a first clock signal restored by the first frequency adjustor 200, an output terminal of the phase detector 300 is used for outputting a phase difference between the initial clock signal and the restored first clock signal, and the phase detector 300 compares a clock signal Clk output by the first frequency adjustor 200₄And said initial clock signal Clk₁Is obtained to represent said clock signal Clk₄And said initial clock signal Clk₁Signal V of the phase difference_pd；

Band pass filter 400, band pass filter 400 sets up between the output of phase discriminator 300 and the second input of first phase difference value ware 500, through band pass filter 400 is right the phase difference signal of phase discriminator 300 output carries out filtering process, band pass filter 400 is right phase difference signal can obtain crosstalk signal V after carrying out band-pass filtering_f. At this time, the first phase difference unit 500 is configured to generate the crosstalk signal V according to the crosstalk signal V_fPerforming phase compensation on the first clock signal.

A first phase difference unit 500, a first input terminal of the first phase difference unit 500 being connected to the output terminal of the frequency synthesizer 100, a second input terminal of the first phase difference unit 500 being connected to the output terminal of the band pass filter 400, an output terminal of the first phase difference unit 500The output end is used for outputting the first clock signal after the phase difference adjustment and is recorded as a second clock signal Clk₅The first phase difference unit 500 is used for generating the crosstalk signal V_fPerforming phase compensation on the first clock signal by the crosstalk signal V_fI.e. the crosstalk V introduced by the frequency synthesizer 100 during the adjustment of the initial clock signal can be eliminated_c。

In the technical solutions disclosed in the above embodiments of the present application, the crosstalk signal is mainly introduced when the frequency synthesizer 100 performs frequency adjustment on the initial clock signal, in the present application, after the frequency synthesizer 100 finishes frequency adjustment on the initial clock signal, the initial clock signal after frequency synthesizer 100 is adjusted is restored by the first frequency adjuster 200, then the restored initial clock signal is compared with the unprocessed initial clock signal by the phase detector 300 to obtain a phase difference therebetween, then the output signal of the phase detector 300 is filtered by the band pass filter 400, that is, the size of the crosstalk signal introduced when the frequency synthesizer 400 performs frequency adjustment on the initial clock signal can be obtained, the first phase difference unit 500 performs phase compensation on the initial clock signal after frequency synthesizer 100 is adjusted based on the output signal of the band pass filter 400, i.e., the crosstalk signal introduced when the frequency synthesizer 100 frequency-adjusts the initial clock signal is cancelled.

Referring to fig. 2, in the technical solution disclosed in another embodiment of the present application, the first expected value may not be an expected value required by a user, and therefore, in the technical solution disclosed in the above embodiment of the present application, a first frequency divider 600 may be further included, an input end of the first frequency divider 600 is connected to an output end of the first phase difference unit 500, an output end of the first frequency divider 600 is used for outputting a clock signal obtained by frequency dividing the second clock signal, and in the present solution, the clock signal compensated by the first phase difference unit 500 is frequency-divided by the first frequency divider 600, so that the clock signal required by the user and having the expected value can be obtained.

In the technical solution disclosed in the embodiment of the present application, the first frequency modulationThe node 200 may be implemented by a phase difference device, or by a combination of a phase difference device and a frequency divider, and when implemented by a combination of a difference device and a frequency divider, the first frequency adjustor 200 includes: a second phase difference device 201, an input end of the second phase difference device 201 is connected with an output end of the frequency synthesizer 100; a second frequency divider 202, an input end of the second frequency divider 202 is connected to an output end of the second phase difference unit 201, an output end of the second frequency divider 202 is configured to perform frequency division processing on the first clock signal adjusted by the second phase difference unit 201 to obtain a third clock signal, a product of frequency adjustment multiples of the second phase difference unit 201 and the second frequency divider 202 and the frequency adjustment multiple of the frequency synthesizer 100 are in an inverse proportional relationship, for example, if the frequency synthesizer 100 makes the initial clock signal Clk k₁Is increased to 2 times, the second phase difference unit 201 does not operate, and the second frequency divider 202 divides the clock signal Clk output by the second phase interpolator₃Performing frequency division by two; if the frequency synthesizer 100 will convert the initial clock signal Clk₁Is increased to 2.2 times, the clock signal Clk output by the frequency synthesizer 100 is first processed by the second phase interpolator₂To the initial clock signal Clk₁2 times the frequency of the clock signal Clk output by the frequency synthesizer 100 by the second phase interpolator₂Is adjusted to 2/2.2 times, and then the clock signal Clk output by the second phase interpolator is divided by the second frequency divider 202₃Is divided by two, i.e. the second frequency divider 202 divides the clock signal Clk output by the second phase interpolator by two₃Is adjusted to 1/2 times.

Corresponding to the circuit, the application also discloses an electronic device using the circuit, and the electronic device can be applied with the electronic device described in any one of the above embodiments.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.