阅读说明：本技术 一种基于spi协议的动态调试方法、装置及系统 (Dynamic debugging method, device and system based on SPI protocol ) 是由 许伟明 胡胜发 于 2020-04-07 设计创作，主要内容包括：本发明公开了一种基于SPI协议的动态调试方法,步骤包括：采用SPI协议与主机端建立通讯连接,并接收来自主机端的指令；根据主机端发送的指令,通过AHB协议与系统芯片进行通信并对所述系统芯片进行数据写入或信息读取；当完成数据写入或信息读取后,将系统芯片的内部信息发送给主机端。本发明提供了一种基于SPI协议的动态调试方法、装置及系统,能够在芯片正常运行期间,获取芯片内部运行的相关信息,动态调试芯片的软件运行程序。(The invention discloses a dynamic debugging method based on an SPI protocol, which comprises the following steps: establishing communication connection with a host computer end by adopting an SPI protocol, and receiving an instruction from the host computer end; according to an instruction sent by a host, communicating with a system chip through an AHB protocol and writing data or reading information into the system chip; and after finishing data writing or information reading, sending the internal information of the system chip to the host end. The invention provides a dynamic debugging method, a device and a system based on an SPI protocol, which can acquire relevant information of internal operation of a chip and dynamically debug a software operation program of the chip during the normal operation of the chip.)

1. A dynamic debugging method based on SPI protocol is characterized in that the steps include:

establishing communication connection with a host computer end by adopting an SPI protocol, and receiving an instruction from the host computer end;

according to an instruction sent by a host, communicating with a system chip through an AHB protocol and writing data or reading information into the system chip;

and after finishing data writing or information reading, sending the internal information of the system chip to the host end.

2. The SPI protocol based dynamic debugging method of claim 1, prior to commencing operation, further comprising:

and responding to a read state register instruction sent by the host terminal, inquiring the debugging state by reading the state register, and feeding back the debugging state information to the host terminal.

3. The dynamic debugging method based on SPI protocol of claim 2, wherein the system chip is read for information according to the instruction sent by the host, specifically:

configuring a base address of AHB reading operation and executing operation of reading system chip information according to an instruction sent by a host end;

and finishing the operation of reading the system chip information, responding to an SPI (serial peripheral interface) dynamic module data reading instruction sent by the host when the debugging state is in a non-busy state, and sending the system chip internal information obtained by reading the system chip to the host.

4. The dynamic debugging method based on SPI protocol of claim 2, wherein data is written to the system chip according to an instruction sent by the host, specifically:

configuring a base address of AHB write operation according to an instruction sent by a host end;

and when the debugging state is in a non-busy state, responding to a data writing instruction of AHB writing operation sent by the host end, and executing data writing operation on the system chip.

5. The dynamic debugging method according to claim 1, wherein the SPI protocol is used to establish a communication link with the host and receive commands from the host, and further comprising:

and clearing the error bit of the dynamic debugging module after receiving the instruction of clearing the state register.

6. An SPI protocol based dynamic debugging apparatus comprising a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein the processor implements the SPI protocol based dynamic debugging method according to any one of claims 1 to 5 when executing the computer program.

7. A dynamic debugging system based on SPI protocol is characterized in that the dynamic debugging system comprises a host computer end, a dynamic debugging module and a system chip;

the host end is used for inputting instructions and displaying information of the dynamic debugging module and the system chip;

the dynamic debugging module is used for establishing communication connection with the host computer end by adopting an SPI protocol and receiving an instruction from the host computer end; according to an instruction sent by a host, communicating with a system chip through an AHB protocol and writing data or reading information into the system chip; and after finishing data writing or information reading, sending the internal information of the system chip to the host end.

8. The dynamic debugging system according to claim 7, wherein the commands that the host can use for input comprise a command for reading the status register of the dynamic debugging module, a command for writing the address of the AHB read operation, a command for writing the address of the AHB write operation, a command for reading the data of the dynamic debugging module, a command for writing the data of the AHB write operation, a command for reading the CPU information 0 from the SPI, a command for reading the CPU information 1 from the SPI, a command for reading the CPU information 2 from the SPI, and a command for clearing the status register of the dynamic debugging module.

9. The dynamic debugging system according to claim 7, wherein the dynamic debugging module comprises an SPI read/write interface, a communication interface of an AHB protocol, and a register interface for querying an operating state of the CPU.

10. The SPI protocol based dynamic debugging system of claim 7 further comprising a translation module;

and the conversion module is used for connecting the host end and the dynamic debugging module and converting the USB communication into the communication adopting the SPI protocol.

Technical Field

The invention relates to the technical field of computers, in particular to a dynamic debugging method, a dynamic debugging device and a dynamic debugging system based on an SPI protocol.

Background

An SOC is an integrated circuit that includes a processor, memory, and on-chip logic. In the conventional SOC debugging scheme, JTAG (Joint Test Action Group) is mostly used, which is an abbreviation of Joint Test Action Group (Joint Test Action Group) and is a common name of standard 1149.1 of IEEE named standard Test access port and boundary scan structure, and is used for verifying functions of printed circuit boards produced by design and Test. However, the use of JTAG is not dynamic and the operation of the SOC system is controlled. Software debugging using JTAG requires the use of single step, multi-step or breakpoint, and cannot allow software to run all the time while acquiring internal information of the SOC.

Disclosure of Invention

In order to solve the technical problems, the invention provides a dynamic debugging method, a dynamic debugging device and a dynamic debugging system based on an SPI protocol, which can acquire relevant information of internal operation of a chip and dynamically debug a software operation program of the chip during the normal operation of the chip.

In order to solve the above problem, an embodiment of the present invention provides a dynamic debugging method based on an SPI protocol, including the steps of:

establishing communication connection with a host computer end by adopting an SPI protocol, and receiving an instruction from the host computer end;

according to an instruction sent by a host, communicating with a system chip through an AHB protocol and writing data or reading information into the system chip;

and after finishing data writing or information reading, sending the internal information of the system chip to the host end.

As a preferred solution, before starting the operation, the dynamic debugging method based on the SPI protocol further includes:

and responding to a read state register instruction sent by the host terminal, inquiring the debugging state by reading the state register, and feeding back the debugging state information to the host terminal.

As a preferred scheme, reading information of the system chip according to an instruction sent by the host, specifically:

configuring a base address of AHB reading operation and executing operation of reading system chip information according to an instruction sent by a host end;

and finishing the operation of reading the system chip information, responding to an SPI (serial peripheral interface) dynamic module data reading instruction sent by the host when the debugging state is in a non-busy state, and sending the system chip internal information obtained by reading the system chip to the host.

As a preferred scheme, data writing is performed on the system chip according to a command sent by the host, specifically:

configuring a base address of AHB write operation according to an instruction sent by a host end;

and when the debugging state is in a non-busy state, responding to a data writing instruction of AHB writing operation sent by the host end, and executing data writing operation on the system chip.

As a preferred scheme, the establishing a communication connection with the host end by using an SPI protocol and receiving an instruction from the host end further includes:

and clearing the error bit of the dynamic debugging module after receiving the instruction of clearing the state register.

In order to solve the same technical problem, an embodiment of the present invention provides an SPI protocol based dynamic debugging apparatus, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein the processor implements the SPI protocol based dynamic debugging method as described above when executing the computer program.

In addition, the embodiment of the invention provides a dynamic debugging system based on an SPI protocol, which comprises a host end, a dynamic debugging module and a system chip, wherein the host end is connected with the dynamic debugging module;

the host end is used for inputting instructions and displaying information of the dynamic debugging module and the system chip;

the dynamic debugging module is used for establishing communication connection with the host computer end by adopting an SPI protocol and receiving an instruction from the host computer end; according to an instruction sent by a host, communicating with a system chip through an AHB protocol and writing data or reading information into the system chip; and after finishing data writing or information reading, sending the internal information of the system chip to the host end.

As a preferred scheme, the instructions that the host can use for inputting include an instruction for reading a dynamic debug module status register, an address write instruction for AHB read operation, an address write instruction for AHB write operation, an instruction for SPI read dynamic debug module data, an data write instruction for AHB write operation, an instruction for SPI read CPU information 0, an instruction for SPI read CPU information 1, an instruction for SPI read CPU information 2, and an instruction for clearing the dynamic debug module status register.

As a preferred scheme, the dynamic debugging module comprises an SPI read-write interface, a communication interface of an AHB protocol and a register interface for inquiring the running state of the CPU.

As a preferred scheme, the dynamic debugging system based on the SPI protocol further comprises a conversion module;

and the conversion module is used for connecting the host end and the dynamic debugging module and converting the USB communication into the communication adopting the SPI protocol.

Compared with the prior art, the embodiment of the invention has the following beneficial effects:

the invention provides a dynamic debugging method, a device and a system based on an SPI protocol, wherein the SPI protocol is adopted to enable a dynamic debugging module to be in data communication with a host end, and the AHB protocol is adopted to enable the dynamic debugging module to be in data communication with a system chip, so that during the normal operation of the system chip, instruction operation is carried out on the host end, a command of the host end is executed through the dynamic debugging module, reading or writing operation is carried out on the system chip, software is enabled to operate all the time, and meanwhile, internal information of the system chip can be read at the host end, or data can be written into the system chip, and a convenient, efficient and rapid dynamic debugging method is provided for software debugging.

Drawings

Fig. 1 is a flowchart illustrating steps of a dynamic debugging method based on SPI protocol in an embodiment of the present invention;

fig. 2 is a schematic diagram of a module connection relationship of a dynamic debugging system based on an SPI protocol in an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1, the present invention provides an exemplary embodiment of a dynamic debugging method based on SPI protocol, including the steps of:

s101, establishing communication connection with a host computer end by adopting an SPI protocol, and receiving an instruction from the host computer end;

s102, according to an instruction sent by a host, communicating with a system chip through an AHB protocol and writing data or reading information into the system chip;

and S103, after data writing or information reading is finished, sending the internal information of the system chip to the host end.

It should be noted that the next SPI operation command on the host side needs to be executed according to the return value of the status register (i.e., the internal status information of the dynamic debug module).

According to the read instruction, all information of the physical address space of the system on chip (SOC system) including the storage space of the SOC system, the register space of the SOC system, and the operating state of the CPU in the SOC system can be read.

In this embodiment, the system chip is an SOC system.

In this embodiment, the SPI protocol is used to establish communication connection with the host and receive instructions from the host, the SPI communication data has a specific format and has two specific formats, namely, 16-bit format and 48-bit format, the 16-bit format includes 8-bit SPI operation instructions and 8-bit NOP instructions, and the 48-bit format includes 8-bit SPI operation instructions, 32-bit specific data and 8-bit NOP instructions.

When the dynamic DEBUG module based on the SPI protocol is used, the dynamic DEBUG module needs to be MASTER of the AHB, so the SOC system needs to be SLAVE of the AHB on the connection architecture.

Before starting operation, the dynamic debugging method based on the SPI protocol further includes:

and responding to a read state register instruction sent by the host terminal, inquiring the debugging state by reading the state register, and feeding back the debugging state information to the host terminal.

Before a host end (namely a PC end) starts instruction operation, the internal state of the dynamic debugging module is inquired to obtain whether the dynamic debugging module is in a busy state or a non-busy state; if the mobile terminal is in a busy state, stopping executing the instruction and waiting for query again; if the CPU is not busy, the instruction can be executed to read/write the address of the memory space or acquire the CPU information.

It should be noted that, when the address write operation of the AHB write operation and the address read operation of the AHB read operation are completed in sequence, the error bit of the status register is set to 1. After the address writing of the AHB reading operation is completed, the busy bit of the status register is set to 1, and the AHB reading operation is automatically performed, and if the PC performs the address writing of the AHB reading operation, the address writing of the AHB writing operation, the SPI reading of the dynamic DEBUG module data, and the data writing of the AHB writing operation, these subsequent operations are invalid.

Reading information of the system chip according to an instruction sent by a host terminal, specifically:

configuring a base address of AHB reading operation and executing operation of reading system chip information according to an instruction sent by a host end;

and finishing the operation of reading the system chip information, responding to an SPI (serial peripheral interface) dynamic module data reading instruction sent by the host when the debugging state is in a non-busy state, and sending the system chip internal information obtained by reading the system chip to the host.

Writing data into a system chip according to an instruction sent by a host terminal, specifically:

configuring a base address of AHB write operation according to an instruction sent by a host end;

and when the debugging state is in a non-busy state, responding to a data writing instruction of AHB writing operation sent by the host end, and executing data writing operation on the system chip.

During specific operation, when a user operates at a host end (namely a PC end), if the address of a storage space needs to be read, firstly, address writing of AHB reading operation is sent, then, a status register is read again, and when a dynamic debugging module is not busy, an SPI (serial peripheral interface) data reading instruction for reading dynamic module data is sent to finish data reading of the address of the storage space.

If the address of the storage space needs to be written, firstly, address writing of AHB writing operation is sent, then the status register is read again, and when the dynamic debugging module is not busy, a data writing instruction of the AHB writing operation is sent again to finish data writing of the address of the storage space.

If the register of the SOC system needs to be written, firstly, address writing of AHB writing operation is sent, then the status register is read again, and when the dynamic debugging module is not busy, a data writing instruction of the AHB writing operation is sent again to finish register data writing.

If the register of the SOC system needs to be read, firstly, address writing of AHB reading operation is sent, then the status register is read again, and when the dynamic debugging module is not busy, a data writing instruction of the AHB writing operation is sent again to finish register data writing.

It is understood that the above operations are all the configuration of the dynamic debugging module by the PC/host end. The dynamic debugging module is configured to automatically complete the behavior from the dynamic debugging module to the system chip, namely, the data writing/information reading based on the AHB protocol is automatically completed.

Adopt SPI agreement and host computer end to establish communication connection, and receive the instruction from host computer end, still include:

and clearing the error bit of the dynamic debugging module after receiving the instruction of clearing the state register.

It should be noted that, if address writing of AHB read operation is used first, and address writing of AHB write operation is used again under the condition that the dynamic DEBUG module is not busy, the dynamic DEBUG module will not complete corresponding operation, and at the same time, the error position 1 of the status register will be used, and at this time, the PC end needs to clear the error position to operate the dynamic DEBUG module again, and the user needs to operate and send an instruction to clear the status register at the host end to clear the error position of the dynamic DEBUG module.

In this embodiment, the registers of the dynamic debug module are cleared regularly according to the clear status register instruction, which is beneficial to releasing the memory space and improving the performance.

In addition, the internal state information of the dynamic debugging module is inquired by reading the state register, so that the next SPI operation instruction at the host end can be executed according to the internal state information, the dynamic debugging module is ensured to execute the instruction in a state with good performance, the error rate in the debugging process is reduced, and the dynamic regulation capability in the chip debugging process is improved.

The invention provides a dynamic debugging device based on SPI protocol, comprising a processor, a memory and a computer program which is stored in the memory and is configured to be executed by the processor, wherein the processor realizes the dynamic debugging method based on SPI protocol when executing the computer program.

Referring to fig. 2, the present invention provides an exemplary embodiment of a dynamic debug system based on an SPI protocol, including a host, a dynamic debug module, and a system chip;

the host end is used for inputting instructions and displaying information of the dynamic debugging module and the system chip;

the dynamic debugging module is used for establishing communication connection with the host computer end by adopting an SPI protocol and receiving an instruction from the host computer end; according to an instruction sent by a host, communicating with a system chip through an AHB protocol and writing data or reading information into the system chip; and after finishing data writing or information reading, sending the internal information of the system chip to the host end.

The dynamic debugging system based on the SPI protocol also comprises a conversion module;

and the conversion module is used for connecting the host end and the dynamic debugging module and converting the USB communication into the communication adopting the SPI protocol.

The dynamic debugging module is further configured to:

and responding to a read state register instruction sent by the host terminal, inquiring the debugging state by reading the state register, and feeding back the debugging state information to the host terminal.

As shown in fig. 2, the host, i.e. a computer or a PC, is connected to a conversion module for converting USB to SPI, then is connected to a dynamic debugging module (dynamic DEBUG module) through an SPI protocol, and finally is connected to a system chip (SOC system) through an AHB protocol.

In this embodiment, the dynamic debug module includes a set of standard four-wire SPI read/write interfaces, a set of communication interfaces of the AHB protocol, and a register interface for querying the running state of the CPU.

In this embodiment, the instructions that the host can be used to input include an instruction to read a state register of the dynamic debug module, an address write instruction for AHB read operation, an address write instruction for AHB write operation, an instruction to read data of the dynamic debug module by SPI, a data write instruction for AHB write operation, an instruction to read CPU information 0 by SPI, an instruction to read CPU information 1 by SPI, an instruction to read CPU information 2 by SPI, and an instruction to clear the state register of the dynamic debug module, where reading the state register of the dynamic debug module and clearing the state register of the dynamic debug module are 16-bit instructions, and the other 7 instructions are 48-bit instructions.

The running information displayed by the host computer end can display the running state of the CPU of a System On Chip (SOC), and the running information comprises a PC pointer of the running of the CPU, a running instruction and a value of a general register in the running.

Before a host end (namely a PC end) starts instruction operation, the internal state of the dynamic debugging module is inquired to obtain whether the dynamic debugging module is in a busy state or a non-busy state; if the mobile terminal is in a busy state, stopping executing the instruction and waiting for query again; if the CPU is not busy, the instruction can be executed to read/write the address of the memory space or acquire the CPU information.

It should be noted that, when the address write operation of the AHB write operation and the address read operation of the AHB read operation are completed in sequence, the error bit of the status register is set to 1. After the address writing of the AHB reading operation is completed, the busy bit of the status register is set to 1, and the AHB reading operation is automatically performed, and if the PC performs the address writing of the AHB reading operation, the address writing of the AHB writing operation, the SPI reading of the dynamic DEBUG module data, and the data writing of the AHB writing operation, these subsequent operations are invalid.

The dynamic debugging module is further configured to:

reading information of the system chip according to an instruction sent by a host terminal, specifically:

configuring a base address of AHB reading operation and executing operation of reading system chip information according to an instruction sent by a host end;

and finishing the operation of reading the system chip information, responding to an SPI (serial peripheral interface) dynamic module data reading instruction sent by the host when the debugging state is in a non-busy state, and sending the system chip internal information obtained by reading the system chip to the host.

The dynamic debugging module is further configured to:

writing data into a system chip according to an instruction sent by a host terminal, specifically:

configuring a base address of AHB write operation according to an instruction sent by a host end;

and when the debugging state is in a non-busy state, responding to a data writing instruction of AHB writing operation sent by the host end, and executing data writing operation on the system chip.

During specific operation, when a user operates at a host end (namely a PC end), if the address of a storage space needs to be read, firstly, address writing of AHB reading operation is sent, then, a status register is read again, and when a dynamic debugging module is not busy, an SPI (serial peripheral interface) data reading instruction for reading dynamic module data is sent to finish data reading of the address of the storage space.

If the address of the storage space needs to be written, firstly, address writing of AHB writing operation is sent, then the status register is read again, and when the dynamic debugging module is not busy, a data writing instruction of the AHB writing operation is sent again to finish data writing of the address of the storage space.

If the register of the SOC system needs to be written, firstly, address writing of AHB writing operation is sent, then the status register is read again, and when the dynamic debugging module is not busy, a data writing instruction of the AHB writing operation is sent again to finish register data writing.

If the register of the SOC system needs to be read, firstly, address writing of AHB reading operation is sent, then the status register is read again, and when the dynamic debugging module is not busy, a data writing instruction of the AHB writing operation is sent again to finish register data writing.

It is understood that the above operations are all the configuration of the dynamic debugging module by the PC/host end. The dynamic debugging module is configured to automatically complete the behavior from the dynamic debugging module to the system chip, namely, the data writing/information reading based on the AHB protocol is automatically completed.

The dynamic debugging module is further configured to:

and clearing the error bit of the dynamic debugging module after receiving the instruction of clearing the state register.

It should be noted that, if address writing of AHB read operation is used first, and address writing of AHB write operation is used again under the condition that the dynamic DEBUG module is not busy, the dynamic DEBUG module will not complete corresponding operation, and at the same time, the error position 1 of the status register will be used, and at this time, the PC end needs to clear the error position to operate the dynamic DEBUG module again, and the user needs to operate and send an instruction to clear the status register at the host end to clear the error position of the dynamic DEBUG module.

In this embodiment, the registers of the dynamic debug module are cleared regularly according to the clear status register instruction, which is beneficial to releasing the memory space and improving the performance.

The invention provides a dynamic debugging method, a device and a system based on an SPI protocol, wherein the SPI protocol is adopted to enable a dynamic debugging module to be in data communication with a host end, and the AHB protocol is adopted to enable the dynamic debugging module to be in data communication with a system chip, so that during the normal operation of the system chip, instruction operation is carried out on the host end, a command of the host end is executed through the dynamic debugging module, reading or writing operation is carried out on the system chip, software is enabled to operate all the time, and meanwhile, internal information of the system chip can be read at the host end, or data can be written into the system chip, and a convenient, efficient and rapid dynamic debugging method is provided for software debugging. In addition, the internal state information of the dynamic debugging module is inquired by reading the state register, so that the next SPI operation instruction at the host end can be executed according to the internal state information, the dynamic debugging module is ensured to execute the instruction in a state with good performance, the error rate in the debugging process is reduced, and the dynamic regulation capability in the chip debugging process is improved.

While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.