阅读说明：本技术 一种时钟发生器电路 (Clock generator circuit ) 是由 曹天骄 刘晓轩 李婷 李海松 吴龙胜 于 2020-05-19 设计创作，主要内容包括：本发明公开了一种时钟发生器电路,属于时钟发生器领域。本发明的时钟发生器电路,选择器由S和SN两开关控制,用于选择由偏置电压产生电路输出的参考高电平或参考低电平,比较器的两端分别接选择器的输出和锯齿波,参考电平小于锯齿波时,比较器输出高电平,选择器的两开关S＝0,SN＝1,使选择器输出参考高电平REFH,锯齿波电压不断增大,直至参考电平大于锯齿波,比较器翻转,输出低电平；参考电平大于锯齿波时,过程类似,以上翻转一直持续,从而形成振荡,振荡频率可由REFH和REFL的压差或锯齿信号产生模块的产生速率动态调节。(The invention discloses a clock generator circuit, belonging to the field of clock generators.A selector is controlled by two switches of S and SN and used for selecting a reference high level or a reference low level output by a bias voltage generating circuit, two ends of a comparator are respectively connected with the output of the selector and a sawtooth wave, when the reference level is less than the sawtooth wave, the comparator outputs the high level, two switches of the selector are S equal to 0, SN equal to 1, so that the selector outputs the reference high level REFH, the sawtooth wave voltage is continuously increased until the reference level is greater than the sawtooth wave, the comparator is turned over and outputs the low level, when the reference level is greater than the sawtooth wave, the process is similar, the turning is continued all the time, thereby forming oscillation, and the oscillation frequency can be dynamically adjusted by the pressure difference of REFH and REF L or the generation rate of a sawtooth signal generating module.)

1. A clock generator circuit, characterized by, including bias voltage generating circuit, sawtooth signal generating circuit, selector and comparator;

the bias voltage generating circuit is used for generating a reference high level REFH, a reference low level REF L and a starting voltage REF0 of the sawtooth signal generating circuit;

the comparator is used for comparing the reference level output by the selector with the sawtooth wave output by the sawtooth signal generating circuit, outputting a high level or a low level according to a comparison result, generating a C L KN signal after the output high level or low level passes through one inverter, generating a C L KP signal after passing through two inverters, and finally outputting the C L KP signal to an OUT end through the proportioner;

the C L KN signal is used for being input into a switch S of the selector, and the C L KP signal is input into a switch SN of the selector;

the C L KN signal and the C L KP signal are also used for being input into a sawtooth signal generating circuit;

when the selector outputs a reference low level REF L, the reference level at the input end of the comparator is less than the sawtooth wave, the comparator outputs a high level, in this stage, C L KN is 0, C L KP is 1, the OUT end outputs a high level, two switches S of the selector are 0, SN is 1, the selector outputs a reference high level REFH, the voltage of the sawtooth wave generated by the sawtooth signal generating circuit continuously rises until the reference high level input by the comparator is greater than the sawtooth wave, the comparator output jumps, and a low level is output;

when the selector outputs the reference low level REFH, the reference level at the input end of the comparator is greater than the sawtooth wave, the comparator outputs the low level, in the phase, C L KN is equal to 1, C L KP is equal to 0, two switches S of the selector are equal to 1, SN is equal to 0, the selector outputs the reference low level REF L, the voltage of the sawtooth wave generated by the sawtooth signal generating circuit continuously drops until the reference low level input by the comparator is less than the sawtooth wave, the comparator outputs the jump, and the high level is output.

2. The clock generator circuit of claim 1, wherein the bias voltage generating circuit comprises 4 voltage dividing resistors R1 and three sets of voltage jitter filtering circuits;

the current bias IBIAS1 is simultaneously connected with a first group of voltage jitter filtering circuits and two resistors R1 connected in series after passing through a switch, the other end of the resistor R1 is simultaneously connected with a third resistor R1 and a second group of voltage jitter filtering circuits, the other end of the third resistor R1 is simultaneously connected with a fourth resistor R1 and a third group of voltage jitter filtering circuits, and the other end of the fourth resistor R1 is connected with gnd;

the first group of voltage jitter filtering circuits is used for generating a reference high level REFH;

the second group of filtered voltage dithering circuits is used for generating a reference low level REF L;

the third set of filtered voltage dither circuits is used to generate the start voltage REF0 of the sawtooth signal generating circuit.

3. The clock generator circuit of claim 2, wherein each set of the voltage jitter filtering circuits comprises an NPN transistor Q1, a PNP transistor Q2, and a global fast reset NMOS transistor M1, a gate of the NPN transistor Q1 and a resistor R1, a drain of the NPN transistor Q1 is connected to Vdd, a source of the NPN transistor Q1 is connected to the current bias IBIAS2, a drain of the global fast reset NMOS transistor M1, and a gate of the PNP transistor Q2, a gate of the global fast reset NMOS transistor M1 is connected to the global reset signal EN, a source of the global fast reset NMOS transistor M1 and a drain of the PNP transistor Q2 are connected to gnd, a source of the PNP transistor Q2 is connected to IBIAS well as the IBIAS the high reference level REFH, the low reference level L, or the start voltage 0 of the sawtooth signal generating circuit, and a high reference level REFH, the low reference level L, or the start voltage 0 of the sawtooth signal generating circuit before the source of the PNP transistor Q2 is connected to the gnd terminal through a capacitor C1.

4. The clock generator circuit of claim 1, wherein the sawtooth signal generation circuit comprises a cascode current source, a transistor N1, a transistor N2, a transistor P1, a transistor P2, a transistor P3, a capacitor C0, and a global fast reset transistor N3, a global fast reset transistor N4;

the drain of the transistor P1 is connected with the drain of the transistor N1, the gate of the transistor N1 inputs a C L KP signal, the source of the transistor N1 is connected with the drain of the transistor N2 and then connected with a cascode current source, the gate of the transistor N2 is connected with the gate of the C L KN signal transistor N2 and simultaneously connected with the source of the transistor P2, the drain of the global quick reset transistor N4, a sawtooth signal output end and a capacitor C0, and the other end of the capacitor C0 is grounded;

the grid electrode of the global quick reset transistor N4 is connected with ENB, the source electrode of the global quick reset transistor N4 is simultaneously connected with REF0 and the drain electrode of the global quick reset transistor N3, the grid electrode of the global quick reset transistor N3 is connected with EN, and the source electrode of the global quick reset transistor N3 is grounded;

the gate of the transistor P2 is connected with the C L KN signal, the drain of the transistor P2 is connected with the source of the transistor P3 and then connected with the cascode current source, the gate of the transistor P3 is connected with the C L KP signal, and the drain of the transistor P3 is grounded;

when EN is 0 and ENB is 1, the global fast reset transistor N3 is turned off, N4 is turned on, and the sawtooth signal generation circuit operates;

when EN is 1 and ENB is 0, the global fast reset transistor N4 is turned off, N3 is turned on, and the sawtooth signal generation circuit is turned off.

Technical Field

The invention belongs to the field of clock generators, and particularly relates to a clock generator circuit.

Background

In a high-integration digital-analog mixed large circuit, a clock generator mainly provides working clocks for read-write operation, sampling and holding and signal processing of all modules. The oscillator is used as the most common clock generator, the performance of which is related to the stability, output quality and noise of the digital-analog hybrid circuit system, and generally, in a radio frequency chip system, the same oscillator needs to meet the requirements of a plurality of communication frequency bands and working modes, so that the oscillator needs to have the characteristics of high performance, wide adjustment range, stable design and the like.

FIG. 1 is a diagram of a conventional RC oscillator circuit, which is formed by reverse cascading three stages of RC ring oscillators, each stage of the oscillator unit providing a 60 DEG phase shift, satisfying the Barkhausen criterion, the oscillation frequency being determined by an RC time constant, having a large drift with process errors, and not being easily adjusted after chip trimming, and the circuit being very sensitive to noise and interference on the power supply and the substrate, and not suitable for a high noise environment of a digital-analog hybrid integrated circuit, FIG. 2 is a diagram of a differential oscillator, where Iss completely flow into a single-side circuit in each half cycle, and the swing of each node is Iss × R1.

Disclosure of Invention

The invention aims to overcome the defect that the existing oscillator is sensitive to power supply disturbance, and provides a clock generator circuit.

In order to achieve the purpose, the invention adopts the following technical scheme to realize the purpose:

a clock generator circuit includes a bias voltage generating circuit, a saw-tooth signal generating circuit, a selector, and a comparator;

the bias voltage generating circuit is used for generating a reference high level REFH, a reference low level REF L and a starting voltage REF0 of the sawtooth signal generating circuit;

the comparator is used for comparing the reference level output by the selector with the sawtooth wave output by the sawtooth signal generating circuit, outputting a high level or a low level according to a comparison result, generating a C L KN signal after the output high level or low level passes through one inverter, generating a C L KP signal after passing through two inverters, and finally outputting the C L KP signal to an OUT end through the proportioner;

the C L KN signal is used for being input into a switch S of the selector, and the C L KP signal is input into a switch SN of the selector;

the C L KN signal and the C L KP signal are also used for being input into a sawtooth signal generating circuit;

when the selector outputs a reference low level REF L, the reference level at the input end of the comparator is less than the sawtooth wave, the comparator outputs a high level, in this stage, C L KN is 0, C L KP is 1, the OUT end outputs a high level, two switches S of the selector are 0, SN is 1, the selector outputs a reference high level REFH, the voltage of the sawtooth wave generated by the sawtooth signal generating circuit continuously rises until the reference high level input by the comparator is greater than the sawtooth wave, the comparator output jumps, and a low level is output;

when the selector outputs the reference low level REFH, the reference level at the input end of the comparator is greater than the sawtooth wave, the comparator outputs the low level, in the phase, C L KN is equal to 1, C L KP is equal to 0, two switches S of the selector are equal to 1, SN is equal to 0, the selector outputs the reference low level REF L, the voltage of the sawtooth wave generated by the sawtooth signal generating circuit continuously drops until the reference low level input by the comparator is less than the sawtooth wave, the comparator outputs the jump, and the high level is output.

Further, the bias voltage generating circuit comprises 4 voltage dividing resistors R1 and three groups of voltage jitter filtering circuits;

the current bias IBIAS1 is simultaneously connected with a first group of voltage jitter filtering circuits and two resistors R1 connected in series after passing through a switch, the other end of the resistor R1 is simultaneously connected with a third resistor R1 and a second group of voltage jitter filtering circuits, the other end of the third resistor R1 is simultaneously connected with a fourth resistor R1 and a third group of voltage jitter filtering circuits, and the other end of the fourth resistor R1 is connected with gnd;

the first group of voltage jitter filtering circuits is used for generating a reference high level REFH;

the second group of filtered voltage dithering circuits is used for generating a reference low level REF L;

the third set of filtered voltage dither circuits is used to generate the start voltage REF0 of the sawtooth signal generating circuit.

Further, each group of the voltage jitter filtering circuits includes an NPN transistor Q1, a PNP transistor Q2, and a global fast reset NMOS transistor M1, the gate of the NPN transistor Q1 and a resistor R1, the drain of the NPN transistor Q1 is connected to Vdd, the source of the NPN transistor Q1 is connected to the current bias IBIAS2, the drain of the global fast reset NMOS transistor M1, and the gate of the PNP transistor Q2, the gate of the global fast reset NMOS transistor M1 is connected to the global reset signal EN, the source of the global fast reset NMOS transistor M1, the drain of the PNP transistor Q2 are connected to gnd, the source of the PNP transistor Q2 is connected to the IBIAS3, the reference high level REFH, the reference low level REF L, or the start voltage of the sawtooth signal generating circuit 0, and the reference high level REFH, the reference low level REF L, or the start voltage of the sawtooth signal generating circuit 0 before being connected to the source of the PNP transistor Q2 is connected to gnd through a capacitor C1.

Further, the sawtooth signal generating circuit comprises a cascode current source, a transistor N1, a transistor N2, a transistor P1, a transistor P2, a transistor P3, a capacitor C0, a global fast reset transistor N3 and a global fast reset transistor N4;

the drain of the transistor P1 is connected with the drain of the transistor N1, the gate of the transistor N1 inputs a C L KP signal, the source of the transistor N1 is connected with the drain of the transistor N2 and then connected with a cascode current source, the gate of the transistor N2 is connected with the gate of the C L KN signal transistor N2 and simultaneously connected with the source of the transistor P2, the drain of the global quick reset transistor N4, a sawtooth signal output end and a capacitor C0, and the other end of the capacitor C0 is grounded;

the grid electrode of the global quick reset transistor N4 is connected with ENB, the source electrode of the global quick reset transistor N4 is simultaneously connected with REF0 and the drain electrode of the global quick reset transistor N3, the grid electrode of the global quick reset transistor N3 is connected with EN, and the source electrode of the global quick reset transistor N3 is grounded;

the gate of the transistor P2 is connected with the C L KN signal, the drain of the transistor P2 is connected with the source of the transistor P3 and then connected with the cascode current source, the gate of the transistor P3 is connected with the C L KP signal, and the drain of the transistor P3 is grounded;

when EN is 0 and ENB is 1, the global fast reset transistor N3 is turned off, N4 is turned on, and the sawtooth signal generation circuit operates;

when EN is 1 and ENB is 0, the global fast reset transistor N4 is turned off, N3 is turned on, and the sawtooth signal generation circuit is turned off.

Compared with the prior art, the invention has the following beneficial effects:

the invention relates to a clock generator circuit, wherein a selector is controlled by an S switch and an SN switch and is used for selecting a reference high level or a reference low level output by a bias voltage generating circuit, two ends of a comparator are respectively connected with the output of the selector and a sawtooth wave, the comparator outputs the high level when the reference level is less than the sawtooth wave, the two switches S of the selector are 0 and SN is 1, so that the selector outputs the reference high level REFH, the sawtooth wave voltage is continuously increased until the reference level is greater than the sawtooth wave, the comparator overturns to output the low level, the process is similar when the reference level is greater than the sawtooth wave, the overturning is continuous all the time, thereby forming oscillation, the oscillation frequency can be dynamically adjusted by the pressure difference of the REFH and REF L or the generation rate of a sawtooth signal generating module, the oscillation frequency of the clock generator circuit is flexibly adjustable, the adjustment range of the frequency is further increased, and power supply and ground noises can not directly act on the comparator to reduce the output jitter.

Further, the bias voltage generating circuit is composed of a resistance voltage dividing part, a plurality of PNP tubes and NPN tubes for filtering voltage jitter, and also comprises a plurality of global quick reset tubes, wherein the grid end of the global quick reset tubes is connected with a reset signal controlled by a time sequence, and the bias voltage generating circuit generates a reference high level REFH, a reference low level REF L and a starting voltage REF0 of the sawtooth signal generating circuit.

Furthermore, the sawtooth signal generating circuit is composed of a current bias, a switch tube controlled by C L KN and C L KP, a capacitor and a global quick reset tube, and generates a sawtooth signal matched with a time sequence, the current bias adopts a current source design of accurate matching of up and down pulling, the duty ratio of an output clock is ensured, and phase noise is reduced, on the other hand, the global quick reset tube can enable the sawtooth signal to be quickly started or shut off, and the response of a system is tracked in real time.

Drawings

FIG. 1 is a diagram of a conventional RC oscillator circuit;

FIG. 2 is a diagram of a differential oscillator circuit;

FIG. 3 is a diagram of a low jitter balanced oscillator according to the present invention;

FIG. 4 is a diagram of a bias voltage generating circuit according to the present invention;

FIG. 5 is a diagram of a sawtooth signal generating circuit according to the present invention;

FIG. 6 is a waveform diagram of the comparator output of the present invention.

Detailed Description

In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

The invention is described in further detail below with reference to the accompanying drawings:

the invention belongs to the technical field of clock generators, and the clock generator has the advantages of high starting speed, flexible fine adjustment of frequency and excellent stability. The oscillator circuit is improved on the basis of the existing oscillator circuit, the sawtooth signal generating circuit matched with the pull-up and the pull-down is provided, reference voltage selection logic is added, the frequency generated by the oscillator is flexible and adjustable, and the low-jitter balanced type wide-range on-chip clock generator suitable for a high-integration digital-analog mixed large circuit is realized.

Referring to fig. 3, fig. 3 is a structural diagram of the low jitter balanced oscillator of the present invention, wherein a bias voltage generating circuit, a saw-tooth signal generating circuit, a selector and a comparator form an oscillator feedback loop, two switches S and SN of the selector are respectively connected to C L KN and C L KP, which are inverse signals, when C L KN is equal to 0, C L KP is equal to 1, i.e., S is equal to 0, SN is equal to 1, the selector outputs a reference high level REFH output by the bias voltage generating circuit, and when C L KN is equal to 1, C L KP is equal to 0, i.e., S is equal to 1, SN is equal to 0, the selector outputs a reference low level L output by the bias voltage generating circuit;

referring to fig. 6, fig. 6 is a waveform diagram of an output of a comparator, two ends of the comparator are respectively connected with an output of a selector and a sawtooth wave output by a sawtooth signal generating circuit, when a reference level is less than the sawtooth wave, the comparator outputs a high level, in the stage, C L KN is 0, C L KP is 1, an OUT end outputs a high level, two switches S of the selector are 0, SN is 1, the selector outputs a high level REFH, in the stage, the voltage of the sawtooth wave generated by the sawtooth signal generating circuit continuously rises until the reference level of the input end of the comparator is greater than the sawtooth wave, the comparator overturns, the OUT end outputs a low level, when the reference level is greater than the sawtooth wave, the comparator outputs a low level, C L KN is 1, C L KP is 0, the two switches S of the selector are 1, SN is 0, the output reference level of the selector is L, in the stage, the sawtooth wave generates a sawtooth wave, the sawtooth wave generates a high level, the comparator continuously falls, the comparator outputs the reference level is lower level, and the output of the sawtooth wave is converted until the high level is less than the output, the output of the high level, the output of the sawtooth wave, and the output of the comparator is inverted.

Referring to fig. 4, fig. 4 is a structure diagram of the bias voltage generating circuit of the present invention, which includes a resistor voltage dividing portion consisting of 4R 1, three NPN transistors Q1 and PNP transistor Q2 for filtering voltage jitter, and generates reference high and low levels REFH and REF L to be output to the selector, respectively, and an initial voltage ref0 of the saw-tooth signal generating circuit, the flip speed of the comparator can be changed by changing the voltage difference between REFH and REF L, and further the frequency of the oscillation output can be changed, the bias voltage generating circuit further includes a plurality of global fast reset NMOS transistors M1, the gate terminal of M1 is connected to a global reset signal EN, and the output of the bias voltage generating circuit can be reset in real time.

Referring to fig. 5, fig. 5 is a circuit diagram of a saw-tooth signal generating circuit, which includes a cascode current source, switching transistors N1, N2, P2, a capacitor C2, and global fast reset transistors N2, N2 controlled by C L KN and C L KP, and generates a saw-tooth signal matched with timing, a gate terminal of the transistor P2 is connected to gnd and is In a constant on state, when C2 KN is equal to 0 and C2 KP is equal to 1, the transistors N2 and P2 are turned on, N2 and P2 are turned off, a current source Ip charges the capacitor C2 through the transistor P2, the transistors P2 and N2 are discharged to ground through a current source In, therefore, an OUT terminal output voltage value of the saw-tooth signal output increases linearly until the comparator output jumps, so that the C72 KN is equal to 1 and C2 KP 0, the transistor N2 and P2 are discharged to ground, and the capacitor N2 is discharged to a reference voltage level of the comparator output is decreased until the transistor N2 is turned on and the transistor N2 is turned off, the capacitor C2 is compared, the transistor N2, and the transistor N2 is turned off.

The current bias adopts a cascode current source design with accurate matching of pull-up and pull-down, so that the rising and falling rates of the sawtooth signals are ensured to be accurate and consistent, the duty ratio of an output clock is further ensured, and the phase noise is reduced.

The global fast reset tubes N3 and N4 are respectively controlled by EN and ENB signals, when EN is 0 and ENB is 1, N3 is turned off, N4 is turned on, and the sawtooth signal generating circuit works normally; when EN is 1 and ENB is 0, N4 is turned off and N3 is turned on, and the sawtooth signal generation circuit is turned off quickly, so that the system response can be tracked in real time.

The above-mentioned contents are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and any modification made on the basis of the technical idea of the present invention falls within the protection scope of the claims of the present invention.