阅读说明：本技术 电子装置和噪声去除系统 (Electronic device and noise removal system ) 是由 小松孝彰 于 2020-01-22 设计创作，主要内容包括：本发明提供一种电子装置和噪声去除系统,该电子装置能够去除输入信号的毛刺噪声,并且对去除了毛刺噪声的次数进行计数并记录该次数。本公开所涉及的电子装置具有去除信号中包含的毛刺的功能,具备：毛刺去除电路,其去除所输入的信号的毛刺；以及计数部,其对去除了毛刺的次数进行计数。(The invention provides an electronic device and a noise removal system, wherein the electronic device can remove the burr noise of an input signal, count the number of times of removing the burr noise and record the number of times. An electronic device according to the present disclosure has a function of removing a glitch included in a signal, and includes: a glitch removal circuit that removes a glitch of an input signal; and a counting unit that counts the number of times the burr is removed.)

1. An electronic device having a function of removing a glitch included in a signal, the electronic device comprising:

a glitch removal circuit that removes a glitch of an input signal; and

and a counting unit that counts the number of times the burr is removed.

2. The electronic device of claim 1,

the burr removal circuit includes:

an n-stage original signal delay element to which an original signal is input, wherein n is an integer of 1 or more; and

an output signal generating section for generating an output signal based on the signal output from the original signal delay element and the original signal,

the counting unit includes:

an output signal delay element of n stages to which the output signal is input;

a determination signal generation unit that generates a determination signal indicating whether or not the glitch is removed, based on a current output signal, a signal output from the output signal delay element, and a signal output from a final stage of the original signal delay element; and

and an increment unit having an incrementer for increasing the number of times the burr is removed and holding the increased number of times, the incrementer being incremented based on the determination signal.

3. The electronic device of claim 2,

the determination signal generating unit generates a determination signal having a value indicating that the glitch is removed, when the current output signal is equal to the signals output from all the output signal delay elements and the current output signal is different from the signal output from the last stage of the original signal delay element.

4. The electronic device of claim 2 or 3,

the increasing section increases the number of times of removing the burr when the determination signal is a value indicating that the burr is removed and is different from a value of the determination signal at the previous time.

5. The electronic device of any one of claims 2 to 4,

the apparatus further includes an initialization circuit that initializes the original signal delay element, the output signal delay element, and the increment unit when a reset signal is input.

6. The electronic device of any of claims 2-5,

the output signal generating unit outputs a logical or of the signal output from each of the original signal delay elements and the original signal.

7. The electronic device of any of claims 2-5,

the output signal generating unit outputs a logical and of the signal output from each of the original signal delay elements and the original signal.

8. The electronic device of any of claims 2-5,

the output signal generation unit generates an output signal based on a logical exclusive or of a logical or and of a signal output from each of the n-stage original signal delay elements and an original signal.

9. The electronic device of claim 8,

the output signal generation unit further includes a first switch for enabling a logical OR and a second switch for enabling a logical AND.

10. The electronic device according to any one of claims 1 to 9, further comprising:

a determination unit that determines whether or not the count value of the count unit exceeds a predetermined threshold; and

and a notification unit configured to notify that the count value of the count unit exceeds a predetermined threshold.

11. The electronic device of claim 10,

the notification unit displays on a screen that the count value of the count unit exceeds a predetermined threshold.

12. The electronic device of claim 10 or 11,

the notification unit transmits information indicating that the count value of the counting unit exceeds a predetermined threshold to the outside.

13. The electronic device of any one of claims 1 to 12,

the recording unit records the count value of the counting unit in a log periodically or when a predetermined event occurs.

14. The electronic device of any one of claims 1 to 13,

the device further comprises a count transmission unit for transmitting the count value of the count unit to the outside.

15. A noise removal system is provided with:

the electronic device of claim 14; and

an information processing device that receives the count value from the electronic device and records the received count value.

Technical Field

The invention relates to an electronic device and a noise removal system.

Background

In the circuit, a beard-like pulse noise having a narrower pulse width than a normal pulse width is called a glitch (glitch). In a logic circuit, when two input signals change at close timing, a glitch may occur in an output. This is a phenomenon mainly caused by a signal delay time of two signals, and is called contention (racing).

In addition, when a plurality of output terminals are simultaneously changed in the same direction in an integrated circuit or the like, a glitch may occur in a terminal in the vicinity, which is referred to as simultaneous switching noise. As another example, when two signals are present in parallel, when one of the signals changes, the other signal may generate a glitch, which is called crosstalk (crosstalk). In addition to this, burrs may be generated due to various causes such as electrostatic discharge and radiation of electromagnetic field.

These glitches sometimes adversely affect the next stage and the logic circuits following the next stage. Therefore, a circuit for removing the glitch noise has been proposed (for example, see patent document 1).

Disclosure of Invention

Problems to be solved by the invention

In the glitch removal circuit described in patent document 1, a signal is input to an n-stage D flip-flop circuit. When the outputs of the D flip-flop circuits of the n stages match, the output of the last stage of the D flip-flop of the n stages is output. On the other hand, when the outputs of the D flip-flop circuits in the n-stage D flip-flop circuits do not match, it is determined that the glitch noise has occurred. Also, the output of the previous time of the last stage of the D flip-flop of the n stages is maintained, thereby removing the glitch noise.

In addition, when a large pulse width glitch noise is generated, which cannot be removed by the glitch removal circuit, it is a fatal error. Therefore, it is desirable to avoid the generation of such large pulse width glitch noise that cannot be removed. As a factor of generation of the glitch noise in the signal, an installation environment of the logic circuit, failure (deterioration) of the component, and the like are conceivable. Before generating a large pulse width glitch noise that cannot be removed, it is considered that a small pulse width glitch noise that can be removed may be generated. Therefore, it is desirable to record that the glitch noise is removed at a stage when the glitch noise having a small pulse width that can be removed is generated. It is desirable to record the number of times the glitch noise is removed in advance.

Means for solving the problems

An electronic device according to an aspect of the present disclosure is an electronic device having a function of removing a glitch included in a signal, and includes: a glitch removal circuit that removes a glitch of an input signal; and a counting unit that counts the number of times the burr is removed.

ADVANTAGEOUS EFFECTS OF INVENTION

According to one embodiment of the present disclosure, it is possible to remove the glitch noise of the input signal, and to count and record the number of times the glitch noise is removed.

Drawings

Fig. 1 is a circuit diagram illustrating an electronic device according to a first embodiment of the present disclosure.

Fig. 2 is a circuit diagram illustrating an electronic device according to a second embodiment of the present disclosure.

Fig. 3 is a timing diagram illustrating changes in input signals, output signals, and incremental values of the electronic device of fig. 2.

Fig. 4 is a circuit diagram illustrating an electronic device according to a third embodiment of the present disclosure.

Fig. 5 is a circuit diagram illustrating an electronic device according to a fourth embodiment of the present disclosure.

Fig. 6 is a circuit diagram illustrating an electronic device according to a fifth embodiment of the present disclosure.

Fig. 7 is a circuit diagram illustrating an electronic device according to a sixth embodiment of the present disclosure.

Fig. 8 is a circuit diagram illustrating an electronic device according to a seventh embodiment of the present disclosure.

Fig. 9 is a circuit diagram illustrating an initialization circuit that can be added to the electronic devices according to the first to fifth embodiments of the present disclosure.

Fig. 10 is a circuit diagram illustrating an electronic device according to an eighth embodiment of the present disclosure.

Fig. 11 is a circuit diagram illustrating an electronic device according to a ninth embodiment of the present disclosure.

Fig. 12 is a circuit diagram illustrating an electronic device according to a tenth embodiment of the present disclosure.

Fig. 13 is a circuit diagram illustrating an electronic device according to an eleventh embodiment of the present disclosure.

Fig. 14 is a circuit diagram illustrating wirings when an initialization circuit is added to the electronic devices according to the tenth and eleventh embodiments of the present disclosure.

Fig. 15 is a circuit diagram illustrating an electronic device according to a twelfth embodiment of the present disclosure.

Fig. 16 is a block diagram showing the configuration of an embodiment of the noise removal system according to the present disclosure.

Description of the reference numerals

1. 1a, 1b, 1c, 1d, 1e, 1f, 1g, 1h, 1i, 1 k: an electronic device; 2: an information processing device; 10. 10a, 10b, 10c, 10 d: a burr removal circuit; 12: an original signal delay element; 13. 13a, 13b, 13c, 13 d: an output signal generating section; 20. 20a, 20b, 20c, 20d, 20e, 20i, 20j, 20 k: a counting section; 21: an output signal delay element; 22. 22a, 22b, 22c, 22 e: a determination signal generation unit; 23. 23e, 23i, 23 k: an increasing section; 30: an electronic device control unit (determination unit); 40: a notification unit; 50: an electronic device recording section; 60: an electronic device communication unit (count transmission unit); 80: initializing a circuit; 131: an output generation OR circuit; 132: an output generation AND circuit; 133: a first switch; 134: a second switch; 231. 232 and 233: an incrementer.

Detailed Description

Embodiments of an electronic device according to the present disclosure will be described below with reference to fig. 1 to 15.

[ first embodiment ]

Fig. 1 is a circuit diagram illustrating an electronic device 1 according to a first embodiment of the present disclosure. The electronic device 1 has a function of removing a glitch included in a signal. In the following description, "glitch noise" and "glitch" may be simply referred to as "glitch".

The electronic device 1 includes: a glitch removal circuit 10 that removes a glitch of an input signal; a counting unit 20 that counts the number of times the burr removing circuit 10 has removed the burrs; an electronic device control unit 30 that controls the count value by the count unit 20; a notification unit 40 that notifies that the count value of the count unit 20 exceeds a predetermined threshold value; an electronic device recording unit 50 that records the count value of the counting unit 20 in a log periodically or when a predetermined event occurs; and an electronic device communication unit 60 that communicates with an external device.

The burr removal circuit 10 includes a signal input terminal 11, n-stage (n is an integer of 1 or more) original signal delay elements 12, an output signal generation unit 13 that generates an output signal, and a signal output terminal 14 that outputs the output signal.

The signal input terminal 11 is a terminal to which an external device not shown is connected. The signal input terminal 11 receives a signal output from an external device. The signal input terminal 11 is used to receive input of a signal that may include a glitch due to an installation environment of an external device, a failure (degradation) of a component, or the like, for example. When the signal input to the signal input terminal 11 is not synchronized with the glitch removal circuit 10, a multi-stage (typically, 2-stage or 3-stage) D flip-flop called a synchronizer (not shown) may be inserted between the signal input terminal 11 and the glitch removal circuit 10 to synchronize the input signal. Hereinafter, a signal input to the signal input terminal 11 or a signal passing through the synchronizer is also referred to as an "original signal".

The n-stage original signal delay element 12 is a circuit to which an original signal is input. The input terminal of the original signal delay element 12 of the first stage among the original signal delay elements 12 of the n stages is connected to the signal input terminal 11. The output terminal of the original signal delay element 12 of the first stage is connected to the input terminal of the original signal delay element 12 of the next stage. The output terminal of the original signal delay element 12 of the next stage is connected to the input terminal of the original signal delay element 12 of the next stage. In this manner, the n-stage original signal delay elements 12 are connected in series to the signal input terminal 11. In the present embodiment, each of the n-stage original signal delay elements 12 is, for example, a D flip-flop. Each of the n-stage original signal delay elements 12 receives a clock signal having the same rise timing. The original signal delay element 12 of the first stage latches the signal input terminal 11 or the output (original signal) of the synchronizer at the time of the rise of the clock signal. Further, each of the original signal delay elements 12 of the second stage and the n-1 stage subsequent to the second stage latches the output of the previous stage at the rise of the clock signal. In addition, the illustration of a circuit for inputting a clock signal is omitted for simplicity.

The output signal generating unit 13 is a circuit that generates an output signal from the signal output from each of the n-stage original signal delay elements 12 and the original signal. The input terminal of the output signal generating unit 13 is connected to the output and signal input terminal 11 of each of the n-stage original signal delay elements 12.

The signal output terminal 14 is a terminal for outputting a signal from which the burr is removed. The signal output terminal 14 is connected to an output terminal of the output signal generating unit 13.

The counting unit 20 includes: an output signal delay element 21 of n stages to which an output signal is input; a determination signal generating unit 22 that generates a determination signal indicating whether or not the burr removing circuit 10 has removed the burr; and an increment unit 23 for counting the number of times the burr is removed based on the determination signal generation unit 22.

The output signal delay element 21 of the n stages is a circuit to which an original signal is input. The input terminal of the output signal delay element 21 of the first stage among the output signal delay elements 21 of the n stages is connected to the output terminal of the output signal generating section 13. Further, the output terminal of the output signal delay element 21 of the first stage is connected to the input terminal of the output signal delay element 21 of the next stage. The output terminal of the output signal delay element 21 of the next stage is connected to the input terminal of the output signal delay element 21 of the further next stage. In this manner, the output signal delay elements 21 of the n stages are cascade-connected to the output signal generating unit 13. In the present embodiment, each of the output signal delay elements 21 of the n stages is, for example, a D flip-flop. The clock signal having the same rise timing is input to each of the output signal delay elements 21 of the n stages. The output signal delay element 21 of the first stage latches the current output signal at the rise of the clock signal. The output signal delay elements 21 in the second stage and subsequent stages latch the outputs of the output signal delay elements 21 in the previous stage at the rise of the clock signal.

The determination signal generation unit 22 generates a determination signal indicating whether or not the glitch is removed, based on the current output signal, the signal output from the output signal delay element 21, and the signal output from the last stage of the original signal delay element 12.

The increasing section 23 has an incrementer 231 that increases the number of times the burr is removed and holds the increased number of times. The incrementer 231 is a circuit that increments (counts) the number of times the burr is removed. The increment unit of the present embodiment directly inputs the determination signal output from the determination signal generation unit 22 to the input terminal of the increment device 231. The output terminal of the step-up mechanism 231 is connected to an electronic device control unit 30, which will be described later, via a bus bar 70 and the like.

The incrementer 231 is constituted by, for example, an addition operator and a register. When the determination signal is at a high level, the incrementer 231 increments (increments) the number of times of removal of the glitch stored in the register by + 1.

The counter 20 checks every clock cycle whether or not the glitch is removed and increments the incrementer 231. That is, when the time width of the burr removed by the burr removal circuit 10 is two clock cycles or more, the counter 20 counts the number of times the burr is removed as a plurality of times.

The electronic device control unit 30 may be configured to have a processor (CPU) that performs an operation instructed by a program. The output value of the incrementer 231 is acquired to control the notification unit 40, the electronic device recording unit 50, and the electronic device communication unit 60, which will be described later.

Specifically, the electronic device control unit 30 has a function as a determination unit that determines whether or not the number of times of removing burrs exceeds a predetermined threshold value in order to control the notification unit 40. The electronic device control unit 30 has a function of determining the timing of recording the count value in the electronic device recording unit 50. The electronic device control unit 30 has a function of transmitting the count value transmitted to the outside to the electronic device communication unit 60. The various functions of the electronic device control unit 30 can be realized by a part of a program for instructing the operation of the processor.

The notification unit 40 is, for example, a display device such as a monitor having a screen, a playback device generating a sound, an output device having a light source for lighting, or the like. The notification unit 40 may be configured to notify that the counted number of times exceeds a predetermined threshold value by displaying, generating a sound, lighting a light source, or the like. The notification unit 40 can also promote improvement of installation environment and replacement of parts.

The electronic device recording unit 50 may have a storage device such as a memory or a hard disk drive. The electronic device recording unit 50 preferably records the count value of the counting unit 20 and the time when the count value is confirmed.

As an event of recording the count value in the electronic device recording unit 50, for example, occurrence of a fatal error can be cited.

The electronic device communication unit 60 functions as a count transmission unit that transmits the count value of the counting unit 20 to the outside. The electronic device communication unit 60 may be configured to include, for example, an ethernet communication module, a wireless communication module, and the like.

The electronic device communication unit 60 can also be used as a second notification unit that: when the number of times of deburring exceeds a predetermined threshold, the second notification unit transmits information indicating that the count value of the count unit 20 exceeds the predetermined threshold to an external device.

According to the electronic device 1 of the first embodiment of the present disclosure described above, the following effects are exhibited.

The electronic device 1 is an electronic device 1 having a function of removing a glitch included in a signal, and includes: a glitch removal circuit 10 that removes a glitch of an input signal; and a counting unit 20 for counting the number of times the burr is removed. This makes it possible to count the number of times the input signal glitch noise is removed, and record the number of times. Therefore, the electronic apparatus 1 can confirm the number of times the burr is removed, for example, the number of times the burr is removed in a factory test of the electronic apparatus 1. Thus, if the number of times of removing the burr is other than 0 times, the individual electronic device 1 can be rejected. In addition, at the time of substrate development or device development, a test in which noise is applied is performed, whereby the noise resistance of the substrate or device can be evaluated. If the number of times of removing the burr is small, it can be said that the noise resistance of the substrate or the device is high (good design). On the contrary, if the number of times of removing the burr is large, it can be said that the noise resistance of the substrate or the device is low (poor design). This is beneficial for improving the design of the substrate or the device.

In the electronic device 1, the burr removal circuit 10 includes: an n-stage original signal delay element 12 to which an original signal is input; and an output signal generating unit 13 for generating an output signal based on the signal output from the original signal delay element 12 and the original signal. This enables output of an output signal from which the glitch is appropriately removed. In the electronic device 1, the counting unit 20 includes: an output signal delay element 21 of n stages to which an output signal is input; a determination signal generation unit 22 that generates a determination signal indicating whether or not the glitch is removed, based on the current output signal, the signal output from the output signal delay element, and the signal output from the final stage of the original signal delay element 12; and an increasing unit 23 having an incrementer 231 for increasing the number of times the burr is removed and holding the increased number of times, and increasing the incrementer 231 based on the determination signal. Thus, the number of times the burr is removed can be accurately counted.

The electronic device 1 further includes: an electronic device control unit 30 that determines whether or not the count value of the counting unit 20 exceeds a predetermined threshold value; and a notification unit 40 that notifies that the count value of the count unit 20 exceeds a predetermined threshold. This makes it possible to notify when the number of burrs exceeds a predetermined number. According to this configuration, since notification can be made before a large burr that cannot be removed is input, improvement can be promoted before an error due to the large burr occurs.

In the electronic device 1, the notification unit 40 can display on the screen that the count value of the count unit 20 exceeds the predetermined threshold. This makes it possible to clearly notify that the number of burrs exceeds a predetermined number of times.

In the electronic device 1, the electronic device communication unit 60 as the second notification unit transmits information indicating that the count value of the counting unit 20 exceeds the predetermined threshold to the outside. This makes it possible to recognize that the number of burrs exceeds a predetermined number of times by an external device, and thus a system capable of grasping the states of the plurality of electronic devices 1 at once can be configured.

The electronic device 1 further includes an electronic device recording unit 50 that records the count value of the counting unit in a log periodically or when a predetermined event occurs. This makes it possible to check the change in the state of occurrence of the burr later.

[ second embodiment ]

Fig. 2 is a circuit diagram illustrating an electronic device 1a according to a second embodiment of the present disclosure. The electronic device 1a is a device for removing a glitch in a low level direction which occurs in an input signal of a high level. In the following description, the same components as those of the embodiment described above are denoted by the same reference numerals, and redundant description thereof is omitted.

The electronic device 1a of the present embodiment includes: a glitch removal circuit 10a that removes a glitch of an input signal; a counting unit 20a that counts the number of times the burr removing circuit 10a has removed the burr; and an electronic device control unit 30 that performs control based on the count value of the count unit 20 a.

The electronic device control unit 30 of the electronic device 1a of the present embodiment is the same as the electronic device control unit 30 of the electronic device 1 of the first embodiment. The electronic device 1a of the present embodiment may also include the notification unit 40, the electronic device recording unit 50, and the electronic device communication unit 60, but illustration and description thereof are omitted.

The burr removal circuit 10a includes a signal input terminal 11, n-stage (n is an integer of 1 or more) original signal delay elements 12, an output signal generation unit 13a that generates an output signal, and a signal output terminal 14 that outputs the output signal.

The output signal generator 13a is an output OR generating circuit 131 that outputs a logical OR. The output signal generating unit 13a outputs the logical or of the signal output from each of the n-stage original signal delay elements 12 and the original signal.

In the above-described burr removal circuit 10a, the original signal is input to the signal input terminal 11. Therefore, a signal that may contain a glitch noise in the low level direction when the signal is at the high level is input to the original signal delay element 12. The n-stage original signal delay element 12 latches the original signal or the output signal of the previous-stage original signal delay element 12 according to the rise of the clock signal. The original signal is input to the output signal generating unit 13 a. The output of each original signal delay element 12 is input to the output signal generating unit 13 a.

In the case where the glitch overlaps with the rise of the clock and has a sufficient pulse width to satisfy the setup time and the hold time, the original signal delay element 12 of the first stage latches a low level according to the rise of the clock. At this time, at the next rise of the clock, the original signal delay element 12 of the second stage latches the low level as the output of the original signal delay element 12 of the first stage. At the next rise of the clock, the original signal delay element 12 of the third stage latches the low level as the output of the original signal delay element 12 of the second stage. In this manner, the original signal delay element 12 of the nth stage latches a low level at the rising of the nth clock signal. However, since the other original signal delay element 12 latches the high level, the output signal generating section 13a outputs the high level.

The output signal generating section 13a outputs a high level unless the original signal is at a low level and all of the original signal delay elements 12 of the n stages latch a low level. That is, unless the low level continues n +1 times in the original signal, the output signal generating section 13a outputs the high level. Thus, the burr removal circuit 10a can remove the burr in the low level direction having a width of up to n clock cycles.

The counting unit 20a includes: an output signal delay element 21 of n stages to which an output signal is input; a determination signal generating unit 22a that generates a determination signal indicating whether or not the burr removing circuit 10 has removed the burr; and an increment unit 23 for counting the number of times the burr is removed based on the determination signal generation unit 22 a.

The determination signal generation unit 22a includes: a delayed signal inverter 221 that inverts a signal output from the last stage of the original signal delay element 12; AND a determination AND circuit 222 to which the output of the delayed signal inverter 221, the present output signal, AND the signals output from all the output signal delay elements 21 are input, AND which outputs the logical AND of them.

The determination signal generation unit 22a outputs the following determination signals: the determination signal is at a high level indicating that the glitch is removed only when the current output signal and the output signal of the past n times are at a high level and the original signal of the past n times is at a low level, and the determination signal is at a low level in other cases.

Fig. 3 shows the clock signal, the original signal, the output signal, and the continuous time change of the count of the incrementer 231 in the electronic device 1 a. Fig. 3 shows the case where n is 1.

When the original signal becomes high level, the output signal generating section 13a makes the output signal transition to high level. When the output signal is at a high level, the output signal generating unit 13a keeps the output signal at a high level unless the original signal is at a low level at the time of rising of the clock signal n +1 times or more in succession. Therefore, when the clock signal is delayed by n clock cycles from the time when the original signal is changed to the low level, the output signal transitions to the low level. Therefore, even if the original signal is at a low level for a short time of n clock cycles or less due to the glitch noise, the output signal generating section 13a keeps the output signal at a high level, that is, outputs the output signal from which the glitch is removed.

The determination signal generating unit 22a sets the determination signal to the high level only when the output of the last-stage original signal delay element 12, which has an output signal that continues to be the high level n +1 times before the current time and outputs the same value as the original signal n times before, is at the low level indicating the glitch. That is, when the output signal remains at the high level n +1 times despite the low level of the original signal at the rising time of the clock n times before, the determination signal generating unit 22a outputs the determination signal indicating that the glitch is removed.

The increment section 23 increments the count of the incrementer 231 by 1 each time the determination signal output from the determination signal generation section 22a becomes high level. When n is 2 or more and the glitch rises over a plurality of clocks, the determination signal generating section 22a keeps the determination signal at a high level for a plurality of clock cycles. Thus, when the width of the glitch is large, the count of the incrementer 231 is increased by 1 or more.

According to the electronic device 1a of the second embodiment described above, the following effects are obtained in addition to the effects of the first embodiment described above.

In the electronic device 1a, when the current output signal is equal to the signals output from all the output signal delay elements 21 and the current output signal is different from the signal output from the last stage of the original signal delay element 12, the determination signal generating unit 22a generates a determination signal having a value indicating that the glitch is removed. Thus, the number of times the burr is removed can be accurately counted.

In the electronic device 1a, a signal that may contain a glitch noise in a low level direction when the signal is at a high level is input to the original signal delay element 12, and the output signal generation unit 13a outputs a logical or of the signal output from each original signal delay element and the original signal. Thus, the output signal generating unit 13a outputs a high level except for the case where the outputs of all the original signal delay elements 12 and the original signals are not at a high level. Thus, even in the case where the pulse width of the glitch rises over a plurality of clocks, the glitch can be removed.

[ third embodiment ]

Fig. 4 is a circuit diagram illustrating an electronic device 1b according to a third embodiment of the present disclosure. The electronic device 1b is a device for removing a glitch in a high level direction which occurs in an input signal of a low level.

The electronic device 1b of the present embodiment includes: a glitch removal circuit 10b that removes a glitch of the input signal; a counting unit 20b that counts the number of times the burr removing circuit 10b removes burrs; and an electronic device control unit 30 that performs control based on the count value of the count unit 20 b.

The electronic device control unit 30 of the electronic device 1b of the third embodiment is the same as the electronic device control unit 30 of the electronic device 1 of the first embodiment.

The burr removal circuit 10b includes a signal input terminal 11, n-stage (n is an integer of 1 or more) original signal delay elements 12, an output signal generation unit 13b that generates an output signal, and a signal output terminal 14 that outputs the output signal.

The output signal generating unit 13b is an output generation AND circuit 132 that outputs the logical AND of the signal output from each of the n-stage original signal delay elements 12 AND the original signal.

In the glitch removal circuit 10b, a signal which may contain a glitch noise in a low level direction when the signal is at a high level is input to the original signal delay element 12.

The output signal generating section 13b outputs a low level unless the original signal is at a high level and all of the original signal delay elements 12 of the n stages latch a high level. That is, unless the high level continues n +1 times in the original signal, the output signal generating section 13b outputs the low level. Thus, the burr removal circuit 10b can remove the burr in the low level direction having a width of up to n clock cycles.

The counting unit 20b includes: an output signal delay element 21 of n stages to which an output signal is input; a determination signal generating section 22b that generates a determination signal indicating whether or not the burr removing circuit 10 has removed the burr; and an increment unit 23 for counting the number of times the burr is removed based on the determination signal generation unit 22 b.

The determination signal generation unit 22b includes: a delayed signal inverter 221 that inverts a signal output from the last stage of the original signal delay element 12; and a decision NOR circuit 223 to which the output of the delayed signal inverter 221, the present output signal, and the signals output from all the output signal delay elements 21 are input and which outputs their logical negations.

The determination signal generation unit 22b outputs the following determination signals: the determination signal is at a high level indicating that the glitch is removed only when the current output signal and the output signal of the past n times are at a low level and the original signal of the past n times is at a high level, and the determination signal is at a low level in other cases.

According to the electronic device 1b of the third embodiment described above, the following effects are obtained in addition to the effects of the first embodiment described above.

In the electronic device 1b, when the current output signal is equal to the signals output from all the output signal delay elements 21 and the current output signal is different from the signal output from the last stage of the original signal delay element 12, the determination signal generating unit 22b generates a determination signal having a value indicating that the glitch is removed. Thus, the number of times the burr is removed can be accurately counted.

In the electronic device 1b, the original signal delay elements 12 are inputted with signals that may contain a glitch noise in the high level direction when the level is low, and the output signal generating unit 13b outputs the logical and of the signals outputted from the original signal delay elements 12 and the original signals. Thus, the output signal generating unit 13b outputs a low level as the output signal except for the case where the outputs of all the original signal delay elements of the n-stage original signal delay elements 12 and the original signal are not at a high level. Therefore, the output signal generating unit 13b can appropriately remove, as the glitch noise, a high-level signal which does not continue for n +1 cycles or more and is included in the original signal.

[ fourth embodiment ]

Fig. 5 is a circuit diagram illustrating an electronic device 1c according to a fourth embodiment of the present disclosure. The electronic device 1c is a device for removing a high-level-direction burr appearing in a low-level input signal and removing a low-level-direction burr appearing in a high-level input signal.

The electronic device 1c includes: a glitch removal circuit 10c that removes a glitch of the input signal; a counting unit 20c that counts the number of times the burr removing circuit 10c has removed the burr; and an electronic device control unit 30 that performs control based on the count value of the count unit 20 c.

The electronic device control unit 30 of the electronic device 1c of the fourth embodiment is the same as the electronic device control unit 30 of the electronic device 1 of the first embodiment.

The burr removal circuit 10c includes a signal input terminal 11, n-stage (n is an integer of 1 or more) original signal delay elements 12, an output signal generation unit 13c that generates an output signal, and a signal output terminal 14 that outputs the output signal.

The output signal generation unit 13c includes: an output generation OR circuit 131 that outputs a logical OR of the output signals of all the original signal delay elements 12 and the original signals; an output generation AND circuit 132 that outputs the logical AND of the output signals of all the original signal delay elements 12 AND the original signals; a first switch 133 capable of invalidating the logical OR of the output generation OR circuit 131; a second switch 134 capable of invalidating the logical AND of the output generation AND circuit 132; an XOR circuit 135 that outputs a logical XOR of the output of the first switch 133 and the output of the second switch 134; an output latch delay element 136 that latches the output signal output from the output signal generation unit 13 c; an output selector 137 that selects the original signal or outputs the output of the latch delay element 136 as the output signal of the output signal generating unit 13 c; a first selection terminal 138 to which a selection signal for selecting whether or not to remove a low-level direction burr included in a high-level original signal is input; and a second selection terminal 139 to which a selection signal for selecting whether or not to remove a glitch in a high level direction included in the low-level original signal is input.

The first switch 133 is a selector as follows: the output of the OR circuit 131 and the original signal are input and output, the selection signal is input to the first selection terminal 138, and when the selection signal is at a high level, the output of the OR circuit 131 is output to the XOR circuit 135, and when the selection signal is at a low level, the output of the OR circuit 131 is invalidated and the original signal is output to the XOR circuit 135. The second switch 134 is a selector as follows: the original signal AND the output of the output generation AND circuit 132 are input, the selection signal is input to the second selection terminal 139, the output of the output generation AND circuit 132 is output to the XOR circuit 135 when the selection signal is at a high level, AND the output of the output generation AND circuit 132 is invalidated AND the original signal is output to the XOR circuit 135 when the selection signal is at a low level. The output of the XOR circuit 135 is output as a selection signal to the output selector 137. The output latch delay element 136 is, for example, a D flip-flop, for storing the output signal 1 clock cycle ago. When the output of the XOR circuit 135 is at a high level, the output selector 137 outputs, as an output signal, a signal that outputs the output of the latch delay element 136, that is, the same value as the previous time, and when the output of the XOR circuit 135 is at a low level, the output selector 137 outputs, as an output signal, the original signal.

The operation of the output signal generating unit 13c having such a configuration will be described in cases where a high-level signal is input to each of the first selection terminal 138 and the second selection terminal 139.

(in the case where the original signal is a high-level signal that may contain a glitch)

The output generation OR circuit 131 outputs a high level unless the original signal is a low level and all of the original signal delay elements 12 of the n stages latch a low level. Thus, unless the low level continues n +1 times in the original signal, the output generation OR circuit 131 outputs the high level. At this time, the output generation AND circuit 132 outputs the high level only when the original signal is at the high level AND all of the n-stage original signal delay elements 12 latch the high level. On the other hand, when a part of the n-stage original signal delay elements 12 latches a low level, the output generation AND circuit 132 outputs a low level.

The XOR circuit 135 outputs a low level to the output selector 137 in a case where both the output generation AND circuit 132 AND the output generation OR circuit 131 output a high level. On the other hand, when the output generation AND circuit 132 outputs the low level, the XOR circuit 135 outputs the high level to the output selector 137.

When the low level is output from the XOR circuit 135, the output selector 137 outputs the high level, which is the original signal, to the signal output terminal 14. On the other hand, when the XOR circuit 135 outputs the high level, the output of the output selector 137 before 1 clock latched by the output latch delay element 136, that is, the high level is output. This makes it possible to remove the low-level direction glitch included in the high-level signal.

(in the case where the original signal is a low-level signal that may contain a glitch)

The output generation OR circuit 131 outputs a low level unless the original signal is at a high level OR any one of the original signal delay elements 12 of the n stages latches a high level. At this time, unless the original signal is at low level AND all the original signal delay elements 12 of the n stages latch at low level, the output generation AND circuit 132 outputs high level. Thus, unless the high level continues n +1 times in the original signal, the output generation AND circuit 132 outputs the low level.

In the case where both the output generation AND circuit 132 AND the output generation OR circuit 131 output a low level, the XOR circuit 135 outputs a low level to the output selector 137. On the other hand, when the output generation OR circuit 131 outputs a high level, the XOR circuit 135 outputs a high level to the output selector 137.

When the low level is output from the XOR circuit 135, the output selector 137 outputs the high level, which is the original signal, to the signal output terminal 14. On the other hand, when the XOR circuit 135 outputs the high level, the output of the output selector 137 before 1 clock latched by the output latch delay element 136, that is, the high level is output. This makes it possible to remove the high-level direction glitch included in the low-level signal.

As described above, the burr removal circuit 10c can remove both the burrs in the high level direction and the burrs in the low level direction.

Next, an operation when a low-level signal is input to at least one of the first selection terminal 138 and the second selection terminal 139 will be described.

When the selection signal input from the first selection terminal 138 to the first switch 133 is at a low level AND the selection signal input from the second selection terminal 139 to the second switch 134 is at a high level, the logical OR of the output generation OR circuit 131 is invalid AND the logical AND of the output generation AND circuit 132 is valid. In this case, since the burr removal circuit 10c of fig. 5 is equivalent to the burr removal circuit 10a of fig. 2, the burr in the low-level direction included in the high-level original signal is removed in the same manner as the burr removal circuit 10a of fig. 2.

When the selection signal input from the first selection terminal 138 to the first switch 133 is at a high level AND the selection signal input from the second selection terminal 139 to the second switch 134 is at a low level, the logical OR of the output generation OR circuit 131 is enabled AND the logical AND of the output generation AND circuit 132 is disabled. In this case, since the burr removal circuit 10c in fig. 5 is equivalent to the burr removal circuit 10b in fig. 4, the burr in the high-level direction included in the low-level original signal is removed in the same manner as the burr removal circuit 10b in fig. 4.

When the selection signal input from the first selection terminal 138 to the first switch 133 is at a low level AND the selection signal input from the second selection terminal 139 to the second switch 134 is at a low level, neither logical nor of the output generation OR circuit 131 AND the output generation AND circuit 132 is valid. In this case, the glitch removal circuit 10c in fig. 5 always outputs the original signal as an output signal.

As described above, the electronic device 1c in fig. 5 can select 4 operation modes by setting the first switch 133 and the second switch 134 for 1 glitch removal circuit 10 a.

The counting unit 20c includes: an output signal delay element 21 of n stages to which an output signal is input; a determination signal generating section 22c that generates a determination signal indicating whether or not the burr removing circuit 10 has removed the burr; and an increment unit 23 for counting the number of times the burr is removed based on the determination signal generation unit 22 c. Further, the output latch delay element 136 may also serve as the first stage of the output signal delay element 21.

The determination signal generation unit 22c includes: a determination AND circuit 224 to which the current output signal AND the signals output from all the output signal delay elements 21 are input AND which outputs a logical AND; a NOR circuit 225 to which the current output signal and the signals output from all the output signal delay elements 21 are input, and which outputs a logical NOR; AND a selector 226 for selecting AND outputting the output of the determination AND circuit 224 or the output of the NOR circuit 225. The output of the original signal delay element 12 at the last stage of the glitch removal circuit 10c is input to the selector 226 as a selection signal, AND when the selection signal is at a high level, the output of the NOR circuit is output to the increment unit 23, AND when the selection signal is at a low level, the output of the AND circuit is output to the increment unit 23.

Thus, when the current output signal is equal to the signals output from all the output signal delay elements 21 and the current output signal is different from the signal output from the last stage of the original signal delay element 12, the determination signal generating unit 22c generates a determination signal having a value indicating that the glitch is removed.

According to the electronic device 1c of the fourth embodiment described above, the following effects are obtained in addition to the effects of the first embodiment described above.

In the electronic device 1c, when the current output signal is equal to the signals output from all the output signal delay elements 21 and the current output signal is different from the signal output from the last stage of the original signal delay element 12, the determination signal generating unit 22c generates a determination signal having a value indicating that the glitch is removed. Thus, the number of times the burr is removed can be accurately counted.

In the electronic device 1c, the original signal delay elements 12 receive signals that may include low-level direction glitch noise at a high level and may include high-level direction glitch noise at a low level, and the output signal generating unit 13 generates an output signal based on an exclusive or of a logical or and of the signal output from each of the original signal delay elements 12 and the original signal. Thus, even if the original signal is a high-level signal, the glitch can be removed. Further, by comparing the signal output to the signal output terminal 14 with the output of the last stage of the original signal delay element 12, the number of times of removing the glitch can be counted. Therefore, the electronic apparatus 1c has relatively high versatility.

In the electronic device 1c, the output signal generating unit 13c further includes a first switch 133 for enabling the logical or and a second switch 134 for enabling the logical and. This enables selective removal of the glitch of the original signal. Therefore, the electronic apparatus 1c has relatively high versatility.

[ fifth embodiment ]

Fig. 6 is a circuit diagram illustrating an electronic device 1d according to a fifth embodiment of the present disclosure. The electronic device 1d according to the present embodiment is a device for removing a high-level directional burr appearing in a low-level input signal and removing a low-level directional burr appearing in a high-level input signal.

The electronic device 1d includes: a glitch removal circuit 10d for removing a glitch of the input signal; a counting unit 20d that counts the number of times the burr removing circuit 10d has removed the burr; and an electronic device control unit 30 that performs control of the count value by the count unit 20 d.

The electronic device control unit 30 of the electronic device 1d according to the fifth embodiment is the same as the electronic device control unit 30 of the electronic device 1 according to the first embodiment.

The burr removal circuit 10d includes a signal input terminal 11, n-stage (n is an integer of 1 or more) original signal delay elements 12, an output signal generation unit 13d that generates an output signal, and a signal output terminal 14 that outputs the output signal.

The output signal generation unit 13d includes: an output generation OR circuit 131 that outputs a logical OR of the output signals of all the original signal delay elements 12 and the original signals; an output generation AND circuit 132 that outputs the logical AND of the output signals of all the original signal delay elements 12 AND the original signals; a first selection terminal 138 to which a selection signal for selecting whether or not to remove a low-level direction burr included in a high-level original signal is input; a second selection terminal 139 to which a selection signal for selecting whether or not to remove a glitch in a high level direction included in a low level original signal is input; a first selection AND circuit 140 that outputs a selection signal input from the first selection terminal 138 AND outputs a logical AND that generates an output of the OR circuit 131; a first selection OR circuit 141 that outputs a logical OR of the output of the first selection AND circuit 140 AND the original signal; a selection signal inverter 142 that inverts the selection signal input from the first selection terminal 138; a second selection OR circuit 143 that outputs a logical OR of the output of the selection signal inverter 142 AND the output of the generation AND circuit 132; a second selection AND circuit 144 that outputs a logical AND of the output of the second selection OR circuit 143 AND the original signal; an output latch delay element 136 that latches the output signal; an output OR circuit 145 that outputs a logical OR of the output of the second selection OR circuit 143 and the output of the output latch delay element 136; AND an output AND circuit 146 that outputs a logical AND of the output of the first selection OR circuit 141 AND the output of the output OR circuit 145.

The first selection AND circuit 140 outputs the output of the output generation OR circuit 131 as it is when the selection signal input from the first selection terminal 138 is at a high level, AND the first selection AND circuit 140 outputs a signal at a low level regardless of the output generation OR circuit 131 when the selection signal input from the first selection terminal 138 is at a low level. When the original signal is at a high level, the output of the output OR circuit 131 is necessarily at a high level. Therefore, the output of the first OR circuit 141 is the original signal (the output when the output is made to generate the logical OR of the OR circuit 131 is disabled) OR the output of the output generation OR circuit 131 (the output when the output is made to generate the logical OR of the OR circuit 131 is enabled).

The second selection OR circuit 143 outputs the output of the output generation AND circuit 132 as it is when the selection signal input from the second selection terminal 139 is at a high level, AND the second selection OR circuit 143 outputs a high-level signal regardless of the output generation AND circuit 132 when the selection signal input from the second selection terminal 139 is at a low level. When the original signal is at a low level, the output of the output generation AND circuit 132 is necessarily at a low level. Therefore, the output of the second selection AND circuit 144 is the original signal (the output when the logical AND of the output generation AND circuit 132 is disabled) or the output of the output generation AND circuit 132 (the output when the logical AND of the output generation AND circuit 132 is enabled).

The output latch delay element 136 stores the output signal 1 clock cycle ago. The output of the output OR circuit 145 is at a high level in the case where the previous output signal is at a high level AND in the case where the output of the second selection AND circuit 144 is at a high level. When both the output of the output OR circuit 145 AND the output of the first selection OR circuit 141 are at the high level, the output of the output AND circuit 146 is at the high level. When the output of the first selection OR circuit 141 (the output of the output generation OR circuit 131) AND the output of the second selection AND circuit 144 (the output of the output generation AND circuit 132) are directly input to the output AND circuit 146, a signal in which a glitch in the low level direction is included in a high level signal is output. However, since the output signal generating section 13 includes the output latch delay element 136 AND the output OR circuit 145, once the output signal is at the high level, even if the output of the second selection AND circuit 144 is at the low level, the output OR circuit 145 outputs a signal at the high level next time the output of the first selection OR circuit 141 is at the high level. Thus, the output of the output AND circuit 146 is a signal obtained by removing the low-level direction glitch AND the high-level direction glitch from the original signal.

The counting unit 20d includes: an output signal delay element 21 of n stages to which an output signal is input; a determination signal generating unit 22d that generates a determination signal indicating whether or not the burr removing circuit 10 has removed the burr; and an increment unit 23 for counting the number of times the burr is removed based on the determination signal generation unit 22 d.

The determination signal generation unit 22d includes: a delayed signal inverter 221 that inverts a signal output from the last stage of the original signal delay element 12; a determination AND circuit 222 to which the output of the delayed signal inverter 221, the current output signal, AND the signals output from all the output signal delay elements 21 are input, AND which outputs the logical AND thereof; a determination NOR circuit 223 to which the output of the delayed signal inverter 221, the current output signal, and the signals output from all the output signal delay elements 21 are input, and which outputs their logical negations; AND a determination OR circuit 227 that outputs a logical OR of the output of the determination AND circuit 222 AND the output of the determination NOR circuit 223.

When the burr removal circuit 10d removes the burr in the low-level direction in the high-level original signal, it determines that the output of the AND circuit 222 is at the high level. When the burr removal circuit 10d removes burrs in the high direction in the low-level original signal, it is determined that the output of the NOR circuit 223 is at the high level. Therefore, when the burr removal circuit 10d removes burrs in either direction, it is determined that the output of the NOR circuit 223 is at a high level.

The electronic device 1d according to the fifth embodiment described above also achieves the same effects as those of the electronic device 1c according to the fourth embodiment described above.

[ sixth embodiment ]

Fig. 7 is a circuit diagram showing an electronic device 1e according to a sixth embodiment of the present disclosure. The electronic device 1e of the present embodiment is a device for removing a high-level directional burr appearing in a low-level input signal and removing a low-level directional burr appearing in a high-level input signal.

The electronic device 1e includes: a glitch removal circuit 10c that removes a glitch of the input signal; a counting unit 20e that counts the number of times the burr removing circuit 10c has removed the burr; and an electronic device control unit 30 that performs control of the count value by the count unit 20 e.

The burr removal circuit 10c of the electronic device 1e of the sixth embodiment is the same as the burr removal circuit 10c of the electronic device 1c of the fourth embodiment. The electronic device control unit 30 of the electronic device 1e according to the sixth embodiment is the same as the electronic device control unit 30 of the electronic device 1 according to the first embodiment.

The counting unit 20e includes: an output signal delay element 21 of n stages to which an output signal is input; a determination signal generating section 22e that generates a determination signal indicating whether or not the burr removing circuit 10 has removed the burr; and an incrementing unit 23e for counting the number of times the burr is removed based on the determination signal generating unit 22 e.

The determination signal generation unit 22e includes: a delayed signal inverter 221 that inverts a signal output from the last stage of the original signal delay element 12; a determination AND circuit 222 to which the output of the delayed signal inverter 221, the current output signal, AND the signals output from all the output signal delay elements 21 are input, AND which outputs the logical AND thereof; and a decision NOR circuit 223 to which the output of the delayed signal inverter 221, the present output signal, and the signals output from all the output signal delay elements 21 are input, and which outputs their logical negations. The determination signal generation unit 22e outputs the output of the determination AND circuit 222 to the increment unit 23e as a first determination signal, AND outputs the output of the determination NOR circuit 223 to the increment unit 23e as a second determination signal.

The increasing section 23e has: a first incrementer 232 that increments the number of times of removing the glitch every time the first determination signal output from the AND circuit 222 is determined to be high level; and a second incrementer 233 that increments the number of times the glitch is removed every time the second determination signal output from the NOR circuit 223 is determined to be high level by the second incrementer 233. That is, the increment unit 23e counts the number of times the burr removal circuit 10c has removed the burr in the low-level direction in the high-level original signal by the first incrementer 232, and counts the number of times the burr removal circuit 10c has removed the burr in the high-level direction in the low-level original signal by the second incrementer 233.

In the electronic apparatus 1e according to the sixth embodiment described above, the number of times the burr in the low level direction is removed and the number of times the burr in the high level direction is removed are counted by the increasing section 23e, and therefore, the occurrence of the burr can be grasped in more detail.

[ seventh embodiment ]

Fig. 8 is a circuit diagram illustrating an electronic device 1f according to a seventh embodiment of the present disclosure. The electronic device 1f of the present embodiment is a device for removing a high-level directional burr appearing in a low-level input signal and removing a low-level directional burr appearing in a high-level input signal.

The electronic device 1f includes: a glitch removal circuit 10d for removing a glitch of the input signal; a counting unit 20e that counts the number of times the burr removing circuit 10d has removed the burr; and an electronic device control unit 30 that performs control of the count value by the count unit 20 e.

The burr removal circuit 10d in the electronic device 1f of the present embodiment is the same as the burr removal circuit 10d in the electronic device 1d of the fifth embodiment. The counting unit 20e in the electronic device 1f according to the present embodiment is the same as the counting unit 20e in the electronic device 1e according to the sixth embodiment.

In the electronic device 1f according to the seventh embodiment, the number of times the burr in the low level direction is removed and the number of times the burr in the high level direction is removed are counted by the increasing section 23e, and therefore, the occurrence of the burr can be grasped in more detail.

[ initialization Circuit ]

Fig. 9 is a circuit diagram illustrating an initialization circuit 80 that can be added to the electronic devices 1a to 1f of the first to seventh embodiments of the present disclosure. An electronic device in which the initialization circuit 80 is added to the electronic devices 1a to 1f of the first to seventh embodiments is another embodiment of the present disclosure.

The initialization circuit 80 includes: a reset terminal 81 to which a reset signal is input, the reset signal being a negative logic signal in a normal state, that is, being at a low level only when a count of the number of times a glitch is removed from a high level is initialized; an original signal inverter 82 that inverts the original signal; a first initialized OR circuit 83 that outputs a logical OR of the output of the original signal inverter 82 and the reset signal input from the reset terminal 81; and a second initialized OR circuit 84 that outputs a logical OR of the original signal and the reset signal input from the reset terminal 81.

The reset signal input to the reset terminal 81 is input to the clear terminal of the incrementer 231 in addition to the first and second initialized OR circuits 83 and 84. The output of the first initializing OR circuit 83 is input to a preset terminal for setting the holding value of each output signal delay element 21 to a high level. On the other hand, the output of the second initialized OR circuit 84 is input to a clear terminal for setting the holding value of each output signal delay element 21 to a low level. All of the clear terminals and the preset terminals are set to negative logic. Therefore, when the reset signal input to the reset terminal 81 is at a low level, the incrementer 231 resets the count to zero (initial setting). The hold value of the output signal delay element 21 is set to a high level when the output of the first initialized OR circuit 83 is a low level, and the hold value of the output signal delay element 21 is set to a low level when the output of the second initialized OR circuit 84 is a low level.

The output of the first initializing OR circuit 83 is at a low level only when the original signal is at a high level and the reset signal input from the reset terminal 81 is at a low level. The output of the second initializing OR circuit 84 is low level only when the original signal is low level and the reset signal input from the reset terminal 81 is low level. Therefore, when the original signal is at a high level when the reset signal is at a low level, the holding value of each output signal delay element 21 is initially set to a high level. When the original signal is at the low level when the reset signal is at the low level, the holding value of each output signal delay element 21 is initially set to the low level.

[ eighth embodiment ]

Fig. 10 is a circuit diagram illustrating an electronic device 1g according to an eighth embodiment of the present disclosure. The electronic device 1g of the present embodiment is a device in which the initialization circuit 80 of fig. 9 is added to the electronic device 1e of the sixth embodiment of the present disclosure.

In the electronic apparatus 1g, the reset signal input to the reset terminal 81 is input to the first and second initialized OR circuits 83 and 84, and is inversely input to the clear terminals of the first and second incrementers 232 and 233. The output of the first initializing OR circuit 83 is inverted and input to the preset terminal of each output signal delay element 21, the preset terminal of each original signal delay element 12, and the preset terminal of the output latch delay element 136. The output of the second initialized OR circuit 84 is inverted and input to the clear terminal of each output signal delay element 21, the clear terminal of each original signal delay element 12, and the clear terminal of the output latch delay element 136.

According to the electronic device 1g of the eighth embodiment described above, the following effects are obtained in addition to the effects of the first and sixth embodiments described above.

The electronic device 1g includes the initialization circuit 80, and when the reset signal is input, the initialization circuit 80 initializes the original signal delay element 12, the output signal delay element 21, and the increment unit 23e (the incrementers 231 and 232). Thereby, the electronic device 1g can initialize the burr removal circuit 10c and the counter 20 e. Therefore, the occurrence of burrs can be grasped in more detail.

[ ninth embodiment ]

Fig. 11 is a circuit diagram illustrating an electronic device 1h according to a ninth embodiment of the present disclosure. The electronic device 1h according to the present embodiment is an electronic device 1f according to a seventh embodiment of the present disclosure to which an initialization circuit 80 shown in fig. 9 is added.

In the electronic apparatus 1h, the reset signal input to the reset terminal 81 is input to the first and second initialized OR circuits 83 and 84, and is inversely input to the clear terminals of the first and second incrementers 232 and 233. The output of the first initializing OR circuit 83 is inverted and input to the preset terminal of each output signal delay element 21, the preset terminal of each original signal delay element 12, and the preset terminal of the output latch delay element 136. The output of the second initialized OR circuit 84 is inverted and input to the clear terminal of each output signal delay element 21, the clear terminal of each original signal delay element 12, and the clear terminal of the output latch delay element 136.

According to the electronic apparatus 1h of the ninth embodiment described above, the electronic apparatus 1h can also initialize the burr removal circuit 10d and the counter 20 e. Therefore, the occurrence of burrs can be grasped in more detail.

[ tenth embodiment ]

Fig. 12 is a circuit diagram showing an electronic device 1i according to a tenth embodiment of the present disclosure. The electronic device 1i of the present embodiment is a device for removing a low-level direction glitch occurring in a high-level input signal.

The electronic device 1i of the present embodiment includes: a glitch removal circuit 10a that removes a glitch of an input signal; a counting unit 20i that counts the number of times the burr removing circuit 10a has removed the burr; and an electronic device control unit 30 that performs control of the count value by the count unit 20 i.

The burr removal circuit 10a in the electronic apparatus 1i of the present embodiment is the same as the burr removal circuit 10a in the electronic apparatus 1a of the second embodiment. The electronic device control unit 30 of the electronic device 1i according to the present embodiment is the same as the electronic device control unit 30 of the electronic device 1 according to the first embodiment.

The counting unit 20i includes: an output signal delay element 21 of n stages to which an output signal is input; a determination signal generating unit 22a that generates a determination signal indicating whether or not the burr removing circuit 10 has removed the burr; and an increment unit 23i for counting the number of times the burr is removed based on the determination signal generation unit 22. The electronic device 1i of the present embodiment differs from the electronic device 1a of the second embodiment only in the configuration of the increasing section 23 i.

The increasing section 23i includes: a determination signal delay element 234 that latches the determination signal output from the determination signal generation unit 22 a; a determination signal inverting element 235 that inverts the output of the determination signal delaying element 234; an increment AND circuit 236 that outputs the logical AND of the determination signal output from the determination signal generation unit 22a AND the output from the determination signal inverting element 235; AND an incrementer 231, the incrementer 231 increments the count each time the output of the increment AND circuit 236 is at a high level.

The increment unit 23i increments the incrementer 231 only when the current determination signal is at the high level and the previous determination signal is at the low level. Therefore, when the burr removal circuit 10a removes burrs continuously for a plurality of clock cycles, the increment unit 23i increments the incrementer only 1 time. That is, the counter 20i counts the edges (japanese: アサートエッジ) for determining the removal of the burrs by the burr removal circuit 10 a.

According to the electronic device 1i of the tenth embodiment described above, the following effects are obtained in addition to the effects of the first embodiment described above.

When the time width of the burr removed by the burr removal circuit 10a is two clock cycles or more, the electronic device 1i counts the number of times the burr is removed as 1 time by the counting unit 20 i. This makes it possible to accurately grasp the occurrence of burrs.

[ eleventh embodiment ]

Fig. 13 is a circuit diagram illustrating an electronic device 1j according to an eleventh embodiment of the present disclosure. The electronic device 1j according to the present embodiment is a device for removing a glitch in a high level direction which appears in a low level input signal.

The electronic device 1j of the present embodiment includes: a glitch removal circuit 10b that removes a glitch of the input signal; a counting unit 20j that counts the number of times the burr removing circuit 10b has removed the burr; and an electronic device control unit 30 that performs control based on the count value of the count unit 20 j.

The counting unit 20j includes: an output signal delay element 21 of n stages to which an output signal is input; a determination signal generating unit 22a that generates a determination signal indicating whether or not the burr removing circuit 10 has removed the burr; and an increment unit 23i for counting the number of times the burr is removed based on the determination signal generation unit 22. The electronic device 1j according to the present embodiment is obtained by replacing the increment section 23 of the electronic device 1b according to the third embodiment with the increment section 23i of the electronic device 1i according to the tenth embodiment.

According to the electronic device 1j of the eleventh embodiment, the number of edges for determining the removed high-level-direction burr is counted, and the occurrence of the high-level-direction burr can be accurately grasped.

[ initialization Circuit ]

Fig. 14 is a circuit diagram showing wirings when the initialization circuit 80 of fig. 9 is added to the electronic device 1 of the tenth embodiment or the electronic device 1j of the eleventh embodiment.

When the initialization circuit 80 is added to the electronic devices 1i and 1j having the increment units 23i, the reset signal input to the reset terminal 81 is also input to the clear terminal of the determination signal delay element 234. Therefore, when the reset signal input from the reset terminal 81 is at a low level, the determination signal delay element is initialized to a low level.

[ twelfth embodiment ]

Fig. 15 is a circuit diagram showing an electronic device 1k according to a twelfth embodiment of the present disclosure. The electronic apparatus 1k of the present embodiment is an apparatus for removing a high-level directional burr appearing in a low-level input signal and removing a low-level directional burr appearing in a high-level input signal.

The electronic device 1k includes: a glitch removal circuit 10d for removing a glitch of the input signal; a counting unit 20k that counts the number of times the burr removing circuit 10d has removed the burr; and an electronic device control unit 30 that performs control based on the count value of the count unit 20 k.

The burr removal circuit 10d of the electronic apparatus 1k of the twelfth embodiment is the same as the burr removal circuit 10d of the electronic apparatus 1d of the fifth embodiment. The electronic device control unit 30 of the electronic device 1k according to the twelfth embodiment is the same as the electronic device control unit 30 of the electronic device 1 according to the first embodiment.

The counting unit 20k includes: an output signal delay element 21 of n stages to which an output signal is input; a determination signal generating unit 22e that generates a determination signal indicating whether or not the burr removing circuit 10d has removed the burr; and an incrementing unit 23k for counting the number of times the burr is removed based on the determination signal generating unit 22 e.

The determination signal generating unit 22e of the counting unit 20k according to the present embodiment is the same as the determination signal generating unit 22e of the counting unit 20e according to the sixth embodiment.

The increasing section 23k includes: a first determination signal delay element 237 that latches the first determination signal output from the determination AND circuit 222 of the determination signal generation section 22 e; a first determination signal inverting element 238 that inverts the output of the first determination signal delay element 237; a first increment AND circuit 239 that outputs a logical AND of the first determination signal output from the determination AND circuit 222 AND the output of the first determination signal inverting element 238; a first incrementer 232 that increments the count every time the output of the first increment AND circuit 239 is high level; a second determination signal delay element 240 that latches the second determination signal output from the determination NOR circuit 223 of the determination signal generation unit 22 e; a second determination signal inverting element 241 that inverts an output of the second determination signal delaying element 240; a second increment AND circuit 242 that outputs a logical AND of the second determination signal output from the determination AND circuit 222 AND the output of the second determination signal inverting element 241; AND a second incrementer 233, the second incrementer 233 incrementing the count every time the output of the second increment AND circuit 242 is at a high level.

The first incrementer 232 counts the edges for assertion of the glitch in the low level direction removed by the glitch removal circuit 10 d. The second incrementer 233 counts the edges for assertion of the glitch in the high level direction removed by the glitch removal circuit 10 d.

In the electronic apparatus 1k according to the twelfth embodiment described above, the increasing section 23k counts the number of edges for determining the removed low-level direction burr and the number of edges for determining the removed high-level direction burr, respectively, and thus the occurrence of the burr can be grasped in more detail.

[ noise removal System ]

An embodiment of the noise canceling system according to the present disclosure will be described below with reference to fig. 16. Fig. 16 is a block diagram showing the configuration of an embodiment of the noise removal system according to the present disclosure.

The noise canceling system includes a plurality of electronic devices 1 and an information processing device 2 that communicates with 1 or more of the electronic devices 1.

The electronic device 1 in the noise canceling system of the present embodiment is the same as the electronic device 1 of the first embodiment.

The information processing device 2 includes: an information processing device communication unit 91 that receives the number of times (count value) the burr is removed by communicating with the electronic device communication unit 60 of the electronic device 1; an information processing device control unit 92 that controls the information processing device communication unit 91; and an information processing device storage unit 93 that records the count value received by the information processing device communication unit 91.

The information processing device communication unit 91 may be configured to include, for example, an ethernet communication module, a wireless communication module, and the like, similar to the electronic device communication unit 60.

The information processing device control unit 92 may be configured to have a processor (CPU) that performs an operation instructed by a program.

The information processing device storage unit 93 may have a configuration including a storage device such as a memory or a hard disk drive.

In the information processing device 2, the information processing device control unit 92 acquires the number of times of deburring performed by each electronic device 1 through the information processing device communication unit 91. The information processing device control unit 92 stores the number of the electronic device 1 in the information processing device storage unit 93 in association with the count value of the electronic device 1. The information processing device 2 may also acquire position information of the electronic device 1. The position information may be acquired by using a position information acquisition system such as a GPS, or may be obtained from the number of the electronic device 1 based on a preset arrangement of the electronic device 1.

Preferably, the count value is acquired from each electronic device 1 and recorded in the information processing device storage unit 93 periodically or when a predetermined event such as occurrence of a fatal error occurs.

The information processing device control unit 92 may analyze the number of times of burr removal acquired from the electronic device 1. In the analysis of the number of times of burr removal, the number of times of burr removal of each electronic device 1 may be used as data in time series, or position information of the electronic device 1 may be used.

The information processing device 2 may further include an analysis result notification unit such as a monitor for notifying an analysis result of the number of times of burr removal. The information processing device may transmit the analysis result of the number of times of burr removal to the electronic device 1 or another device via the information processing device communication unit 91.

According to the noise canceling system according to the embodiment of the present disclosure described above, the following effects are obtained.

The noise canceling system according to the embodiment of the present disclosure described above includes the electronic device 1 and the information processing device 2, and the information processing device 2 receives the count value from the electronic device 1 and records the received count value. Thus, it is possible to acquire the number of times that the burr noise is removed by 1 or a plurality of electronic devices 1, and comprehensively grasp the generation status of burrs.

While the preferred embodiments of the electronic device of the present disclosure have been described above, the present disclosure is not limited to the above embodiments and can be modified as appropriate.

For example, in the above-described embodiment, the original signal delay element 12 is described as a D flip-flop, but the present invention is not limited thereto. The original signal delay element 12 may also be a JK type flip-flop.