阅读说明：本技术 输出缓冲器控制电路 (Output buffer control circuit ) 是由 刘惠强 于 2020-06-02 设计创作，主要内容包括：本发明揭示了一种输出缓冲器控制电路,所述控制电路包括：运算放大器；反馈电阻R<Sub>F</Sub>；分压电阻；浮动开关,包括第一浮动开关SW1及第二浮动开关SW2,第一浮动开关SW1一端与第一分压电阻R<Sub>1</Sub>和第二分压电阻R<Sub>2</Sub>电连接,另一端与运算放大器的第二输入端电连接,第二浮动开关SW2一端与第二分压电阻R<Sub>2</Sub>和反馈电阻R<Sub>F</Sub>电连接,另一端与运算放大器的第二输入端电连接；MOS管开关,包括共栅连接的第一MOS管开关SW3和第二MOS管开关SW4,第一MOS管开关SW3和第二MOS管SW4开关分别与第一分压电阻R1电连接。本发明的输出缓冲器控制电路通过浮动开关控制电压域之间的切换,MOS管开关的漏电流不会流过电阻,大大提高了输出电压的线性度。(The invention discloses an output buffer control circuit, which comprises: an operational amplifier; feedback resistor R F (ii) a A voltage dividing resistor; a floating switch including a first floating switch SW1 and a second floating switch SW2, a first end of the first floating switch SW1 and a first voltage dividing resistor R 1 And a second voltage dividing resistor R 2 Electrically connected to the second input terminal of the operational amplifier, and a second floating switch SW2 having one end connected to the second voltage dividing resistor R 2 And a feedback resistor R F The other end of the first input end is electrically connected with the first input end of the operational amplifier; the MOS tube switch comprises a first MOS tube switch SW3 and a second MOS tube switch SW4 which are connected in a common grid mode, and the first MOS tube switch SW3 and the second MOS tube switch SW4 are electrically connected with the first voltage dividing resistor R1 respectively. The output buffer control circuit controls the switching between the voltage domains through the floating switch, the leakage current of the MOS tube switch can not flow through the resistor, and the linearity of the output voltage is greatly improved.)

1. An output buffer control circuit, the control circuit comprising:

the operational amplifier comprises a first input end, a second input end and an output end;

feedback resistor R_FElectrically connected to the output of the operational amplifier;

a voltage dividing resistor including a first voltage dividing resistorR₁And a second voltage dividing resistor R₂And a feedback resistance R_FAre arranged in series;

a floating switch including a first floating switch SW1 and a second floating switch SW2, a first end of the first floating switch SW1 and a first voltage dividing resistor R₁And a second voltage dividing resistor R₂Electrically connected to the second input terminal of the operational amplifier, and a second floating switch SW2 having one end connected to the second voltage dividing resistor R₂And a feedback resistor R_FThe other end of the first input end is electrically connected with the first input end of the operational amplifier;

the MOS tube switch comprises a first MOS tube switch SW3 and a second MOS tube switch SW4 which are connected in a common grid mode, and the first MOS tube switch SW3 and the second MOS tube switch SW4 are respectively connected with a first divider resistor R₁And (6) electrically connecting.

2. The output buffer control circuit of claim 1, wherein the first floating switch SW1 and the second floating switch SW2 are NMOS transistors, the first MOS transistor switch SW3 is an NMOS transistor, and the second MOS transistor switch SW4 is a PMOS transistor.

3. The output buffer control circuit of claim 2, wherein the control circuit is further configured to:

the drain of the first floating switch SW1 and the first voltage dividing resistor R₁And a second voltage dividing resistor R₂Electrically connected to the second input terminal of the operational amplifier, the source of the second floating switch SW2, the drain of the second floating switch SW2, and the second voltage dividing resistor R₂And a feedback resistor R_FElectrically connected to the second input terminal of the operational amplifier, the source of the second floating switch SW2 having a drain voltage V₁Source voltage is V_IMThe gate control voltage of the second floating switch SW2 is V_GBulk voltage is V_B；

The source voltage of the first MOS transistor switch SW3 is 0, and the source voltage of the second MOS transistor switch SW4 is V_RThe drains of the first and second MOS tube switches SW3 and SW4 and the first voltage dividing resistor R₁Is electrically connected with the drain electrode at a voltage of V_RIGate of the first MOS transistor switch SW3The gate of the gate and second MOS transistor switch SW4 is coupled to the control signal VSE L.

4. The output buffer control circuit of claim 3, wherein the input voltage at the first input of the operational amplifier is V_IPSatisfy 0. ltoreq. V_IP≤V_I，V_IIs a predetermined voltage threshold, and the source voltage V of the first MOS transistor switch SW3_RGreater than a predetermined voltage threshold V_I。

5. The output buffer control circuit of claim 4, wherein the control circuit comprises:

in the first state, the first floating switch SW1 is turned on, the second floating switch SW2 is turned off, and when V is greater than V_RI0 and V_IMWhen equal to 0, V₁When V is equal to 0_RI＝V_RAnd V is_IMWhen equal to 0, V₁＝-aV_RWhen V is_RI0 and V_IM＝V_IWhen, V₁＝(1+a)V_IWhen V is_RI＝V_RAnd V is_IM＝V_IWhen, V₁＝-aV_R+(1+a)V_IWherein a ═ R₂/R₁；

In the second state, the first floating switch SW1 is turned off, the second floating switch SW2 is turned on, and V is set to₁＝V_IM，0≤V₁≤V_I。

6. The output buffer control circuit of claim 5, further comprising a voltage generation unit for generating a follower V₁Or V_IMThe voltage of (c).

7. The output buffer control circuit of claim 6, wherein the voltage follower unit comprises:

a first voltage comparison unit for obtaining V₁And V_IMMiddle lower voltage min (V)₁,V_IM)；

Second voltage ratioComparison unit for obtaining V₁And V_IMMedium high voltage max (V)₁,V_IM)；

The third resistor and the first control switch are electrically connected between the first voltage comparison unit and the second voltage comparison unit in sequence;

and the first level shifter and the second control switch are electrically connected between the third resistor and the first control switch.

8. The output buffer control circuit of claim 7, wherein the voltage follower unit is in a first state, the first level shifter is short-circuited by the second control switch, and min (V) is obtained by the first voltage comparator unit₁,V_IM) As the gate control voltage V of the second floating switch SW2_GAnd V is_B＝V_G(ii) a In the second state, max (V) obtained by the first voltage comparison unit is adopted₁,V_IM) And is raised by the first level shifter as the gate control voltage V of the second floating switch SW2_GAnd V is_B＝min(V₁,V_IM) (ii) a The voltage following unit is in a second state, V_G-max(V₁,V_IM)≥bV_THWherein b is not less than 1 and V_THIs the threshold voltage of the second floating switch SW 2.

9. The output buffer control circuit of claim 8, wherein the voltage follower unit further comprises a second level shifter electrically connected to the first voltage comparator unit, the second level shifter being configured to shift min (V) obtained by the first voltage comparator unit₁,V_IM) After reducing the pressure, the product is used as V_BAnd (6) outputting.

10. The output buffer control circuit of claim 7, wherein the first voltage comparison unit comprises a first differential pair of two PMOS transistors and the second voltage comparison unit comprises a second differential pair of two NMOS transistors.

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to an output buffer control circuit.

Background

The output buffer needs to support the output of several voltage domains simultaneously, including switching between outputting positive and negative voltages, e.g., between four voltage domains + VA/+ VB/-VA/-VB, which need to be controlled by switches.

Referring to fig. 1, a control circuit in the prior art includes an amplifier and a voltage dividing resistor R₁And R₂(R₂＝aR₁) A feedback resistor R_FThe control circuit has the advantages that the switch control is convenient, a level shifter (level shifter) is not needed, but the leakage current (L eakage) of the MOS tube of the control circuit at high temperature can affect the output precision, for example, when the + VA voltage domain is selected for output, the NMOS tube SW1 ' is conducted, the other MOS tubes are closed, the leakage current of the NMOS tube SW3 ' and the PMOS tube SW4 ' can flow through a voltage-dividing resistor, when the leakage current is 1nA, the 100k ohm resistor can generate a voltage of 0.1mV, and after the voltage is amplified to be output, the influence on the linearity of the output voltage is great.

Therefore, it is desirable to provide an output buffer control circuit for solving the above problems.

Disclosure of Invention

The present invention provides an output buffer control circuit to improve the linearity of the output buffer.

In order to achieve the above object, an embodiment of the present invention provides the following technical solutions:

an output buffer control circuit, the control circuit comprising:

the operational amplifier comprises a first input end, a second input end and an output end;

feedback resistor R_FElectrically connected to the output of the operational amplifier;

a voltage dividing resistor including a first voltage dividing resistor R₁And a second voltage dividing resistor R₂And a feedback resistance R_FAre arranged in series;

a floating switch including a first floating switch SW1 and a second floating switch SW2, a first end of the first floating switch SW1 and a first voltage dividing resistor R₁And a second voltage dividing resistor R₂Electrically connected to the second input terminal of the operational amplifier, and a second floating switch SW2 having one end connected to the second voltage dividing resistor R₂And a feedback resistor R_FThe other end of the first input end is electrically connected with the first input end of the operational amplifier;

the MOS tube switch comprises a first MOS tube switch SW3 and a second MOS tube switch SW4 which are connected in a common grid mode, and the first MOS tube switch SW3 and the second MOS tube switch SW4 are respectively connected with a first divider resistor R₁And (6) electrically connecting.

In one embodiment, the first floating switch SW1 and the second floating switch SW2 are NMOS transistors, the first MOS transistor switch SW3 is an NMOS transistor, and the second MOS transistor switch SW4 is a PMOS transistor.

In one embodiment, the control circuit further comprises:

the drain of the first floating switch SW1 and the first voltage dividing resistor R₁And a second voltage dividing resistor R₂Electrically connected to the second input terminal of the operational amplifier, the source of the second floating switch SW2, the drain of the second floating switch SW2, and the second voltage dividing resistor R₂And a feedback resistor R_FElectrically connected to the second input terminal of the operational amplifier, the source of the second floating switch SW2 having a drain voltage V₁Source voltage is V_IMThe gate control voltage of the second floating switch SW2 is V_GBulk voltage is V_B；

The source voltage of the first MOS transistor switch SW3 is 0, and the source voltage of the second MOS transistor switch SW4 is V_RThe drains of the first and second MOS tube switches SW3 and SW4 and the first voltage dividing resistor R₁Is electrically connected with the drain electrode at a voltage of V_RIThe gates of the first and second MOS switches SW3 and SW4 are connected to the control signal VSE L.

In one embodiment, the input voltage of the first input terminal of the operational amplifier is V_IPSatisfy 0. ltoreq. V_IP≤V_I，V_IIs a predetermined voltage threshold, and the source voltage V of the first MOS transistor switch SW3_RGreater than a predetermined voltage threshold V_I。

In one embodiment, the control circuit includes:

in the first state, the first floating switch SW1 is turned on, the second floating switch SW2 is turned off, and when V is greater than V_RI0 and V_IMWhen equal to 0, V₁When V is equal to 0_RI＝V_RAnd V is_IMWhen equal to 0, V₁＝-aV_RWhen V is_RI0 and V_IM＝V_IWhen, V₁＝(1+a)V_IWhen V is_RI＝V_RAnd V is_IM＝V_IWhen, V₁＝-aV_R+(1+a)V_IWherein a ═ R₂/R₁；

In the second state, the first floating switch SW1 is turned off, the second floating switch SW2 is turned on, and V is set to₁＝V_IM，0≤V₁≤V_I。

In one embodiment, the control circuit further comprises a voltage generation unit for generating the following V₁Or V_IMThe voltage of (c).

In one embodiment, the voltage follower unit includes:

a first voltage comparison unit for obtaining V₁And V_IMMiddle lower voltage min (V)₁,V_IM)；

A second voltage comparison unit for obtaining V₁And V_IMMedium high voltage max (V)₁,V_IM)；

The third resistor and the first control switch are electrically connected between the first voltage comparison unit and the second voltage comparison unit in sequence;

and the first level shifter and the second control switch are electrically connected between the third resistor and the first control switch.

In one embodiment, when the voltage follower unit is in the first state, the first level shifter is short-circuited by the second control switch, and min (V) obtained by the first voltage comparator unit is used₁,V_IM) As the gate control voltage V of the second floating switch SW2_GAnd V is_B＝V_G(ii) a In the second state, max (V) obtained by the first voltage comparison unit is adopted₁,V_IM) And is raised by the first level shifter as the gate control voltage V of the second floating switch SW2_GAnd V is_B＝min(V₁,V_IM) (ii) a The voltage following unit is in a second state, V_G-max(V₁,V_IM)≥bV_THWherein b is not less than 1 and V_THIs the threshold voltage of the second floating switch SW 2.

In one embodiment, the voltage follower unit further comprises a second level shifter electrically connected to the first voltage comparator unit, the second level shifter is used for comparing min (V) obtained by the first voltage comparator unit₁,V_IM) After reducing the pressure, the product is used as V_BAnd (6) outputting.

In one embodiment, the first voltage comparison unit includes a first differential pair composed of two PMOS transistors, and the second voltage comparison unit includes a second differential pair composed of two NMOS transistors.

Compared with the prior art, the invention has the following advantages:

the output buffer control circuit controls the switching between the voltage domains through the floating switch, the leakage current of the MOS tube switch can not flow through the resistor, and the linearity of the output voltage is greatly improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a diagram of an output buffer control circuit in the prior art;

FIG. 2 is a diagram illustrating an output buffer control circuit according to an embodiment of the present invention;

FIGS. 3a and 3b are equivalent circuit diagrams of an output buffer control circuit in a first state and a second state, respectively, according to an embodiment of the present invention;

FIG. 4 is a block diagram of a voltage follower unit in accordance with an embodiment of the present invention;

fig. 5 is a circuit diagram of an implementation of a voltage follower unit according to an embodiment of the invention.

Detailed Description

The present invention will be described in detail below with reference to embodiments shown in the drawings. The embodiments are not intended to limit the present invention, and structural, methodological, or functional changes made by those skilled in the art according to the embodiments are included in the scope of the present invention.

Referring to fig. 2, an output buffer control circuit according to an embodiment of the present invention includes:

an operational amplifier including a first input terminal (the homodromous input terminal +), a second input terminal (the inverting input terminal-) and an output terminal;

feedback resistor R_FElectrically connected to the output of the operational amplifier;

a voltage dividing resistor including a first voltage dividing resistor R₁And a second voltage dividing resistor R₂And a feedback resistance R_FAre arranged in series;

a floating switch including a first floating switch SW1 and a second floating switch SW2, a first end of the first floating switch SW1 and a first voltage dividing resistor R₁And a second voltage dividing resistor R₂Electrically connected to the second input terminal of the operational amplifier, and a second floating switch SW2 having one end connected to the second voltage dividing resistor R₂And a feedback resistor R_FThe other end of the first input end is electrically connected with the first input end of the operational amplifier;

the MOS tube switch comprises a first MOS tube switch SW3 and a second MOS tube switch SW4 which are connected in a common grid mode, and the first MOS tube switch SW3 and the second MOS tube switch SW4 are respectively connected with a first divider resistor R₁And (6) electrically connecting.

Specifically, the drain of the first floating switch SW1 and the first voltage dividing resistor R₁And a second voltage dividing resistor R₂Electrically connected to the second input terminal of the operational amplifier, the source of the second floating switch SW2, the drain of the second floating switch SW2, and the second voltage dividing resistor R₂And a feedback resistor R_FElectrically connected to the second input terminal of the operational amplifier, the source of the second floating switch SW2 having a drain voltage V₁Source voltage is V_IMThe gate control voltage of the second floating switch SW2 is V_GBulk voltage is V_B；

The source voltage of the first MOS transistor switch SW3 is 0, and the source voltage of the second MOS transistor switch SW4 is V_RFirst MOS transistor switch SThe drain of W3, the drain of the second MOS transistor switch SW4 and the first divider resistor R₁Is electrically connected with the drain electrode at a voltage of V_RIThe gates of the first and second MOS switches SW3 and SW4 are connected to the control signal VSE L.

The input voltage of the first input terminal of the operational amplifier is V_IPSatisfy 0. ltoreq. V_IP≤V_I，V_IIs a predetermined voltage threshold, and the source voltage V of the first MOS transistor switch SW3_RGreater than a predetermined voltage threshold V_I。

In this embodiment, the first floating switch SW1 and the second floating switch SW2 are NMOS transistors, the first MOS transistor switch SW3 is an NMOS transistor, and the second MOS transistor switch SW4 is a PMOS transistor. Wherein, SW1, SW3 and SW4 can be controlled by low-voltage logic, and the control circuit comprises the following two states according to the control condition of SW 1:

in the first state, referring to FIG. 3a, the first floating switch SW1 is turned on and the second floating switch SW2 is turned off when V is greater than V_RI0 and V_IMWhen equal to 0, V₁When V is equal to 0_RI＝V_RAnd V is_IMWhen equal to 0, V₁＝-aV_RWhen V is_RI0 and V_IM＝V_IWhen, V₁＝(1+a)V_IWhen V is_RI＝V_RAnd V is_IM＝V_IWhen, V₁＝-aV_R+(1+a)V_IWherein a ═ R₂/R₁；

In the second state, referring to FIG. 3b, the first floating switch SW1 is closed, the second floating switch SW2 is turned on, and V is₁＝V_IM，0≤V₁≤V_I。

When the first floating switch SW1 is turned on in the first state, one end (V) of the switch of the second floating switch SW2 is turned on₁End) negative pressure will occur, which is described below:

when the second MOS transistor switch SW4(PMOS transistor) is selected to be turned on by VSE L, i.e., V is set to 1_RI＝V_RAt the same time, SW1 is turned on and SW2 is turned off, V_IP0V, when V₁＝-V_RIf the gate voltage V of SW2_GAt 0V SW2 has not been fully closed, a ratio-V is required_RThe still low voltage controls the gate of SW2 to turn SW2 off. In addition, the substrate of SW2 also needs to be switched to a relatively negative voltage between the source and drain, where V is_IM>V₁。

When V is_RIWhen equal to 0V, V₁Can be up to 2 x V_IAt this time V_IM<V₁。

In both cases V_RI、V₁、V_IMThe relationship of (A) is shown in the following table:

VRI	V1(VIM＝0)	V1(VIM＝VI)
			0V	0	(1+a)VI
VR	-aVR	-aVR+(1+a)VI

therefore, under different circumstances, SW2 needs to generate a voltage control gate that needs to be switched lower than the source and drain to turn off SW 2.

When SW1 is turned off and SW2 is turned on in the first state, V₁＝V_IMI.e. V₁Need to be in the range of 0 to V_IAnd (4) change. At this time, the gate of SW2 needs to have a ratio V₁/V_IMEnd high by at least 1V_THAbove, to ensure a sufficiently small conductanceThrough impedance, preferably at 2V_THThe above.

In the embodiment, VSE L is adopted to control the output of a positive voltage domain or a negative voltage domain, and SW1 and SW2 switches are used for controlling the switching between the voltage domains.

According to the above description, to control the gate voltage V of SW2_GAnd generating a corresponding Bulk voltage V_BIt is necessary to generate a following V according to different application conditions₁Or V_IMThe voltage of (c).

Referring to fig. 4, the voltage follower unit in the present embodiment includes:

a first voltage comparison unit (smaller) for obtaining V₁And V_IMMiddle lower voltage min (V)₁,V_IM)；

A second voltage comparison unit (lager) for obtaining V₁And V_IMMedium high voltage max (V)₁,V_IM)；

The third resistor R3 and the first control switch are electrically connected between the first voltage comparison unit (small) and the second voltage comparison unit (large) in sequence;

and a first level shifter and a second control switch electrically connected between the third resistor R3 and the first control switch.

The voltage following unit is in the first state, the first level shifter is short-circuited by the second control switch, and min (V) obtained by the first voltage comparing unit₁,V_IM) As the gate control voltage V of the second floating switch SW2_GAnd V is_B＝V_G；

The voltage following unit adopts max (V) acquired by the first voltage comparison unit in the second state₁,V_IM) And is raised by the first level shifter as the gate control voltage V of the second floating switch SW2_GAnd V is_B＝min(V₁,V_IM). At this time, V_G-max(V₁,V_IM)≥bV_THWherein b is not less than 1 and V_THIs the threshold voltage of the second floating switch SW 2.

Specifically, when VSW is high, SW2 needs to be turned off, and V is selected by the first voltage comparing unit₁/V_IMThe lower one is used as the gate control signal V of SW2_GWhen the intermediate second control switch shorts the first level shifter to make V_G＝V_B。

When VSW is low level (High) it is necessary to turn on SW2 and select V by the second voltage comparing unit₁/V_IMHigher of the first level shifter, and then V is converted by the first level shifter_GBimax (V)₁,V_IM) High 2V_THThis ensures that SW2 has a small on-resistance.

Due to the Bulk voltage V_BUsing V all the time₁/V_IMThe lower one, so that the Bulk voltage can be guaranteed to be the lowest voltage of the NMOS tube.

Referring to fig. 5, which is a specific implementation circuit of the voltage follower unit in this embodiment, the first voltage comparison unit (small) includes a first differential pair composed of two PMOS transistors, and the second voltage comparison unit (large) includes a second differential pair composed of two NMOS transistors.

Specifically, the first voltage comparison unit (small) comprises a first differential pair consisting of two PMOS tubes P1 and P2, and the gate voltages of the PMOS tubes P1 and P2 are V respectively₁And V_IMA source connected to a current source I1, a drain connected to a resistor R₅、R₆Connected in series with a current source I2 and a resistor R₅And a current source I2_B。

The second voltage comparison unit (lager) comprises a second differential pair consisting of two NMOS tubes N1 and N2, and the grid voltages of the NMOS tubes N1 and N2 are V respectively₁And V_IMAnd source electrode connecting resistor R₃Then electrically connected with a current source I2, and a drain electrode connected with a resistor R₇、R₈After being connected in series, the current source I3 is electrically connected with a switch S1The switch S1 is a PMOS transistor, the switch S1 is used to control whether the second voltage comparing unit works, and the gate driving signal is VSW. Second voltage comparison unit and resistor R₃Between voltage is V_B。

The first level shifter comprises two NMOS transistors N3, N4 connected in series for obtaining max (V)₁,V_IM) After being lifted, the steel sheet is taken as V_GAnd (6) outputting. N4 source electrode connected to V_AThe gate and the drain are electrically connected with the source of N3, and the gate and the drain of N3 have voltage V_GAnd is connected with a resistor R₄At the resistance R₃The N3 and N4 are electrically connected with a current source I4 through a switch S2, the switch S2 is a PMOS tube and is used for controlling whether the first level shifter works or not, and the grid drive signal is

The second level shifter comprises two NMOS transistors N5, N6 connected in series for comparing min (V) obtained by the first voltage comparison unit₁,V_IM) After reducing the pressure, the product is used as V_BAnd (6) outputting.

Specifically, in the present embodiment, min (V) is used as the first voltage comparing unit (small) and the second voltage comparing unit (large) through the NMOS and PMOS differential pairs respectively₁,V_IM) And max (V)₁,V_IM) Are selected separately. Wherein min (V)₁,V_IM) Two lower V_GSThen as Bulk voltage V_B。

The switch S1 controls whether the second voltage comparing unit (lager) operates, and when S1 is turned off, current does not flow through the second voltage comparing unit (lager), and the unit does not operate. At this time, S2 is on, and V is due to no current flowing through R3 and R4_A＝V_G＝V_BThe switch SW2 is on.

When S1 is turned on, S2 is turned off, and the second voltage comparing unit (lager) can work normally, V_A＝max(V₁,V_IM) The current flows through several V via S2_GSThe first level shifter is composed to generate a higher voltage V_GSW2 is turned on.

It should be understood thatThe voltage follower unit in the above embodiment is only one specific implementation circuit of the present invention, and other voltage follower circuits may be used to implement the voltage V in other embodiments₁Or V_IMWill not be further illustrated herein.

According to the technical scheme, the invention has the following beneficial effects:

the output buffer control circuit controls the switching between the voltage domains through the floating switch, the leakage current of the MOS tube switch can not flow through the resistor, and the linearity of the output voltage is greatly improved.

It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.