阅读说明：本技术 一种电荷泵锁相环、锁相环和闭环控制电路 (Charge pump phase-locked loop, phase-locked loop and closed-loop control circuit ) 是由 刘程斌 于 2020-06-12 设计创作，主要内容包括：本申请公开了一种电荷泵锁相环,包括：第一PFD、第二PFD、PMOS管、NMOS管、第一开关电流源、第二开关电流源、低通滤波器；还包括：数字延时模块,用于分别对第一PFD和第二PFD的输出信号进行延时,得到第一延时信号和第二延时信号；第一可控开关,与PMOS管相连,用于根据第一延时信号对PMOS管的导通状态进行控制,以使PMOS管的输出电压在开启时刻前与低通滤波器的上极板电压相等；第二可控开关,与NMOS管相连,用于根据第二延时信号对NMOS管的导通状态进行控制,以使NMOS管的输出电压在开启时刻前与低通滤波器的上极板电压相等。显然,这样就能够显著降低电荷泵锁相环所需要的设计成本。(The application discloses charge pump phase-locked loop includes: the device comprises a first PFD, a second PFD, a PMOS tube, an NMOS tube, a first switch current source, a second switch current source and a low-pass filter; further comprising: the digital delay module is used for delaying the output signals of the first PFD and the second PFD respectively to obtain a first delay signal and a second delay signal; the first controllable switch is connected with the PMOS tube and used for controlling the conduction state of the PMOS tube according to the first delay signal so as to enable the output voltage of the PMOS tube to be equal to the voltage of the upper electrode plate of the low-pass filter before the starting time; and the second controllable switch is connected with the NMOS tube and used for controlling the conduction state of the NMOS tube according to the second delay signal so as to enable the output voltage of the NMOS tube to be equal to the voltage of the upper electrode plate of the low-pass filter before the starting time. Obviously, this can significantly reduce the design cost required for the charge pump phase locked loop.)

1. A charge pump phase locked loop comprising: the voltage control circuit comprises a first PFD, a second PFD, a PMOS tube, an NMOS tube, a first switching current source controlled by the first PFD through the PMOS tube, a second switching current source controlled by the second PFD through the NMOS tube, and a low-pass filter connected to the rear ends of the NMOS tube and the PMOS tube, and logic signals output by the first PFD and the second PFD can be converted into voltage signals for controlling a voltage-controlled oscillator by the first switching current source, the second switching current source and the low-pass filter; it is characterized by also comprising:

the digital delay module is used for respectively delaying the output signals of the first PFD and the second PFD to obtain a first delay signal and a second delay signal;

the first controllable switch is connected with the PMOS tube and used for controlling the conduction state of the PMOS tube according to the first delay signal so as to enable the output voltage of the PMOS tube to be equal to the voltage of the upper electrode plate of the low-pass filter before the starting time;

and the second controllable switch is connected with the NMOS tube and used for controlling the conduction state of the NMOS tube according to the second delay signal so as to enable the output voltage of the NMOS tube to be equal to the voltage of the upper electrode plate of the low-pass filter before the starting time.

2. The charge pump phase locked loop of claim 1, wherein the first controllable switch is a PMOS transistor.

3. The charge pump phase locked loop of claim 1, wherein the second controllable switch is an NMOS transistor.

4. The charge pump phase locked loop of any of claims 1 to 3, wherein the digital delay module is embodied as a digital logic circuit having a delay function.

5. The charge pump phase locked loop of any of claims 1 to 3, wherein the digital delay module is embodied as a delay flip-flop.

6. A phase locked loop comprising a charge pump phase locked loop as claimed in any one of claims 1 to 5.

7. A closed loop control circuit comprising a phase locked loop as claimed in claim 6.

Technical Field

The invention relates to the technical field of integrated power electronics, in particular to a charge pump phase-locked loop, a phase-locked loop and a closed-loop control circuit.

Background

Referring to fig. 1, fig. 1 is a schematic diagram of a charge pump phase-locked loop in the prior art, in the charge pump phase-locked loop, when a PMOS transistor and an NMOS transistor are both turned off, a first current source I1 and a second current source I2 discharge the voltage of the NMOS transistor to zero and charge the voltage of the PMOS transistor to Vdd, that is, discharge a Y node to zero and charge an X node to Vdd. Obviously, the voltage variation of the nodes X and Y is different during the voltage variation of the nodes X and Y, wherein the voltage difference between the nodes X and Y is provided by the charge stored in the low-pass filter Cp, but this may cause the voltage of Vcout to jump and cause the jitter of the charge pump phase-locked loop.

At present, the operational amplifier is usually used to eliminate the jitter problem of the charge pump pll, please refer to fig. 2, where fig. 2 is a schematic diagram illustrating the prior art when the operational amplifier is used to eliminate the jitter of the charge pump pll. That is, when S3 and S4 are turned off and S1 and S2 are turned on, the potentials of the X node and the Y node are maintained at Vcout using the operational amplifier, so that at the next phase comparison instant, when S3 and S4 are turned on and S1 and S2 are turned off, since the potentials of the X node and the Y node are both Vcout, the jitter occurring in the charge pump pll can be avoided. However, when the jitter of the charge pump pll is eliminated in this way, the charge pump pll needs to use an operational amplifier which is expensive in cost, which results in a high design cost. At present, no effective solution exists for the technical problem.

Therefore, how to reduce the design cost required by the charge pump phase-locked loop while eliminating the jitter of the charge pump phase-locked loop is a technical problem to be solved urgently by those skilled in the art.

Disclosure of Invention

Accordingly, the present invention is directed to a charge pump pll, a pll and a closed-loop control circuit for reducing the design cost of the charge pump pll. The specific scheme is as follows:

a charge pump phase locked loop comprising: the voltage control circuit comprises a first PFD, a second PFD, a PMOS tube, an NMOS tube, a first switching current source controlled by the first PFD through the PMOS tube, a second switching current source controlled by the second PFD through the NMOS tube, and a low-pass filter connected to the rear ends of the NMOS tube and the PMOS tube, and logic signals output by the first PFD and the second PFD can be converted into voltage signals for controlling a voltage-controlled oscillator by the first switching current source, the second switching current source and the low-pass filter; further comprising:

the digital delay module is used for respectively delaying the output signals of the first PFD and the second PFD to obtain a first delay signal and a second delay signal;

the first controllable switch is connected with the PMOS tube and used for controlling the conduction state of the PMOS tube according to the first delay signal so as to enable the output voltage of the PMOS tube to be equal to the voltage of the upper electrode plate of the low-pass filter before the starting time;

and the second controllable switch is connected with the NMOS tube and used for controlling the conduction state of the NMOS tube according to the second delay signal so as to enable the output voltage of the NMOS tube to be equal to the voltage of the upper electrode plate of the low-pass filter before the starting time.

Preferably, the first controllable switch is a PMOS transistor.

Preferably, the second controllable switch is an NMOS transistor.

Preferably, the digital delay module is embodied as a digital logic circuit with a delay function.

Preferably, the digital delay module is specifically a delay trigger.

Correspondingly, the invention also discloses a phase-locked loop, which comprises the charge pump phase-locked loop disclosed in the foregoing.

Correspondingly, the invention also discloses a closed-loop control circuit which comprises the phase-locked loop disclosed in the foregoing.

Therefore, in the charge pump phase-locked loop provided by the invention, because the digital delay module can be used for delaying the output signals of the first PFD and the second PFD, and the first delay signal and the second delay signal after the delay are used for respectively triggering the first controllable switch and the second controllable switch to control the conduction states of the PMOS tube and the NMOS tube, the output voltage of the PMOS tube and the output voltage of the NMOS tube can be equal to the upper electrode plate voltage of the low-pass filter before the starting time, and the jitter condition of the charge pump phase-locked loop can be eliminated. Obviously, since the manufacturing cost of the digital delay module and the controllable switch is far lower than that of the operational amplifier, the design cost required by the charge pump phase-locked loop can be significantly reduced by such an arrangement. Correspondingly, the phase-locked loop and the closed-loop control circuit provided by the invention also have the beneficial effects.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

FIG. 1 is a schematic diagram of a prior art charge pump phase locked loop;

FIG. 2 is a diagram illustrating a prior art method for eliminating charge pump jitter using an operational amplifier;

fig. 3 is a structural diagram of a charge pump phase-locked loop according to an embodiment of the present invention;

fig. 4 is a timing diagram illustrating operation of a charge pump phase locked loop according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 3, fig. 3 is a structural diagram of a charge pump phase-locked loop according to an embodiment of the present invention, the charge pump phase-locked loop includes: the voltage control circuit comprises a first PFD, a second PFD, a PMOS tube, an NMOS tube, a first switching current source I1 controlled by the first PFD through the PMOS tube, a second switching current source I2 controlled by the second PFD through the NMOS tube, and a low-pass filter Cp connected to the rear ends of the NMOS tube and the PMOS tube, and logic signals output by the first PFD and the second PFD can be converted into voltage signals for controlling a voltage-controlled oscillator VCO through the first switching current source I1, the second switching current source I2 and the low-pass filter Cp; further comprising:

the digital delay module is used for respectively delaying the output signals of the first PFD and the second PFD to obtain a first delay signal UP _ L and a second delay signal DN _ L;

the first controllable switch K1 is connected with the PMOS tube and used for controlling the conduction state of the PMOS tube according to the first delay signal UP _ L so as to enable the output voltage of the PMOS tube to be equal to the voltage of the upper electrode plate of the low-pass filter before the starting time;

and the second controllable switch K2 is connected with the NMOS tube and is used for controlling the conducting state of the NMOS tube according to the second delay signal DN _ L so as to enable the output voltage of the NMOS tube to be equal to the voltage of the upper electrode plate of the low-pass filter before the starting time.

In this embodiment, a novel charge pump phase-locked loop is provided, by which the design cost required by the charge pump phase-locked loop can be reduced while the jitter occurring in the charge pump phase-locked loop is eliminated. Compared with the prior art, the charge pump phase locked loop provided by the embodiment is newly added with a digital delay module, a first controllable switch K1 and a second controllable switch K2, which can be seen in fig. 3 specifically.

When the digital delay module outputs the first delay signal UP _ L and the second delay signal DN _ L, the first delay signal UP _ L and the second delay signal DN _ L are respectively used for controlling the first controllable switch K1 and the second controllable switch K2, so that the output voltage of the PMOS transistor and the output voltage of the NMOS transistor are equal to the upper plate voltage of the low-pass filter before the starting time of the PMOS transistor and the NMOS transistor, that is, the voltage values of the X node and the Y node are equal to the upper plate voltage Vcout of the low-pass filter before the starting time of the PMOS transistor and the NMOS transistor.

Specifically, when the output signal UP of the first PFD is changed into low level UP _ L, the digital delay module delays UP _ L, so that the output voltage of the PMOS tube is equal to the upper plate voltage Vcout of the low-pass filter before the starting time, and similarly, when the output signal DN of the second PFD is changed into low level DN _ L, the digital delay module delays DN _ L, so that the output voltage of the NMOS tube is equal to the upper plate voltage Vcout of the low-pass filter before the starting time.

Referring to fig. 4, fig. 4 is a timing diagram of the charge pump pll in operation according to the embodiment of the present invention, in fig. 4, UP is an output signal of the first PFD, UP _ L is a signal obtained by delaying UP by the digital delay module, UP _ L is always at a high level before NT cycles, in this case, only the PMOS transistor has toggle action, the first controllable switch K1 is always in a closed state, and the charge pump pll completes locking after NT cycles are completed, however, in this process, the low pass filter Cp in the charge pump pll outputs charges to the PMOS transistor or the NMOS transistor, so that output voltages of the PMOS transistor and the NMOS transistor are equal, that is, voltages at the X node and the Y node are equal, which causes a jitter of the charge pump pll, UP occurs in (N +1) T cycles, the charge pump pll is at a low level, the PMOS transistor is turned on, the UP _ L output by the digital delay module is turned on for a period, and if the charge pump pll is turned on for a period, the Cp is turned on, the first controllable switch K56 is turned on, and the charge pump pll is kept in a state of the low pass filter, which is stable, and the charge pump pll is not able to be switched to store a voltage vci, thereby, and to prevent the charge pump pll from being changed, and the vci from being switched.

Obviously, the manufacturing cost of the digital delay module and the controllable switch is far lower than that of the operational amplifier, so that compared with the prior art, the design cost required by the charge pump phase-locked loop can be significantly reduced by the arrangement mode provided by the application.

Therefore, in the charge pump phase-locked loop provided by the invention, because the digital delay module can be used for delaying the output signals of the first PFD and the second PFD, and the first delay signal and the second delay signal after the delay are used for respectively triggering the first controllable switch and the second controllable switch to control the conduction states of the PMOS tube and the NMOS tube, the output voltage of the PMOS tube and the output voltage of the NMOS tube can be equal to the upper electrode plate voltage of the low-pass filter before the starting time, and the jitter condition of the charge pump phase-locked loop can be eliminated. Obviously, since the manufacturing cost of the digital delay module and the controllable switch is far lower than that of the operational amplifier, the design cost required by the charge pump phase-locked loop can be significantly reduced by such an arrangement.

Based on the above embodiments, the present embodiment further describes and optimizes the technical solution, and as a preferred implementation, the first controllable switch K1 is specifically a PMOS transistor.

Specifically, in the present embodiment, the first controllable switch K1 is configured as a PMOS transistor, because when the PMOS transistor disposed at the rear end of the first switching current source I1 and the first controllable switch K1 are configured as controllable switches with the same structure, the stability of the charge pump phase-locked loop during the high-low level conversion of the first PFD can be relatively ensured.

Based on the above embodiments, the present embodiment further describes and optimizes the technical solution, and as a preferred implementation, the second controllable switch K2 is specifically an NMOS transistor.

In practical application, the second controllable switch K2 is set as an NMOS transistor, because the cost of the NMOS transistor is low, and when the NMOS transistors set at the rear ends of the second controllable switch K2 and the second switch current source I2 are both set as NMOS transistors, the structure of the charge pump phase-locked loop can be more orderly, so that the overall reliability of the charge pump phase-locked loop in the working process can be relatively improved.

Based on the above embodiments, this embodiment further describes and optimizes the technical solution, and as a preferred implementation, the digital delay module is specifically a digital logic circuit with a delay function.

In this embodiment, the digital delay module is configured as a digital logic circuit with a delay function, that is, the digital delay module is built by using a basic digital logic circuit not gate, or gate, and gate, etc. It is conceivable that, since the manufacturing cost of the digital logic circuit is low, when the digital delay module is built by using the digital logic circuit, the design cost required by the digital delay module can be further reduced.

Based on the above embodiments, the present embodiment further describes and optimizes the technical solution, and as a preferred implementation, the digital delay module is specifically a delay flip-flop.

In practical application, the digital delay module can be set as a delay trigger, and the delay trigger not only has stable and reliable working performance, but also is common in practical life, so that when the digital delay module is set as the delay trigger, the universality of the charge pump phase-locked loop in practical application can be relatively improved.

Correspondingly, the embodiment of the invention also provides a phase-locked loop, which comprises the charge pump phase-locked loop disclosed in the foregoing.

The phase-locked loop provided by the embodiment of the invention has the beneficial effects of the charge pump phase-locked loop disclosed above.

Correspondingly, the embodiment of the invention also provides a closed-loop control circuit which comprises the phase-locked loop disclosed in the foregoing.

The closed-loop control circuit provided by the embodiment of the invention has the beneficial effects of the phase-locked loop disclosed above.

The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The present invention provides a charge pump phase-locked loop, a phase-locked loop and a closed-loop control circuit, which are described in detail above, and the principle and the implementation of the present invention are explained in this document by applying specific examples, and the description of the above embodiments is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.