阅读说明：本技术 用于校准低功率电压模式发射机驱动器阻抗的系统及方法 (System and method for calibrating low power voltage mode transmitter driver impedance ) 是由 郭飞 李义慧 薛红 马昕 王晖 于 2020-02-03 设计创作，主要内容包括：本申请的实施例涉及用于校准低功率电压模式发射机驱动器阻抗的系统及方法。本文描述了一种用于发射来自集成芯片的数字信号的低功率发射机。发射机包括由多个驱动器片组成的电压模式发射机驱动器,其包括具有第一电阻器和第一晶体管的上单元以及具有第二电阻器、第二晶体管和第三晶体管的下单元。校准电路通过调节施加到上单元的副本的第一晶体管的第一栅极电压并调节施加到下单元的副本的第三晶体管的第二栅极电压,将副本电路驱动到期望的阻抗。校准的第一栅极电压被施加到多个驱动器片中的每个驱动器片的第一晶体管和第二晶体管,并且校准的第二栅极电压被施加到多个驱动器片中的每个驱动器片的第三晶体管。(Embodiments of the present application relate to systems and methods for calibrating low power voltage mode transmitter driver impedance. A low power transmitter for transmitting digital signals from an integrated chip is described herein. The transmitter includes a voltage-mode transmitter driver composed of a plurality of driver slices, which includes an upper cell having a first resistor and a first transistor, and a lower cell having a second resistor, a second transistor, and a third transistor. The calibration circuit drives the replica circuit to a desired impedance by adjusting a first gate voltage applied to a first transistor of the replica of the upper cell and adjusting a second gate voltage applied to a third transistor of the replica of the lower cell. The calibrated first gate voltage is applied to the first transistor and the second transistor of each of the plurality of driver slices, and the calibrated second gate voltage is applied to the third transistor of each of the plurality of driver slices.)

1. A low power transmitter for transmitting a digital signal from an integrated chip, the transmitter comprising:

a voltage-mode transmitter driver comprised of a plurality of driver slices, wherein each driver slice comprises:

an upper unit including a first resistor and a first transistor, wherein the upper unit is connected to a voltage source and an output terminal of the voltage mode transmitter driver; and

a lower unit including a second resistor, a second transistor, and a third transistor, wherein the lower unit is connected to the output terminal of the voltage-mode transmitter driver and ground;

a replica circuit comprising a replica of the upper unit and a replica of the lower unit; and

a calibration circuit configured to drive the replica circuit to a desired impedance by adjusting a first gate voltage applied to the first transistor of the replica of the upper cell to be equal to a calibrated first gate voltage and adjusting a second gate voltage applied to the third transistor of the replica of the lower cell to be equal to a calibrated second gate voltage;

a bias generator configured to apply the calibrated first gate voltage to the first and second transistors of each of the plurality of driver slices and to apply the calibrated second gate voltage to the third transistor of each of the plurality of driver slices.

2. The low power transmitter of claim 1, wherein, in response to applying the calibrated first gate voltage to the first and second transistors of each of the plurality of driver slices and in response to applying the calibrated second gate voltage to the third transistor of each of the plurality of driver slices, the upper cell of each of the plurality of driver slices is configured to generate an impedance that matches an impedance of a corresponding lower cell of each of the plurality of driver slices.

3. The low power transmitter of claim 2, wherein a total impedance of the upper cells of the plurality of driver slices is equal to the impedance of the replica of the upper cells in response to applying the calibrated first gate voltage to the first and second transistors of each of the plurality of driver slices and in response to applying the calibrated second gate voltage to the third transistor of each of the plurality of driver slices.

4. The low power transmitter of claim 2, wherein a total impedance of the lower cell of the plurality of driver slices is equal to the impedance of the replica of the lower cell in response to applying the calibrated first gate voltage to the first and second transistors of each of the plurality of driver slices and in response to applying the calibrated second gate voltage to the third transistor of each of the plurality of driver slices.

5. The low power transmitter of claim 1, wherein the replica of the upper unit further comprises:

a copy of the first resistor and a copy of the first transistor, wherein the copy of the upper cell is connected to the voltage source and the output of the voltage mode transmitter driver;

wherein the copy of the lower unit further comprises:

a copy of the second resistor, a copy of the second transistor, and a copy of the third transistor, wherein the copy of the lower cell is connected to the output of the voltage mode transmitter driver and the ground.

6. The low power transmitter of claim 5, wherein the calibration circuit further comprises:

a second lower unit including a fourth transistor and a third resistor;

a constant current source configured to feed a constant current into the second lower unit to generate an output voltage;

a comparator configured to compare the output voltage generated by the second lower unit with a first reference voltage and a second reference voltage; and

a calibration logic control configured to adjust an impedance of the second lower cell to match a first predetermined impedance by adjusting the second gate voltage via a bias generator based on an output of the comparator.

7. The low power transmitter of claim 6, wherein the bias generator is configured to decrease the second gate voltage in response to the calibration logic control receiving a high level output from the comparator indicating that the impedance of the second lower cell is low; and

wherein the bias generator is configured to increase the second gate voltage in response to the calibration logic controlling receiving a low level output from the comparator indicating that the impedance of the second lower cell is high.

8. The low power transmitter of claim 6, wherein the calibration circuit is further configured to:

maintaining, via the bias generator, the second gate voltage at a voltage at which the impedance of the second lower cell matches the first predetermined impedance;

adjusting, via the bias generator, the first gate voltage to a voltage at which an impedance of the replica of the upper cell matches a second predetermined impedance; and

calibrating a first gate voltage to a voltage at which the impedance of the replica of the upper cell matches the second predetermined impedance.

9. The low power transmitter of claim 8, wherein the calibration circuit is further configured to:

maintaining, via the bias generator, the calibrated first gate voltage;

adjusting, via the bias generator, the second gate voltage such that an impedance of the replica of the lower cell matches the second predetermined impedance; and

calibrating the second gate voltage to a voltage at which the impedance of the replica of the lower cell matches the second predetermined impedance.

10. The low power transmitter of claim 9, wherein the bias generator is configured to supply the calibrated first gate voltage to the first and second transistors of each of the plurality of driver slices and the calibrated second gate voltage to the third transistor of each of the plurality of driver slices.

11. A method for transmitting a digital signal from an integrated chip via a low power transmitter comprising a plurality of driver slices, the method comprising:

calibrating, via a calibration circuit of the low power transmitter, a first gate voltage and a second gate voltage by driving a replica circuit of the low power transmitter to a desired impedance;

applying a calibrated first gate voltage to a first transistor of an upper cell of each of the plurality of driver slices;

applying the calibrated first gate voltage to a second transistor of a lower cell of each of the plurality of driver slices; and

applying a calibrated second gate voltage to the third transistor of the lower cell of each of the plurality of driver slices.

12. The method of claim 11, wherein, in response to applying the calibrated first gate voltage to the first and second transistors of each of the plurality of driver slices and in response to applying the calibrated second gate voltage to the third transistor of each of the plurality of driver slices, the upper cells of each of the plurality of driver slices are configured to generate an impedance that matches an impedance of the corresponding lower cells of each of the plurality of driver slices.

13. The method of claim 12, wherein a total impedance of the upper cell of the plurality of driver slices is equal to the impedance of the replica of the upper cell in response to applying the calibrated first gate voltage to the first and second transistors of each of the plurality of driver slices and in response to applying the calibrated second gate voltage to the third transistor of each of the plurality of driver slices.

14. The method of claim 12, wherein a total impedance of the lower cell of the plurality of driver slices is equal to the impedance of the replica of the lower cell in response to applying the calibrated first gate voltage to the first and second transistors of each of the plurality of driver slices and in response to applying the calibrated second gate voltage to the third transistor of each of the plurality of driver slices.

15. The method of claim 11, wherein calibrating, via the calibration circuit of the low power transmitter, the first gate voltage and the second gate voltage by driving the replica circuit of the low power transmitter to a desired impedance comprises:

feeding a constant current to the second lower unit through the constant current source to generate an output voltage;

comparing the output voltage generated by the second lower unit with a first reference voltage and a second reference voltage via a comparator; and

adjusting, via calibration logic control, an impedance of the second lower cell to match a first predetermined impedance by adjusting the second gate voltage via a bias generator based on an output of the comparator.

16. The method of claim 15, further comprising:

reducing, via the bias generator, the second gate voltage in response to the calibration logic control receiving a high level output from the comparator indicating that the impedance of the second lower cell is low.

17. The method of claim 15, further comprising:

increasing, via the bias generator, the second gate voltage in response to the calibration logic control receiving a low level output from the comparator indicating that the impedance of the second lower cell is high.

18. The method of claim 15, further comprising:

maintaining, via the bias generator, the second gate voltage at a voltage at which the impedance of the second lower cell matches the first predetermined impedance;

adjusting, via the bias generator, the first gate voltage to a voltage at which an impedance of the replica of the upper cell matches a second predetermined impedance; and

calibrating the first gate voltage to a voltage at which the impedance of the replica of the upper cell matches the second predetermined impedance.

19. The method of claim 18, further comprising:

maintaining the calibrated first gate voltage via the bias generator;

adjusting, via the bias generator, the second gate voltage such that an impedance of the replica of the lower cell matches the second predetermined impedance; and

calibrating the second gate voltage to a voltage at which the impedance of the replica of the lower cell matches the second predetermined impedance.

20. The method of claim 19, further comprising:

supplying the calibrated first gate voltage to the first and second transistors of each of the plurality of driver slices and the calibrated second gate voltage to the third transistor of each of the plurality of driver slices via the bias generator.

Technical Field

The present disclosure relates to configuration of low power transmitter drivers, and in particular to configurations for calibrating impedances of different units at a low power voltage mode transmitter driver.

Background

Voltage mode transmitter drivers are commonly used for chip-to-chip connections for devices such as servers and routers. A voltage-mode transmitter driver typically has two cells, an upper cell with a transistor and a resistor, and a lower cell with a transistor and a resistor. The junction connecting the upper and lower units forms the output terminal of the voltage mode transmitter driver.

High speed chip-to-chip interconnect standards often require that the lower cell impedance and upper cell impedance match the required reference impedance to reduce reflections along the interconnect that degrade signal integrity. In other words, the power supply (V)_S) And the upper cell impedance between the output terminal and the lower cell impedance between the output terminal and ground needs to be equal to a certain reference impedance value. However, the transistors in the upper cell or the lower cell are generally composed of large-sized n-type transistors. The resistance of the transistors is typically due to different drive voltage levelsBut varies significantly and may be quite unstable due to environmental factors such as temperature, humidity, vibration, etc. Thus, the varying resistance of the n-type transistors in the upper and lower cells typically results in a mismatch between the upper and lower cell impedances, especially during different operating modes of the transistors. Such mismatches often cause excessive noise in the voltage-mode transmitter driver and produce unstable and even erroneous outputs at the output terminals of the voltage-mode transmitter driver.

Disclosure of Invention

Embodiments described herein provide a low power transmitter for transmitting digital signals from an integrated chip. The transmitter includes a voltage-mode transmitter driver comprised of a plurality of driver slices, wherein each driver slice includes an upper cell and a lower cell. The upper unit comprises a first resistor and a first transistor, wherein the upper unit is connected to a voltage source and to an output of the voltage mode transmitter driver. The lower cell includes a second resistor, a second transistor, and a third transistor, wherein the lower cell is connected to an output of the voltage-mode transmitter driver and ground. The transmitter further includes a replica circuit that includes a replica of the upper unit and a replica of the lower unit. The calibration circuit of the transmitter is configured to drive the replica circuit to a desired impedance by adjusting a first gate voltage applied to the first transistor of the replica of the upper cell to be equal to the calibrated first gate voltage and adjusting a second gate voltage applied to the third transistor of the replica of the lower cell to be equal to the calibrated second gate voltage. The bias generator applies a calibrated first gate voltage to the first transistor and the second transistor of each of the plurality of driver slices and applies a calibrated second gate voltage to the third transistor of each of the plurality of driver slices.

In some embodiments, the upper unit of each of the plurality of driver slices is configured to: generating an impedance that matches an impedance of a corresponding lower unit of each of the plurality of driver slices in response to the first and second transistors applying the calibrated first gate voltage to each of the plurality of driver slices and the third transistor applying the calibrated second gate voltage to each of the plurality of driver slices.

In some embodiments, in response to applying the calibrated first gate voltage to the first and second transistors of each of the plurality of driver slices and applying the calibrated second gate voltage to the third transistor of each of the plurality of driver slices, a total impedance of the upper cell of the plurality of driver slices is equal to an impedance of the replica of the upper cell.

In some embodiments, in response to applying the calibrated first gate voltage to the first and second transistors of each of the plurality of driver slices and applying the calibrated second gate voltage to the third transistor of each of the plurality of driver slices, a total impedance of a lower cell of the plurality of driver slices is equal to an impedance of a replica of the lower cell.

In some embodiments, the copy of the upper cell further comprises a copy of the first resistor and a copy of the first transistor, wherein the copy of the upper cell is connected to the voltage source and the output of the voltage mode transmitter driver. The replica of the lower cell further includes a replica of the second resistor, a replica of the second transistor, and a replica of the third transistor, wherein the replica of the lower cell is connected to the output of the voltage mode transmitter driver and ground.

In some embodiments, the calibration circuit further comprises: a second lower unit including a fourth transistor and a third resistor; and a constant current source configured to feed a constant current into the second lower unit to generate an output voltage; a comparator configured to compare an output voltage generated by the second lower unit with a first reference voltage and a second reference voltage; and a calibration logic control configured to adjust an impedance of the second lower cell to match the first predetermined impedance by adjusting the second gate voltage via the bias generator based on an output of the comparator.

In some embodiments, the bias generator is configured to decrease the second gate voltage in response to the calibration logic controlling receiving a high level output from the comparator indicating that the impedance of the second lower cell is low. In some embodiments, the bias generator is configured to increase the second gate voltage in response to the calibration logic controlling receiving a low level output from the comparator indicating that the impedance of the second lower cell is high.

In some embodiments, the calibration circuit is further configured to (i) maintain the second gate voltage at a voltage at which the impedance of the second lower cell matches the first predetermined impedance via the bias generator, (ii) adjust the first gate voltage to a voltage at which the impedance of the copy of the upper cell matches the second predetermined impedance via the bias generator, and (iii) calibrate the first gate voltage to a voltage at which the impedance of the copy of the upper cell matches the second predetermined impedance.

In some embodiments, the calibration circuit is further configured to (i) maintain the calibrated first gate voltage via the bias generator; (ii) (ii) adjusting the second gate voltage via the bias generator such that the impedance of the replica of the lower cell matches the second predetermined impedance, and (iii) calibrating the second gate voltage to a voltage at which the impedance of the replica of the lower cell matches the second predetermined impedance.

In some embodiments, the bias generator is configured to supply a calibrated first gate voltage to the first transistor and the second transistor of each of the plurality of driver slices and supply a calibrated second gate voltage to the third transistor of each of the plurality of driver slices.

Drawings

Other features of the present disclosure, its nature and various advantages will become apparent from the following detailed description when considered in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout, and:

fig. 1 is a block diagram illustrating a low power voltage mode transmitter driver using additional transistors with adjustable gate voltages applied to calibrate the impedance of upper and lower cells, according to some embodiments described herein;

FIG. 2 is a logic flow diagram illustrating a process of operating the circuit shown in FIG. 1 to calibrate the impedance of a voltage mode transmitter according to one embodiment described herein.

Fig. 3 is a circuit diagram illustrating a voltage mode transmitter driver slice and a replica slice for calibrating impedance in a voltage mode transmitter driver, according to some embodiments described herein; and

fig. 4 illustrates a circuit diagram of a calibration circuit for calibrating the impedance of the upper and lower cells in replica tile 201 to a desired impedance value, according to some embodiments herein; and

fig. 5 a-5 c are logic flow diagrams illustrating a process 500 of operating the circuit shown in fig. 4 for calibrating impedance in replica tile 201 according to one embodiment described herein.

Fig. 6 is a system diagram of a low power transmitter according to one embodiment described herein.

Detailed Description

In view of the problem of impedance mismatch in voltage-mode transmitter drivers, systems and methods for independently calibrating the respective impedances of upper and lower cells in a low-power voltage-mode transmitter driver are described herein. In some embodiments, the low power voltage mode transmitter driver may be used in technical systems such as servers and routers. These systems require high speed, low power consumption, area efficient chip-to-chip interconnects.

Fig. 1 is a circuit diagram 100 illustrating a low power voltage mode transmitter driver that calibrates the impedance of upper and lower cells using additional transistors with adjustable gate voltages applied thereto, and fig. 2 is a logic flow diagram illustrating a process of operating the circuit 100 shown in fig. 1 to calibrate the impedance of a voltage mode transmitter according to one embodiment described herein. The circuit diagram 100 of fig. 1 illustrates a low power voltage mode driver modeled as having an upper cell 102 and a lower cell 104. The upper unit 102 and the lower unit 104 may be used to provide different bits of the data stream. The upper cell 102 includes a transistor 106 and a resistor 108, one end of the resistor 108 being connected to the source of the transistor 106. Crystal grainThe source of transistor 106 is connected to a voltage source (V)_S). The other terminal of resistor 108 is connected to the output 118 of the voltage-mode transmitter driver. In conventional transmitter drivers, the value of resistor 108 is selected to ensure that the output impedance measured at output terminal 118 matches the desired impedance. In such embodiments, the upper cell impedance may be measured as R (108) +1/Gmn1(106), where Gmn1(106) is the transconductance of device 106. For example, in a conventional transmitter, when the desired impedance is 50 ohms, an appropriate resistance value may be selected for resistor 108. The gate terminal of transistor 106 is connected to the output terminal of voltage driver 120. Voltage driver 120 has V_IPAnd an adjustable drive voltage V_DDR. In an embodiment, the drive voltage V is adjusted_DDRTo change the output voltage from the voltage driver 120 applied to the gate of the transistor 106 to change the resistance of the transistor 106, which in turn changes the voltage at the voltage source V_SAnd the impedance of the upper cell 102 between the output terminals 118.

Lower cell 104 includes a resistor 112 having one terminal connected to output 118 and another terminal connected to the drain of transistor 114. Transistor 114 is driven by a voltage driver 110, the voltage driver 110 being similar to voltage driver 120, having V_INAnd the same adjustable drive voltage V_DDR. Similar to the upper cell, the impedance of the lower cell between the output 118 and ground can be adjusted by adjusting the adjustable drive voltage_VDDRTo change.

An additional transistor 116 is connected to the source of transistor 114. Specifically, a source terminal of transistor 114 is connected to a drain terminal of an n-type transistor 116. The source terminal of n-type transistor 116 is connected to ground.

The gate terminal of the n-type transistor 116 is connected to a tunable gate voltage (V)_G). Except for V_DDRIn addition, the gate voltage V can be adjusted_GTo change the resistance of transistor 116, which in turn changes the impedance of the lower cell.

In some embodiments, the transistor 116 may be a p-type transistor instead of an n-type transistor as shown in fig. 1. In such embodiments, the other transistors 106 and 114 may also be p-type transistors instead of n-type transistors.

The circuit 100 shown in fig. 1 operates as shown at process 200 in fig. 2. At 212, the drain and source terminals of the transistor 106 of the upper cell 102 are connected to a voltage source V, respectively_SAnd an output 118 of the voltage-mode transmitter driver. At 214, the drain and source terminals of the transistor 114 of the lower cell 104 are connected to the output 118 of the voltage-mode transmitter driver and to ground via the additional transistor 116, respectively. At 216, the adjustable gate voltage V is applied_GTo the gate of the additional transistor 116. At 218, the gate voltage V is adjusted_GTo the voltage level of the lower unit impedance between the output terminal 118 and ground and the voltage source V_SAnd the output terminal 118. By adjusting V_GThe output impedance variation between the impedance of the upper cell 102 and the impedance of the lower cell 104 can be reduced.

Fig. 3 is a circuit diagram illustrating a voltage mode transmitter driver slice and a replica slice to calibrate impedance in a voltage mode transmitter driver according to some embodiments described herein. In one implementation, as shown in fig. 3, multiple identical copies (referred to as "slices") of the transmitter driver 100 of fig. 1 are connected in parallel. Each driver slice includes an instance of upper cell 102, lower cell 104, and additional transistor 116. The same voltage drivers 120 and 110 may be applied to the upper and lower cells in all driver slices.

The respective impedances of the upper or lower cells may be set to match a desired reference value. For example, the desired impedance of the upper unit 102 of the low power voltage mode transmitter driver is 50 ohms. Similarly, the desired impedance of the lower cell 104 of the low power voltage mode transmitter driver is also 50 ohms in order to match the desired upper cell impedance. To achieve a target impedance of 50 ohms for both upper cell 102 and lower cell 104, for example, when 20 driver slices are connected in parallel, each driver slice may need to be adjusted to have a respective upper cell impedance of 1K ohms. The net impedance of 20 driver slices connected in parallel can be measured using the following equation:

where Z is 1k ohms (per driver slice) and n is Z producing 50 ohms_NetNumber of driver slices (20). In some embodiments, to achieve different target impedances for voltage-mode transmitter driver 100, each driver slice may be adjusted to present different impedance values for the respective upper-cell or lower-cell impedance.

To achieve the desired impedance in the upper unit 102 and the lower unit 104 of the voltage mode transmitter driver, a replica slice 201 similar to the original driver slice is connected to the original parallel connected driver slices. Each of the 20 driver slices can be tuned to an impedance of 1k ohms by tuning the replica slice to a value of 1k ohms. This will eventually result in the impedance of the upper and lower units 102, 104 of the transmitter driver 100 being calibrated to a desired value of 50 ohms. The copy sheet 201 includes an upper copy unit 202 and a lower copy unit 204. Replica upper unit 202 includes a transistor 206 that is a replica of transistor 106 and a resistor 208 that is a replica of resistor 108. Replica lower cell 204 includes a transistor 214 that is a replica of transistor 114 and a resistor 212 that is a replica of resistor 112, and a replica transistor 216 that is a replica of transistor 116. All duplicate components are connected in a similar manner as the components are connected in the drive 100. Drive voltage V_DDRIs applied to the gate terminals of transistors 206 and 214.

Adjustable voltage V_GAnd V_DDRWill be adjusted to calibrate the impedance of the replica upper unit 202 and the replica lower unit 204 to the desired value (in this case 1K ohms). Since the replica chip is connected in parallel to the driver chip via connection 218, the voltage V is adjusted when the impedance in the replica chip reaches a desired value_GAnd V_DDRThe impedance in each of the original driver slices is calibrated in turn to reach the desired value (1K ohms in this case). Fig. 4-5C further describe aspects of calibrating the replica tile 201.

FIG. 4 illustrates a diagram according to the present inventionHerein, some embodiments are directed to a circuit diagram of a calibration circuit for calibrating respective impedances of upper and lower cells in the replica chip 201 to desired impedance values. In some embodiments, the respective impedances of the upper cell 202 and the lower cell 201 are calibrated independently of each other. Adjusting the independent voltage V with a bias generator 302 controlled by calibration logic 304_GAnd V_G1Independent calibration of the impedance of the upper cell 202 and the lower cell 204 occurs. The calibration circuit 400 is arranged to adjust the copy sheet 201. The gate terminal of transistor 206 of cell 202 on the replica slice 201 is connected to switch box 318. Switch box 318 has switch A, which when closed connects the gate terminal of replica transistor 206 to V_DDR210. Switch box 318 has another switch B that grounds the gate terminal of replica transistor 206 when B is closed. Similarly, the gate terminal of the transistor 214 of the cell 202 on the replica of the replica slice 201 is connected to the switch box 316. Switch box 316 has switch A, which when closed connects the gate terminal of transistor 214 to V_DDR210. Switch box 316 has another switch B which, when closed, grounds the gate terminal of transistor 214. Replica transistor 216 is connected to V_G208。

Additionally, V_DDR210 are connected to the source terminal of transistor 320. The drain terminal of the transistor 320 is connected to a power supply V_S. The gate terminal of transistor 320 is connected to bias generator 302, and bias generator 302 in turn outputs a bias output voltage V_G1To be applied at the gate of transistor 320 and output V_G208 to be applied at the gate of the replica transistor 216. By adjusting V_G1Bias generator 302 indirectly changes V through transistor 320_DDR210. The bias generator 302 is controlled by a calibration logic unit 304, the calibration logic unit 304 sending signals to the bias generator to adjust the output voltage V_GAnd V_G1(and indirectly adjust V_DDR) So that both the copy-on cell 202 and the copy-off cell 204 of the copy sheet 201 exhibit the desired impedance values.

Calibration logic 304 receives two inputs: a clock and an output from comparator 306. In addition to controlling the bias generator 302, the calibration logic unit 304 also controls the switch box 318, the switch box 316, the switch box 314, the switch 326, and the select bits of the multiplexer 308, as described further below. Comparator 306 compares the voltage level measured at output terminal 328 with the reference voltage value retrieved from multiplexer 308.

To adjust the impedance of the replica upper cell 202 independently of the impedance of the replica lower cell 204, a second lower cell 312 is added in parallel to the replica lower cell 204 in the calibration circuit 300. The lower cell 312 includes a transistor 322 and a resistor 324. The source terminal of transistor 322 is connected to ground and the drain terminal of transistor 322 is connected to resistor 324. A gate terminal of transistor 322 is connected to switch box 314. The switch box 314 has a switch A which, when connected, applies a voltage V to the transistor 322_G(connected to bias generator 302). Additionally, the switch box 314 has another switch 314B, the gate terminal of the transistor 322 being grounded when the switch 314B is connected. Resistor 324 of lower cell 312 is connected to switch 326, and switch 326 connects resistor 324 to current source 310.

To calibrate the impedance of replica upper unit 202, replica lower unit 204, and lower unit 312, the voltage level is measured at output terminal 328. The voltage level measured at output terminal 328 is compared to a reference voltage value at comparator 306. In particular, different reference voltage values may be selected from the multiplexer 308 by the calibration logic 304. Calibration logic 304 provides a select signal to multiplexer 308 to cause multiplexer 308 to output one of the available reference voltage values, e.g., based on a calibration phase. Additionally, based on the output value of comparator 306, calibration logic unit 304 sends a signal to bias generator 302 to adjust output voltage V_GAnd V_G1Or modify any of switches 314, 316, 318, and 326. The operation of the various components of circuit diagram 400 are further described in conjunction with fig. 5A-5C.

In some embodiments, the impedance of the cell 202 on the replica is first calibrated and is for V_DDRThe corresponding value of 210 is fixed. Subsequently, the voltage V can be adjusted_G208 to calibrate the replicaThe impedance of the lower cell 204. To adjust the impedance of the cell 202 on the replica, a lower cell 312 is deployed. The impedance of the lower cell 312 is controlled by resistor 324 and transistor 322. In some embodiments, to obtain a desired impedance of 1K ohms in the replica upper unit 202 and the replica lower unit 204 of the replica sheet 201, the impedance of the lower unit 312 is fixed at 3K ohms. Based on the desired impedance values for the upper cell 102 and the lower cell 104, a desired impedance value of 3k ohms for the lower cell 312 is selected. In some embodiments, the expected value of the impedance of the lower cell 312 may be different if the expected values of the impedances for the upper cell 102 and the lower cell 104 are different than 50 ohms.

Fig. 5A-5C are logic flow diagrams illustrating a process 500 of operating the circuit shown in fig. 4 for calibrating impedance in the replica tile 201 according to one embodiment described herein.

According to an example embodiment, the lower cell 312 is first calibrated such that the impedance of the lower cell 312 is set to a desired value (e.g., 3k ohms in this case). At the start of the impedance calibration of the lower cell 312, the calibration logic 304 sends control signals to close switch B at 318, close switch B at 316, close switch 326, and close switch a at 314. At the same time, calibration logic 304 sends control signals to open switch a at 318, switch a at 316, and switch B at 314. By controlling the switches in this manner, transistors 206 and 214 are effectively removed from the circuit, and transistor 322 is connected to current source 310. Calibration logic 304 selects REF1 as the reference voltage from multiplexer 308 for the reference input to comparator 306. A second input of the comparator 304 is the voltage measured at the output terminal 328.

Specifically, at 502, a constant current from the constant current source 310 is fed to the lower cell 312. This may produce a voltage on the lower cell 312 that may be measured at the output terminal 328.

At 504, a voltage level at the output terminal 328 is measured, the measured voltage level being indicative of an impedance between the output terminal 328 and ground. As shown in fig. 4, the measured voltage level at output terminal 328 is fed into the negative terminal of comparator 306.

At 506, an output is provided from a multiplexer 308, the multiplexer 308 connected to a first reference voltage source providing a first reference voltage value REF1 and a second reference voltage source providing a second reference voltage value REF 2. At 508, the calibration logic unit 304 sends a select signal causing the multiplexer 308 to output one of the first reference voltage value REF1 and the second reference voltage value REF 2. For example, to calibrate the impedance across lower cell 312, the REF1 reference voltage is selected. In some embodiments, the reference voltage values REF1 and REF2 are predefined based on the desired impedances of upper cell 102 and lower cell 104.

At 510, comparator 306 compares the first voltage level detected at output terminal 328 to a reference voltage value REF1 from multiplexer 308. The output of the comparison indicates that the following are sent to calibration logic unit 304: the voltage level at output terminal 328 is greater than reference voltage REF1, less than reference voltage REF1, or substantially similar to reference voltage REF 1. As used herein, "substantially similar" means that two entities with tolerable differences are nearly identical or equivalent due to limited measurement accuracy.

At 512, calibration logic unit 304 controls whether the output of comparator 306 indicates that the voltage level at output terminal 328 deviates from the first reference voltage value REF 1.

In response to determining that the output of comparator 306 indicates that the voltage level at output terminal 328 deviates from REF1, calibration logic unit 304 sends a signal to bias generator 302 causing bias generator 302 to adjust the adjustable gate voltage V based on the sign of the output of comparator 306_GUntil the updated output of comparator 306 indicates that the updated voltage level at output terminal 328 is substantially similar to reference voltage value REF 1.

For example, in some embodiments, a high positive output from comparator 306 means that the voltage at output terminal 328 is too low, and calibration logic unit 304 will command offset generator 302 to decrease V_GVoltage to increase the voltage measured on the lower cell 312. Similarly, if the output of comparator 306 is low, thenCalibration logic 304 may command offset generator 302 to increase V_G208. In some embodiments, the output from the multiplexer 308 may be connected to the negative terminal of the comparator 306, while the output terminal 328 may be connected to the positive terminal of the comparator 306. In this case, the response of the calibration logic will also be the opposite of the previous embodiment.

Finally, based on the signal from the calibration logic unit 304, V is paired using the bias generator 302_GThe modification(s) may be such that the voltage at 328 is substantially similar to the REF1 voltage, or at least within a predetermined allowable range of the REF1 voltage. In such an embodiment, V_GA slight increase or decrease in this will cause the comparator output to toggle from high to low or from low to high. At this point, calibration of the lower cell 312 to the desired 3K ohms impedance is complete.

Once the voltage at output terminal 328 measured on lower cell 312 reaches a desired value (REF1), replica chip 201 is connected to lower cell 312 to be calibrated. Calibration of the replica upper unit 202 is performed by connecting the lower unit 312 to the replica upper unit 202. Calibration logic 304 accomplishes this by closing switch a at 318, closing switch B at 316, and closing switch a at 314 and opening switch B at 318, opening switch a at 316, opening switch 326, and opening switch B at 314. Calibration logic 304 selects REF1 as the voltage reference from multiplexer 308. A voltage REF1 is fed to the positive input of the comparator 306. Calibration logic 304 commands bias generator 302 to lock voltage V from the calibration configuration of lower cell 312_GThe value of (c).

At 518, the replica upper unit 202 is connected to the lower unit 312. The replica lower cell 204 and the current source 310 are removed from the calibration circuit 300 based on the switch configuration selected by the calibration logic 304 as described above. The replica upper unit 202 and lower unit 312 are part of the calibration circuit 300. Once the replica upper cell 202 is connected to the lower cell 312, the voltage level is measured at the output terminal 328.

At 520, comparator 306 compares the voltage level detected at output terminal 328 to a first reference voltage value REF 1.

In the judgmentAt decision block 522, calibration logic 304 determines whether the output of comparator 306 indicates that the second voltage level at output terminal 328 deviates from the first reference voltage value REF 1. The output of the comparator is provided to calibration logic 304. Based on the result, calibration logic 304 controls the bias generator 302 via V_G1208 supply the voltage of the calibration circuit 300.

At 524, in response to determining that the output of comparator 306 indicates that the voltage level at output terminal 328 deviates from the first reference voltage value REFl, calibration logic 304 sends a second signal to bias generator 302 causing bias generator 302 to adjust the second adjustable gate voltage V based on the sign of the second output of comparator 306_G1Until the updated second voltage level of comparator 306 indicates that the updated second voltage level at the output terminal is substantially similar to first reference voltage value REF 1.

At 526, in response to determining that the output of comparator 306 indicates that the first voltage level at output terminal 328 does not deviate from the first reference voltage value REFl, but is substantially similar to the first reference voltage value REFl, calibration logic 304 applies an adjusted second adjustable gate voltage V at the gate of transistor 106 and the gate of second transistor 114 as the transistor driver voltage_G1。

As previously described during calibration of the lower cell 312, the calibration logic 304 controls the bias generator 302 to adjust the voltage V based on the results received from the comparator 306_G1To change V_DDR. During this process, the voltage V_GIs maintained at a value selected during the time of calibration of the lower cell 312. In some embodiments, when the output of comparator 306 is high, it means that the impedance of cell 202 on the replica is too large and the calibration logic will command bias generator 302 to increase by V_G1Voltage so as to increase V_DDR210, thereby reducing the impedance of the cell 202 on the replica. On the other hand, if the comparator output is low, the calibration logic 304 will command the bias generator 302 to decrease the voltage V_G1To reduce the voltage V_DDR210. This process is repeated until the voltage REF1 measured at 328 is within a tolerable range.

It should be noted that once the voltage at output terminal 328 is substantially similar to REF1, the impedance of cell 202 on the replica is 1K ohms according to ohm's law (V ═ I × R calibration logic 304 switches the configuration of calibration circuit 300 to calibrate the impedance of cell 204 under the replica to 1K ohms.

Continuing to 530, the lower cell 204 is connected to the constant current source 310 while the calibration logic 304 sends control signals to close switch B at 318, close switch a at 316, close switch 326 and close switch B at 314, and open switch a at 318, open switch B at 314, and open switch a at 316. Calibration logic 304 selects REF2 at multiplexer 308 as the reference voltage to be fed to the positive input of comparator 306. The reference voltage is exchanged from REF1 to REF2 because the desired impedance for the replica lower cell 204 is different than the desired impedance for the lower cell 312. According to this configuration of the calibration circuit 300, the replica upper unit 202 and lower unit 312 are removed from the circuit. Replica lower cell 204 is connected to a current source 310. Current source 310 feeds a fixed amount of current into replica lower cell 204 to produce a voltage across replica lower cell 204 that can be measured at 328.

At 532, comparator 306 compares the voltage measured at output terminal 328 to the REF2 reference voltage received from multiplexer 308. The calibration logic 304 changes the select bit value of the multiplexer 308 to select REF2 instead of REF 1. The output of the comparison is fed to calibration logic 304.

At 534, calibration logic 304 determines whether the output of the comparator indicates that the voltage level at output terminal 328 deviates from the second reference voltage value REF 2.

At 536, in response to determining that the output of the comparator indicates that the voltage level at the output terminal 328 deviates from the second reference voltage value REF2, the calibration logic 304 sends a signal to the bias generator 302 causing the bias generator 302 to adjust the first adjustable gate voltage V based on the sign of the output of the comparator_GUntil the updated output of comparator 306 indicates that the updated voltage level at output terminal 328 is substantially similar to second reference voltage value REF 2. The calibration logic is configured to command the offset generator 302 to modify V_GUntil the measured voltage at output terminal 328 is substantially similar to the REF2 voltage, while maintaining V_G1Is fixed to a previously determined value. In some embodiments, when the output of the comparator is high, the impedance of the cell 204 under the replica is too low, and the calibration logic 304 will command the offset generator 302 to decrease the voltage V_GVoltage to increase the impedance of the cell 204 under the replica. Similarly, if the output of the comparator is low, the calibration logic 304 will command the bias generator 302 to increase the voltage V_G. When the lower cell impedance is adjusted to the desired range, calibration of the replica chip is completed.

At 538, the calibration process is complete in response to determining that the output of the comparator indicates that the voltage level at the output terminal 328 does not deviate from the second reference voltage value REF 2. After adjusting the impedance of the lower cell 312, the copy of the copy upper cell 202, and the copy of the copy lower cell 204 to the desired value, the calibration process is complete. Calibrated V_DDRAnd V_GWill be applied to the gate voltages of transistors 106, 114 and 116, respectively, of voltage mode transmitter driver 100.

Figure 6 illustrates a system diagram of a low power transmitter according to one embodiment described herein. As shown in fig. 6, a digital signal will be transmitted from one integrated chip (system-on-chip 602) to another integrated chip (system-on-chip 620) via a low power physical layer transmitter 604. Specifically, as shown in FIG. 6, 80-bit data is transmitted from SOC 602 to transmitter 604 for transmission to SOC 620.

Transmitter 604 includes a transmitter data multiplexer 606, a transmitter driver 608, calibration logic 610, an offset generator 612, and a replica driver unit 614. The calibration logic 610 is configured to drive the replica driver unit 614 to a desired impedance via a bias generator 612. Specifically, the calibration logic 610 adjusts the first gate voltage (VG1) and the second gate Voltage (VG) applied to the replica driver. Once the impedance of the replica driver cell 614 reaches a desired impedance (e.g., 1k ohms), the bias generator applies the calibrated first gate voltage VG1 and the calibrated second gate voltage VG to the transmitter driver 608 (e.g., the low-power voltage mode transmitter driver 100).

As discussed above with reference to fig. 5A-5C, the calibration logic 610 controls the bias generator 612 to set the first gate voltage VG1 and the second gate voltage VG to the calibrated first gate voltage and the calibrated second gate voltage, respectively. Once the calibrated first gate voltage VG1 and the calibrated second gate voltage VG are applied to the transmitter driver 608 (e.g., the first gate voltage VG1 is applied to the first transistor 106 of the upper cell 102 and to the second transistor 114 of the lower cell 104 of each driver slice, and the second gate voltage VG is applied to the third transistor 116 of the lower cell 104, as shown in fig. 1), the impedances of the upper cell 102 and the lower cell 104 match.

In conventional transmitter designs, reflections are generated during transmission from the transmitter 604 to the SOC 620 because the impedances of the upper and lower cells 102, 104 are not continuous. However, the transmitter design described herein provides matched impedance at the transmitter driver 608. Therefore, when a high-speed digital signal to be transmitted is converted into a low-swing analog high-speed signal, no reflection occurs, thereby improving the overall system performance. The transmitted low swing analog high speed signal is received at the physical layer of the receiver 618 before being sent to the SOC 620.

Although operations are depicted in the drawings in a particular order, this should not be construed as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results.

The subject matter of this specification has been described in terms of particular aspects, but other aspects can be implemented and are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve desirable results. As one example, the processes depicted in fig. 4-6 do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some implementations, multitasking and parallel processing may be advantageous. Other variations are within the scope of the following claims.