阅读说明：本技术 一种低复杂度的近阈值异或单元 (Low-complexity near-threshold exclusive OR unit ) 是由 乔树山 袁甲 胡晓宇 于增辉 凌康 于 2020-03-30 设计创作，主要内容包括：本发明涉及一种低复杂度的近阈值异或单元,包括：同或逻辑电路和输出反相器电路,其中电路结构仅采用7个晶体管,不仅结构简单,而且在近阈值状态下具有很好的功能稳定性。(The invention relates to a low-complexity near-threshold exclusive OR unit, which comprises: the circuit structure only adopts 7 transistors, so that the structure is simple, and the circuit has good functional stability in a near-threshold state.)

1. A low complexity near-threshold xor unit, comprising: an exclusive-nor logic circuit and an output inverter circuit.

2. The low complexity near-threshold XOR cell of claim 1, wherein the XNOR logic circuit comprises a first PMOS (MP1), a second PMOS (MP2), a third PMOS (MP3), a first NMOS (MN1), and a second NMOS (MN 2);

the source electrode of the first PMOS (MP1) is connected with a power Voltage (VDD), the grid electrode of the first PMOS (MP1) is connected with a first signal input end (A), and the drain electrode of the first PMOS (MP3) is connected with the source electrode of the third PMOS (MP 3);

the source electrode of the second PMOS (MP2) is connected with a power Voltage (VDD), the grid electrode of the second PMOS (MP2) is connected with a signal output end (XOR), and the drain electrodes of the second PMOS (MP3), the first NMOS (MN1) and the second NMOS (MN2) are respectively connected with the drain electrode of the third PMOS (MP 3);

the source of the third PMOS (MP3) is connected with the drain of the first PMOS (MP1), the grid is connected with the second signal input end (B), and the drains are respectively connected with the drain of the second PMOS (MP2), the source of the first NMOS (MN1) and the drain of the second NMOS (MN 2);

the source electrode of the first NMOS (MN1) is respectively connected with the drain electrode of the second PMOS (MP2), the drain electrode of the third PMOS (MP3) and the drain electrode of the second NMOS (MN2), the grid electrode is connected with the second signal input end (B), and the drain electrode is connected with the first signal input end (A);

the source of the second NMOS (MN2) is connected to the second signal input terminal (B), the gate is connected to the first signal input terminal (a), and the drain is connected to the drain of the second PMOS (MP2), the drain of the third PMOS (MP3), and the source of the first NMOS (MN1), respectively.

3. The low complexity near-threshold XOR cell of claim 2, wherein the output inverter circuit comprises a fourth PMOS (MP4) and a third NMOS (MN 3);

the source of the fourth PMOS (MP4) is connected with a power Voltage (VDD), and the drain is connected with the drain of the third NMOS (MN 3); the grid is respectively connected with the drain electrode of the second PMOS (MP2), the drain electrode of the third PMOS (MP3), the source electrode of the first NMOS (MN1), the drain electrode of the second NMOS (MN2) and the grid electrode of the third NMOS (MN 3);

the source of the third NMOS (MN3) is grounded, the drain is connected with the drain of the fourth PMOS (MP4), and the gate is respectively connected with the drain of the second PMOS (MP2), the drain of the third PMOS (MP3), the source of the first NMOS (MN1), the drain of the second NMOS (MN2) and the gate of the fourth PMOS (MP 4).

Technical Field

The invention relates to the technical field of chip near-threshold values, in particular to a low-complexity near-threshold value exclusive OR unit.

Background

With the rise of application fields such as internet of things, medical electronics, intelligent monitoring and the like, a plurality of application scenes with extremely low power consumption emerge. The near-threshold technology realizes the most effective technology of extremely low power consumption of the chip, can bring about reduction of the power consumption magnitude of the chip, and has attracted extensive attention and research in more than ten years. While effective, near-threshold techniques also present significant challenges such as performance degradation, reduced stability, process sensitivity, etc.

In order to improve the circuit stability in the near-threshold state, some auxiliary circuits are often required to be added on the basis of the conventional structure. Although the stability of the circuit in the near-threshold state is improved, the complexity of the circuit is increased, the area is increased, and the effect of power consumption optimization is weakened to a certain extent.

Disclosure of Invention

The invention aims to provide a low-complexity near-threshold exclusive OR unit which is simple in structure and can stably work in a near-threshold state.

In order to achieve the purpose, the invention provides the following scheme:

a low complexity near-threshold xor unit, comprising: an exclusive-nor logic circuit and an output inverter circuit.

Optionally, the exclusive-nor logic circuit includes a first PMOS (MP1), a second PMOS (MP2), a third PMOS (MP3), a first NMOS (MN1), and a second NMOS (MN 2);

the source electrode of the first PMOS (MP1) is connected with a power Voltage (VDD), the grid electrode of the first PMOS (MP1) is connected with a first signal input end (A), and the drain electrode of the first PMOS (MP3) is connected with the source electrode of the third PMOS (MP 3);

the source electrode of the second PMOS (MP2) is connected with a power Voltage (VDD), the grid electrode of the second PMOS (MP2) is connected with a signal output end (XOR), and the drain electrodes of the second PMOS (MP3), the first NMOS (MN1) and the second NMOS (MN2) are respectively connected with the drain electrode of the third PMOS (MP 3);

the source of the third PMOS (MP3) is connected with the drain of the first PMOS (MP1), the grid is connected with the second signal input end (B), and the drains are respectively connected with the drain of the second PMOS (MP2), the source of the first NMOS (MN1) and the drain of the second NMOS (MN 2);

the source electrode of the first NMOS (MN1) is respectively connected with the drain electrode of the second PMOS (MP2), the drain electrode of the third PMOS (MP3) and the drain electrode of the second NMOS (MN2), the grid electrode is connected with the second signal input end (B), and the drain electrode is connected with the first signal input end (A);

the source of the second NMOS (MN2) is connected to the second signal input terminal (B), the gate is connected to the first signal input terminal (a), and the drain is connected to the drain of the second PMOS (MP2), the drain of the third PMOS (MP3), and the source of the first NMOS (MN1), respectively.

Optionally, the output inverter circuit comprises a fourth PMOS (MP4) and a third NMOS (MN 3);

the source of the fourth PMOS (MP4) is connected with a power Voltage (VDD), and the drain is connected with the drain of the third NMOS (MN 3); the grid is respectively connected with the drain electrode of the second PMOS (MP2), the drain electrode of the third PMOS (MP3), the source electrode of the first NMOS (MN1), the drain electrode of the second NMOS (MN2) and the grid electrode of the third NMOS (MN 3);

the source of the third NMOS (MN3) is grounded, the drain is connected with the drain of the fourth PMOS (MP4), and the gate is respectively connected with the drain of the second PMOS (MP2), the drain of the third PMOS (MP3), the source of the first NMOS (MN1), the drain of the second NMOS (MN2) and the gate of the fourth PMOS (MP 4).

According to the specific embodiment provided by the invention, the invention discloses the following technical effects:

the invention discloses a low-complexity near-threshold exclusive OR unit, which adopts a transmission tube structure to realize exclusive OR logic, realizes full-swing output through an upward-pulling path under the condition that two inputs are simultaneously 0, and adopts a feedback PMOS tube to realize full-swing output under the condition that the two inputs are simultaneously 1. The invention only adopts 7 transistors, the area is reduced by more than 50%, and meanwhile, the structure is combined with transmission tube logic and a feedback PMOS circuit, and has good functional stability in a near-threshold state.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.

FIG. 1 is a low complexity logic diagram of a near-threshold XOR cell according to the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The invention aims to provide a low-complexity near-threshold exclusive OR unit, which has a simplified structure, reduces the area and can stably work in a near-threshold state.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.

Fig. 1 is a logic circuit diagram of a low-complexity near-threshold xor unit according to the present invention, and as shown in fig. 1, a low-complexity near-threshold xor unit includes: an exclusive-nor logic circuit and an output inverter circuit of the transmission pipe structure.

The exclusive-nor logic circuit of the transmission tube structure comprises a first PMOS (MP1), a second PMOS (MP2), a third PMOS (MP3), a first NMOS (MN1) and a second NMOS (MN 2).

The connection relationship is as follows:

the source electrode of the first PMOS (MP1) is connected with a power supply Voltage (VDD), the grid electrode of the first PMOS (MP1) is connected with the first signal input end (A), and the drain electrode of the first PMOS (MP1) is connected with the source electrode of the third PMOS (MP 3);

the source of the second PMOS (MP2) is connected with the power supply Voltage (VDD), the gate of the second PMOS (MP2) is connected with the output end (XOR), and the drain of the second PMOS (MP2) is connected with the drain of the third PMOS (MP3), the source of the first NMOS (MN1), the drain of the second NMOS (MN2), the gate of the fourth PMOS (MP4) and the gate of the third NMOS (MN 3);

the source electrode of the third PMOS (MP3) is connected with the drain electrode of the first PMOS (MP1), the grid electrode of the third PMOS (MP3) is connected with the second signal input end (B), the drain electrode of the third PMOS (MP3) is connected with the drain electrode of the second PMOS (MP2), the source electrode of the first NMOS (MN1), the drain electrode of the second NMOS (MN2), the grid electrode of the fourth PMOS (MP4) and the grid electrode of the third NMOS (MN 3);

the drain of the first NMOS (MN1) is connected with the first signal input end (A), the gate of the first NMOS (MN1) is connected with the second signal input end (B), the source of the first NMOS (MN1) is connected with the drain of the second PMOS (MP2), the drain of the third PMOS (MP3), the drain of the second NMOS (MN2), the gate of the fourth PMOS (MP4) and the gate of the third NMOS (MN 3);

the source of the second NMOS (MN2) is connected to the second signal input terminal (B), the gate of the second NMOS (MN2) is connected to the first signal input terminal (a), the drain of the second NMOS (MN2) is connected to the drain of the second PMOS (MP2), the drain of the third PMOS (MP3), the source of the first NMOS (MN1), the gate of the fourth PMOS (MP4), and the gate of the third NMOS (MN 3).

And an output inverter circuit including a fourth PMOS (MP4) and a third NMOS (MN 3).

The connection relationship is as follows:

the source of the fourth PMOS (MP4) is connected with the power supply Voltage (VDD), the gate of the fourth PMOS (MP4) is connected with the drain of the second PMOS (MP2), the drain of the third PMOS (MP3), the source of the first NMOS (MN1), the drain of the second NMOS (MN2) and the gate of the third NMOS (MN3), and the drain of the fourth PMOS (MP4) is connected with the drain of the third NMOS (MN3) to form the output end (XOR) of the circuit;

the source of the third NMOS (MN3) is grounded, the gate of the third NMOS (MN3) is connected with the drain of the second PMOS (MP2), the drain of the third PMOS (MP3), the source of the first NMOS (MN1), the drain of the second NMOS (MN2) and the gate of the fourth PMOS (MP4), and the drain of the third NMOS (MN3) is connected with the drain of the fourth PMOS (MP4) to form the output end (XOR) of the circuit.

The invention also discloses the following technical effects:

the invention discloses a low-complexity near-threshold exclusive OR unit, which has a simple circuit structure and good functional stability in a near-threshold state.

The invention has simple structure, adopts two transmission tube structures to carry out ingenious construction, realizes full-swing output through one pull-up path under the condition that two inputs are simultaneously 0, and adopts a feedback PMOS tube to realize full-swing output under the condition that the two inputs are simultaneously 1. For inputs one is 0 and one is 1, the first NMOS (MN1) and the second NMOS (MN2) in the pass tube must have one opened to pull down the xnor node to zero. Through the structure design of the transmission tube, the invention only adopts 7 transistors to realize the exclusive OR function, and compared with a 15-tube structure of the traditional structure, the complexity is reduced by more than 50%.

The invention has good circuit stability under the state of near threshold value. As described above, when the two inputs are 0 at the same time, a stable pull-up path is formed by the first PMOS (MP1) and the third PMOS (MP 3). When one is 1 and one is 0, the first NMOS (MN1) and the second NMOS (MN2) in the pass transistor must have one opened, and a stable pull-down path is formed for the xnor node. When both inputs are 1, the NMOS pass transistor pulls up the xnor node, which may cause a threshold loss. Aiming at the problem, the invention introduces a feedback PMOS tube: the second PMOS (MP2), when xnor has threshold loss, xnor is 0, will open the pull-up second PMOS (MP2), pulling xnor up to full swing. Therefore, the unit structure has excellent stability in the near-threshold state

The invention is a low-complexity near-threshold exclusive OR unit, and is suitable for the requirement of low-power-consumption design.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.

The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.