阅读说明：本技术 摄像装置 (Image pickup apparatus ) 是由 冈巧 河津直树 铃木敦史 于 2018-11-07 设计创作，主要内容包括：根据本发明的摄像装置设置有：多个像素电路,其包括第一至第三像素电路,各像素电路包括第一端子、第二端子、第三端子、能够存储电荷的存储单元、能够基于第一端子的电压将第三端子连接至存储单元的第一晶体管、能够基于第二端子的电压将预定电压供给到存储单元的第二晶体管和能够输出与存储单元中的电压相对应的信号的输出单元；第一控制线,其在第一方向上延伸且连接至第一至第三像素电路的第一端子；第二控制线,其在第一方向上延伸且连接至第一至第三像素电路的第二端子；第一电压供给线,其连接至第一像素电路的第三端子；第二电压供给线,其连接至第二像素电路的第三端子；第一受光元件,其连接至第三像素电路的第三端子；以及诊断单元。(An image pickup apparatus according to the present invention is provided with: a plurality of pixel circuits including first to third pixel circuits, each pixel circuit including a first terminal, a second terminal, a third terminal, a storage unit capable of storing electric charges, a first transistor capable of connecting the third terminal to the storage unit based on a voltage of the first terminal, a second transistor capable of supplying a predetermined voltage to the storage unit based on a voltage of the second terminal, and an output unit capable of outputting a signal corresponding to the voltage in the storage unit; a first control line extending in a first direction and connected to first terminals of the first to third pixel circuits; a second control line extending in the first direction and connected to second terminals of the first to third pixel circuits; a first voltage supply line connected to the third terminal of the first pixel circuit; a second voltage supply line connected to a third terminal of the second pixel circuit; a first light receiving element connected to a third terminal of the third pixel circuit; and a diagnostic unit.)

1. An image pickup apparatus, comprising:

a plurality of pixel circuits including a first terminal, a second terminal, a third terminal, an accumulation unit configured to accumulate electric charges, a first transistor configured to connect the third terminal to the accumulation unit based on a voltage of the first terminal, a second transistor configured to supply a predetermined voltage to the accumulation unit based on a voltage of the second terminal, and an output unit configured to output a signal corresponding to the voltage in the accumulation unit, respectively, the plurality of pixel circuits including a first pixel circuit, a second pixel circuit, and a third pixel circuit;

a first control line extending in a first direction and connected to the respective first terminals of the first, second, and third pixel circuits;

a second control line extending in the first direction and connected to the respective second terminals of the first, second, and third pixel circuits;

a first voltage supply line connected to the third terminal of the first pixel circuit;

a second voltage supply line connected to the third terminal of the second pixel circuit;

a first light receiving element connected to the third terminal of the third pixel circuit; and

a diagnostic unit configured to perform diagnostic processing based on a first signal output from the output unit of the first pixel circuit and a second signal output from the output unit of the second pixel circuit.

2. The image pickup apparatus according to claim 1, further comprising:

an address generating section configured to generate an address signal; and

a driving unit configured to drive the first control line and the second control line based on the address signal, wherein

The diagnostic unit performs the diagnostic process based on the address signal, the first signal, and the second signal.

3. The image pickup apparatus according to claim 2, wherein the diagnosis unit includes:

a conversion circuit configured to generate a first digital code by performing AD conversion based on the first signal and a second digital code by performing AD conversion based on the second signal, an

Diagnostic circuitry configured to perform the diagnostic processing based on the address signal, the first digital code, and the second digital code.

4. The image pickup apparatus according to claim 2, wherein

The first control line, the second control line, the first voltage supply line, the second voltage supply line, the plurality of pixel circuits, and the first light receiving element are formed on a first semiconductor substrate

The address generating section and the driving unit are formed on a second semiconductor substrate bonded to the first semiconductor substrate.

5. The image pickup apparatus according to claim 1, wherein

The plurality of pixel circuits respectively belong to any one of a plurality of pixel lines,

the first pixel circuit, the second pixel circuit, and the third pixel circuit belong to a first pixel line of the plurality of pixel lines,

a predetermined number of pixel circuits belong to respective ones of the plurality of pixel lines, the respective third terminals of the predetermined number of pixel circuits are connected to the first voltage supply line or the second voltage supply line, the predetermined number is greater than or equal to 2, and

the number of the plurality of pixel lines is less than or equal to the number represented by a connection combination of the respective third terminals and the first voltage supply line or the second voltage supply line in the predetermined number of pixel circuits.

6. The image pickup apparatus according to claim 5, wherein first information includes second information, the first information being represented by a connection combination of the respective third terminals of the predetermined number of pixel circuits and the first voltage supply line or the second voltage supply line, the predetermined number of pixel circuits belonging to the first pixel line, the second information being configured to identify the first pixel line.

7. The image pickup apparatus according to claim 6, wherein the first information further includes third information indicating a property of the first pixel line.

8. The image pickup apparatus according to claim 1, further comprising:

third and fourth control lines extending in the first direction, respectively; and

a signal line connected to the output unit of the first pixel circuit, wherein

The plurality of pixel circuits includes a fourth pixel circuit,

the first terminal of the fourth pixel circuit is connected to the third control line,

the second terminal of the fourth pixel circuit is connected to the fourth control line,

the output unit of the fourth pixel circuit is connected to the signal line, and

the third terminal of the fourth pixel circuit is connected to the second voltage supply line.

9. The image pickup apparatus according to claim 1, further comprising a second light receiving element whose light is blocked, wherein

The plurality of pixel circuits includes a fifth pixel circuit,

the first terminal of the fifth pixel circuit is connected to the first control line,

the second terminal of the fifth pixel circuit is connected to the second control line, and

the third terminal of the fifth pixel circuit is connected to the second light receiving element.

10. The image pickup device according to claim 1, further comprising a voltage supply section configured to apply a first voltage signal having a first voltage and a second voltage to the first voltage supply line.

11. The image pickup apparatus according to claim 10, wherein

The first voltage comprises the predetermined voltage, and

the first voltage signal has the first voltage in a first period in which both the first transistor and the second transistor are turned on, and the second voltage in a second period other than the first period.

12. The image pickup device according to claim 1, further comprising a third voltage supply line, wherein

The plurality of pixel circuits includes a sixth pixel circuit,

the first terminal of the sixth pixel circuit is connected to the first control line,

the second terminal of the sixth pixel circuit is connected to the second control line, and

the third terminal of the sixth pixel circuit is connected to the third voltage supply line.

13. The image pickup apparatus according to claim 1, further comprising a first driving unit configured to drive the first control line, wherein

The first control line has a first end and a second end, the first end is connected with the first driving unit,

the first pixel circuit and the second pixel circuit are arranged in a first region,

the third pixel circuit is arranged in the second region, and

the first region and the second region are arranged in order in a direction from the second end to the first end.

14. The image pickup apparatus according to claim 13, further comprising a second driving unit that is connected to the second end of the first control line and is configured to drive the first control line.

15. The image pickup apparatus according to claim 14, wherein

The plurality of pixel circuits includes a seventh pixel circuit and an eighth pixel circuit,

the respective first terminals of the seventh pixel circuit and the eighth pixel circuit are connected to the first control line,

the respective second terminals of the seventh pixel circuit and the eighth pixel circuit are connected to the second control line,

the third terminal of the seventh pixel circuit is connected to the first voltage supply line,

the third terminal of the eighth pixel circuit is connected to the second voltage supply line,

the seventh pixel circuit and the eighth pixel circuit are arranged in the third region, and

the first region, the second region, and the third region are arranged in order in a direction from the second end to the first end.

16. An image pickup apparatus, comprising:

a plurality of pixel circuits including a first terminal, a second terminal, a third terminal, an accumulation unit configured to accumulate electric charges, a first transistor configured to connect the third terminal to the accumulation unit based on a voltage of the first terminal, a second transistor configured to supply a predetermined voltage to the accumulation unit based on a voltage of the second terminal, and an output unit configured to output a signal corresponding to the voltage in the accumulation unit, respectively, the plurality of pixel circuits including a first pixel circuit, a second pixel circuit, and a third pixel circuit;

a first control line extending in a first direction and connected to the respective first terminals of the first, second, and third pixel circuits;

a second control line extending in the first direction and connected to the respective second terminals of the first, second, and third pixel circuits;

a first voltage supply line connected to the third terminal of the first pixel circuit;

a second voltage supply line connected to the third terminal of the second pixel circuit; and

a first light receiving element connected to the third terminal of the third pixel circuit.

17. An image pickup apparatus, comprising:

a first pixel circuit;

a first signal line connected to the first pixel circuit;

a first conversion circuit configured to generate a first digital code by performing AD conversion based on a signal in the first signal line;

a first selector including a first input terminal supplied with the first digital code and a second input terminal supplied with a first fixed digital code, the first selector being configured to select and output any one of the first digital code and the first fixed digital code;

a transmission section configured to transmit the digital code output from the first selector; and

a diagnostic unit configured to perform a diagnostic process based on the first fixed digital code transmitted by the transmission section.

18. The image capture device of claim 17, further comprising:

a second pixel circuit;

a second signal line connected to the second pixel circuit;

a second conversion circuit configured to generate a second digital code by performing AD conversion based on a signal in the second signal line; and

a second selector including a first input terminal supplied with the second digital code and a second input terminal supplied with a second fixed digital code, the second selector being configured to select and output any one of the second digital code and the second fixed digital code, wherein

The second fixed digital code comprises a digital code different from the first fixed digital code,

the transmission section also transmits the digital code output from the second selector, and

the diagnostic unit executes the diagnostic process based on the first fixed digital code and the second fixed digital code, which are transmitted by the transmission section.

19. The image capture device of claim 17, wherein the first fixed digital code comprises information configured to identify the first conversion circuit.

Technical Field

The present invention relates to an imaging apparatus for capturing an image.

Background

In general, in an image pickup apparatus, pixels are arranged in a matrix, and each pixel includes a photodiode and generates an electric signal corresponding to a light receiving amount. Then, for example, an AD conversion circuit (analog-to-digital converter) converts an electric signal (analog signal) generated in each pixel into a digital signal. Some of such image pickup apparatuses have a Built-in self test (BIST) function (for example, patent document 1).

Reference list

Patent document

Patent document 1: specification of U.S. unexamined patent application publication No. 2005/0231620

Disclosure of Invention

As described above, it is desirable for the image pickup apparatus to perform self-diagnosis by the BIST function to diagnose the presence or absence of a failure.

It is desirable to provide an image pickup apparatus capable of performing self-diagnosis.

A first image pickup device according to an embodiment of the present invention includes a plurality of pixel circuits, a first control line, a second control line, a first voltage supply line, a second voltage supply line, a first light receiving element, and a diagnostic unit. The plurality of pixel circuits respectively include a first terminal, a second terminal, a third terminal, an accumulation unit, a first transistor, a second transistor, and an output unit. The plurality of pixel circuits includes a first pixel circuit, a second pixel circuit, and a third pixel circuit. The accumulation unit is configured to accumulate electric charges. The first transistor is configured to connect the third terminal to the accumulation unit based on a voltage of the first terminal. The second transistor is configured to supply a predetermined voltage to the accumulation unit based on a voltage of the second terminal. The output unit is configured to output a signal corresponding to the voltage in the accumulation unit. The first control line extends in a first direction. The first control line is connected to respective first terminals of the first pixel circuit, the second pixel circuit, and the third pixel circuit. The second control line extends in the first direction. The second control line is connected to respective second terminals of the first pixel circuit, the second pixel circuit, and the third pixel circuit. The first voltage supply line is connected to the third terminal of the first pixel circuit. The second voltage supply line is connected to the third terminal of the second pixel circuit. The light receiving element is connected to the third terminal of the third pixel circuit. The diagnostic unit is configured to perform a diagnostic process based on the first signal and the second signal. The first signal is output from the output unit of the first pixel circuit. The second signal is output from the output unit of the second pixel circuit.

A second image pickup device according to an embodiment of the present invention includes a plurality of pixel circuits, a first control line, a second control line, a first voltage supply line, a second voltage supply line, and a first light receiving element. The plurality of pixel circuits respectively include a first terminal, a second terminal, a third terminal, an accumulation unit, a first transistor, a second transistor, and an output unit. The plurality of pixel circuits includes a first pixel circuit, a second pixel circuit, and a third pixel circuit. The accumulation unit is configured to accumulate electric charges. The first transistor is configured to connect the third terminal to the accumulation unit based on a voltage of the first terminal. The second transistor is configured to supply a predetermined voltage to the accumulation unit based on a voltage of the second terminal. The output unit is configured to output a signal corresponding to the voltage in the accumulation unit. The first control line extends in a first direction. The first control line is connected to respective first terminals of the first pixel circuit, the second pixel circuit, and the third pixel circuit. The second control line extends in the first direction. The second control line is connected to respective second terminals of the first pixel circuit, the second pixel circuit, and the third pixel circuit. The first voltage supply line is connected to the third terminal of the first pixel circuit. The second voltage supply line is connected to the third terminal of the second pixel circuit. The light receiving element is connected to the third terminal of the third pixel circuit.

A third image pickup apparatus according to an embodiment of the present invention includes a first pixel circuit, a first signal line, a first conversion circuit, a first selector, a transmission section, and a diagnostic unit. The first signal line is connected to the first pixel circuit. The first conversion circuit is configured to generate a first digital code by performing AD conversion based on a signal in the first signal line. The first selector includes a first input terminal and a second input terminal. The first input terminal is supplied with a first digital code. The second input terminal is supplied with a first fixed digital code. The first selector is configured to select and output any one of the first digital code and the first fixed digital code. The transmission section is configured to transmit the digital code output from the first selector. The diagnostic unit is configured to perform a diagnostic process based on the first fixed digital code transmitted by the transmission section.

In the first image pickup apparatus according to the embodiment of the invention, the first control line is connected to the respective first terminals of the first pixel circuit, the second pixel circuit, and the third pixel circuit. The second control line is connected to respective second terminals of the first pixel circuit, the second pixel circuit, and the third pixel circuit. The first voltage supply line is connected to the third terminal of the first pixel circuit. The second voltage supply line is connected to the third terminal of the second pixel circuit. The first light receiving element is connected to the third terminal of the third pixel circuit. A diagnostic process is performed based on the first signal and the second signal. The first signal is output from the output unit of the first pixel circuit. The second signal is output from the output unit of the second pixel circuit.

In the second image pickup apparatus according to the embodiment of the present invention, the first control line is connected to the respective first terminals of the first pixel circuit, the second pixel circuit, and the third pixel circuit. The second control line is connected to respective second terminals of the first pixel circuit, the second pixel circuit, and the third pixel circuit. The first voltage supply line is connected to the third terminal of the first pixel circuit. The second voltage supply line is connected to the third terminal of the second pixel circuit. The first light receiving element is connected to the third terminal of the third pixel circuit.

In the third image pickup apparatus according to the embodiment of the present invention, AD conversion is performed based on a signal in the first signal line to which the first pixel circuit is connected, thereby generating a first digital code. The first selector selects and outputs any one of the first digital code and the first fixed digital code. The digital code output from the first selector is transmitted to the diagnostic unit. The diagnostic unit then performs a diagnostic process based on the first fixed digital code.

In the first and second image pickup devices according to the respective embodiments of the present invention, the first voltage supply line is connected to the third terminal of the first pixel circuit, and the second voltage supply line is connected to the third terminal of the second pixel circuit. Thus, self-diagnosis can be performed.

The third image pickup apparatus according to the embodiment of the present invention is provided with a first selector configured to select and output any one of the first digital code and the first fixed digital code. Thus, self-diagnosis can be performed.

It is to be noted that the effects described herein are not necessarily restrictive, but may include any of the effects in the present invention.

Drawings

Fig. 1 is a block diagram illustrating a configuration example of an image pickup apparatus according to a first embodiment of the present invention.

Fig. 2 is a circuit diagram illustrating a configuration example of the pixel shown in fig. 1.

Fig. 3A is a circuit diagram illustrating a configuration example of the dummy pixel shown in fig. 1.

Fig. 3B is another circuit diagram illustrating a configuration example of the dummy pixel shown in fig. 1.

Fig. 4 is a circuit diagram illustrating a configuration example of the pixel array shown in fig. 1.

Fig. 5 is a table showing an example of the arrangement of the dummy pixels shown in fig. 3A and 3B.

Fig. 6 is a circuit diagram illustrating a configuration example of the readout section shown in fig. 1.

Fig. 7 is an explanatory diagram illustrating an embodiment of the image pickup apparatus shown in fig. 1.

Fig. 8 is an explanatory diagram illustrating another embodiment of the image pickup apparatus shown in fig. 1.

Fig. 9 is a timing chart illustrating an operation example of the image pickup apparatus shown in fig. 1.

Fig. 10 is a timing waveform diagram illustrating an operation example of the image pickup apparatus shown in fig. 1.

Fig. 11 is another timing waveform diagram illustrating an operation example of the image pickup apparatus shown in fig. 1.

Fig. 12 is an explanatory diagram illustrating an operation example of the readout unit shown in fig. 6.

Fig. 13 is a schematic diagram illustrating an operation example of the diagnosis process according to the first embodiment.

Fig. 14 is an explanatory diagram illustrating an operation example of the readout section and the diagnosis processing section shown in fig. 1.

Fig. 15 is a block diagram illustrating a configuration example of an image pickup apparatus according to a modification of the first embodiment.

Fig. 16A is a circuit diagram of a configuration example of a dummy pixel according to another modification of the first embodiment.

Fig. 16B is another circuit diagram of a configuration example of a dummy pixel according to another modification of the first embodiment.

Fig. 16C is another circuit diagram of an example of the structure of a dummy pixel according to another modification of the first embodiment.

Fig. 16D is another circuit diagram of a configuration example of a dummy pixel according to another modification of the first embodiment.

Fig. 17 is a table showing an example of the arrangement of the dummy pixels shown in fig. 16A to 16D.

Fig. 18 is an explanatory diagram illustrating an operation example of the readout section and the diagnosis processing section according to another modification of the first embodiment.

Fig. 19 is a table showing an example of the arrangement of virtual pixels according to another modification of the first embodiment.

Fig. 20 is a structural diagram illustrating another embodiment of the image pickup apparatus shown in fig. 1.

Fig. 21 is a structural view illustrating another embodiment of the image pickup apparatus shown in fig. 1.

Fig. 22 is a structural diagram illustrating another embodiment of the image pickup apparatus shown in fig. 1.

Fig. 23 is a structural diagram illustrating another embodiment of the image pickup apparatus shown in fig. 1.

Fig. 24 is a structural diagram illustrating another embodiment of the image pickup apparatus shown in fig. 1.

Fig. 25 is a structural diagram illustrating another embodiment of the image pickup apparatus shown in fig. 1.

Fig. 26 is a structural diagram illustrating another embodiment of the image pickup apparatus shown in fig. 1.

Fig. 27 is a structural view illustrating another embodiment of the image pickup apparatus shown in fig. 1.

Fig. 28A is a structural diagram illustrating another embodiment of the image pickup apparatus shown in fig. 1.

Fig. 28B is a structural diagram illustrating another embodiment of the image pickup apparatus shown in fig. 1.

Fig. 29 is a structural diagram illustrating another embodiment of the image pickup apparatus shown in fig. 1.

Fig. 30 is a structural view illustrating another embodiment of the image pickup apparatus shown in fig. 1.

Fig. 31 is a block diagram illustrating a configuration example of an image pickup apparatus according to the second embodiment.

Fig. 32 is a circuit diagram illustrating a configuration example of the readout section shown in fig. 31.

Fig. 33 is a table showing an example of the fixed number code shown in fig. 32.

Fig. 34 is a schematic diagram illustrating an operation example of the diagnosis process according to the second embodiment.

Fig. 35 is an explanatory diagram illustrating a use example of the imaging apparatus.

Fig. 36 is a block diagram showing an example of a schematic configuration of a vehicle control system.

Fig. 37 is a diagram for assisting in explaining an example of mounting positions of the vehicle exterior information detecting unit and the imaging unit.

Detailed Description

Embodiments of the present invention are described in detail below with reference to the accompanying drawings. Note that the description is given in the following order.

1. First embodiment

2. Second embodiment

3. Use example of imaging device

4. Application example of Mobile body

<1 > first embodiment >

[ construction examples ]

Fig. 1 illustrates a configuration example of an image pickup apparatus (image pickup apparatus 1) according to an embodiment the image pickup apparatus 1 includes a pixel array 10, two scanning units 20L and 20R, a readout section 30, and a controller 40.

The pixel array 10 includes a plurality of pixels P1 arranged in a matrix. The pixels P1 include photodiodes PD (described below) respectively, and generate pixel voltages Vpix corresponding to the light receiving amounts. A plurality of these pixels P1 are arranged in the normal pixel region R1.

Further, the pixel array 10 includes, in addition to the plurality of pixels P1, a plurality of light-shielded pixels P2 and a plurality of dummy pixels P3 (dummy pixels P3A and P3B). Each light-shielded pixel P2 is a pixel including a photodiode PD (described below). For the light-shielded pixel P2, light is shielded. As described below, the light-shielded pixel P2 is used to detect a dark current of the photodiode PD. A plurality of light-shielded pixels P2 are arranged in the light-shielded pixel regions R21 and R22. Each of the dummy pixels P3 is a pixel that does not include the photodiode PD. A plurality of virtual pixels P3 are arranged in the virtual pixel regions R31 and R32. In this example, in the pixel array 10, the virtual pixel region R31, the light-shielded pixel region R21, the normal pixel region R1, the light-shielded pixel region R22, and the virtual pixel region R32 are arranged in this order from left to right in the horizontal direction (lateral direction in fig. 1).

The pixel P1, the light-shielded pixel P2, and the dummy pixel P3 are described in detail below.

Fig. 2 illustrates a configuration example of the pixels P1 in the normal pixel region R1 the pixel array 10 includes a plurality of control lines TG L, a plurality of control lines RST L, a plurality of control lines SE LL, a plurality of power supply lines P L, and a plurality of signal lines SG L in the normal pixel region R1.

Control lines TG L extend in the horizontal direction (lateral direction in fig. 2), respectively, one end of the control line TG L is connected to the scan cell 20L and the other end is connected to the scan cell 20R, that is, the control line TG L is arranged to extend through the dummy pixel region R31, the light-shielded pixel region R21, the normal pixel region R1, the light-shielded pixel region R22, and the dummy pixel region R32 the scan cells 20L and 20R apply a control signal STG to the control line TG L.

Control lines RST L extend in the horizontal direction, respectively, one end of the control line RST L is connected to the scanning unit 20L, the other end is connected to the scanning unit 20R, that is, the control line RST L is arranged to extend through the dummy pixel region R31, the light-shielded pixel region R21, the normal pixel region R1, the light-shielded pixel region R22, and the dummy pixel region R32 the scanning units 20L and 20R apply a control signal SRST to the control line RST L.

Control lines SE LL extend in the horizontal direction, respectively, one end of the control line SE LL is connected to the scan cell 20L and the other end is connected to the scan cell 20R, that is, the control line SE LL is arranged to extend through the dummy pixel region R31, the light-shielded pixel region R21, the normal pixel region R1, the light-shielded pixel region R22, and the dummy pixel region R32 the scan cells 20L and 20R apply a control signal SSE L to the control line SE LL.

The power supply lines P L are respectively connected to a voltage generating section 42 (described below) of the controller 40 the voltage generating section 42 applies a power supply voltage VDD to the power supply line P L.

The signal lines SG L extend in the vertical direction (longitudinal direction in fig. 2), respectively, and the ends thereof are connected to the readout section 30.

The pixel P1 includes a photodiode PD and a pixel circuit CKT that includes transistors TG, RST, AMP, and SE L and a floating diffusion FD.. in this example, the transistors TG, RST, AMP, and SE L are all Metal Oxide Semiconductor (MOS) transistors.

The photodiode PD is a photoelectric converter that generates and accumulates electric charges of an amount corresponding to the light receiving amount. The anode of the photodiode PD is grounded, and the cathode is connected to the source of the transistor TG.

The gate of the transistor TG is connected to a control line TG L through a terminal T1 of the pixel circuit CKT, the source thereof is connected to the cathode of the photodiode PD through a terminal T3 of the pixel circuit CKT, and the drain thereof is connected to the floating diffusion FD.

The floating diffusion portion FD accumulates charges supplied from the photodiode PD, and includes, for example, a diffusion layer formed on a surface of a semiconductor substrate. Fig. 2 illustrates the floating diffusion FD using a symbol of a capacitor.

In this configuration, in the pixel P1, the transistor TG is turned on based on the control signal STG, and the charge generated in the photodiode PD of the pixel P1 is transferred to the floating diffusion FD (charge transfer operation).

The gate of the transistor RST is connected to a control line RST L through a terminal T2 of the pixel circuit CKT, the drain thereof is connected to a power supply line P L, and the source thereof is connected to the floating diffusion FD.

In this configuration, in the pixel P1, before electric charges are transferred from the photodiode PD to the floating diffusion FD, the transistor RST is turned on based on the control signal SRST, and the power supply voltage VDD is supplied to the floating diffusion FD. This causes the voltage of the floating diffusion FD in the pixel P1 to be reset (reset operation).

The transistor AMP has a gate connected to the floating diffusion FD, a drain connected to the power supply line P L, and a source connected to the drain of the transistor SE L.

The transistor SE L has a gate connected to the control line SE LL, a drain connected to the source of the transistor AMP, and a source connected to the signal line SG L.

In this configuration, in the pixel P1, the transistor SE L is turned on so that the transistor AMP is connected to the current source 35 (described below) of the readout section 30, which causes the transistor AMP to operate as a so-called source follower, and outputs a voltage corresponding to the voltage of the floating diffusion FD as the signal SIG to the signal line SG L through the transistor SE L specifically, after the voltage of the floating diffusion FD is reset, the transistor AMP outputs a reset voltage Vreset as the signal SIG in a P-phase (Pre-charge phase) period TP, the reset voltage Vreset corresponding to the voltage of the floating diffusion FD in the P-phase period TP.

Next, light-shielded pixels P2 in the light-shielded pixel regions R21 and R22 are described-similarly to the normal pixel region R1 (fig. 2), in the light-shielded pixel regions R21 and R22, the pixel array 10 includes a plurality of control lines TG L, a plurality of control lines RST L, a plurality of control lines SE LL, a plurality of power supply lines P L, and a plurality of signal lines SG L.

The light-shielded pixel P2 includes a photodiode PD and a pixel circuit CKT, similar to the pixel P1 (fig. 2). The light-shielded pixel P2 is different from the pixel P1 in that light is shielded from entering the photodiode PD by a metal such as tungsten. The light-shielded pixel P2 is used to generate a reference signal to adjust the black level of the pixel P1.

In this configuration, in the light-shielded pixel P2, as with the pixel P1, the transistor SE L is turned on so that the transistor AMP outputs a signal SIG corresponding to the voltage of the floating diffusion FD to the signal line SG L through the transistor SE L light is shielded in the light-shielded pixel P2, and therefore, the voltage of the floating diffusion FD is a voltage corresponding to the dark current of the photodiode PD in the D-phase period TD.

Fig. 3A and 3B illustrate a configuration example of a dummy pixel P3 in each of dummy pixel regions R31 and R32, respectively fig. 3A illustrates an example of a dummy pixel P3A, and fig. 3B illustrates an example of a dummy pixel P3B in dummy pixel regions R31 and R32, a pixel array 10 includes a plurality of control lines TG L, a plurality of control lines L, a plurality of control lines SE LL, a plurality of power lines P L, a plurality of voltage supply lines V L0, and a plurality of signal lines SG L, the voltage supply lines V L0 are connected to voltage generating sections 42 (described below) of a controller 40, respectively, the voltage generating sections 42 apply a single voltage signal SVR to the plurality of voltage supply lines V L, the voltage signal SVR is a signal that changes between a predetermined voltage VR and a power supply voltage VDD, the voltage signal SVR is set to the power supply voltage VDD in a period in which both transistors TG and RST are turned on, and the voltage signal is set to the power supply voltage VDD in a period in which both transistors TG and RST are turned on.

The dummy pixel P3 (dummy pixels P3A and P3B) includes a pixel circuit ckt, respectively the sources of the respective transistors TG of the dummy pixels P3A and P3B have different connection destinations, specifically, as shown in fig. 3A, the source of the transistor TG of the dummy pixel P3A is connected to a power supply line P L, and as shown in fig. 3B, the source of the transistor TG of the dummy pixel P3B is connected to a voltage supply line V L0.

In this configuration, in the dummy pixel P3, as with the pixel P1, the transistor SE L is turned on so that the transistor AMP outputs a signal SIG corresponding to the voltage of the floating diffusion FD to the signal line SG L through the transistor SE L the source of the transistor TG of the dummy pixel P3A is connected to the power supply line P L, and therefore, the voltage of the floating diffusion FD in the D-phase period TD is the power supply voltage VDD. this causes the transistor AMP of the dummy pixel P3A to output a voltage corresponding to the power supply voltage VDD as the signal SIG in the D-phase period TD, further, the source of the transistor of the dummy pixel P3B is connected to the voltage supply line V L0. the voltage of the voltage signal SVR applied to this voltage supply line V L0 is set to the voltage VR in the D-phase period TD, and therefore, the voltage of the floating diffusion FD in the D-phase period TD is the voltage VR., so that the transistor AMP of the dummy pixel P3B outputs a voltage corresponding to the voltage SIG in the D-phase period TD.

Fig. 4 illustrates an arrangement of pixels P1, light-shielded pixels P2, and virtual pixels P3 in the pixel array 10 in fig. 4, a virtual pixel region R31, a light-shielded pixel region R21, and a normal pixel region R1 are drawn, a pixel line L includes pixels P1, light-shielded pixels P2, and virtual pixels P3 in one row, a pixel P1, a light-shielded pixel P2, and a virtual pixel P3 belonging to a specific pixel line L are connected to one control line TG L, to one control line RST L, and to one control line SE LL, in this example, one pixel line L includes 11 virtual pixels P3 (virtual pixels P3[10] to P3[0]) in the virtual pixel region R31, each of these virtual pixels P3[10] to P3[0] is a virtual pixel P3A (fig. 3A) or a virtual pixel P3B 3B (fig. 3B).

In fig. 5, "0" represents a virtual pixel P3A, and "1" represents a virtual pixel P3 b. for example, the 0 th pixel line A [0] has "00000000000" as the arrangement of the virtual pixel P A, that is, 11 virtual pixels P A [10] to P A [0] are all virtual pixels P3 a. the 1 st pixel line A [1] has "A" as the arrangement of the virtual pixel P A, that is, the virtual pixel P A [0] is the virtual pixel P3A, and the other virtual pixels P A [10] to P A [1] are the virtual pixels P3 a. the 2 nd pixel line A [2] has "A" as the arrangement of the virtual pixel P72, that is, that the virtual pixel P A [1] is the virtual pixel P3P 72, the other virtual pixel P A [10] to P A [1] are the virtual pixel P3 a. the 2 nd pixel line A [2] has "A" as the virtual pixel P72, that the arrangement of the virtual pixel P A is the virtual pixel P A, that the virtual pixel P A is the pixel P A, that the pixel P A is the pixel P A, that is the virtual pixel P A, that is the virtual pixel P A is the pixel P A, and the pixel P A is the pixel P A, that is the pixel P3b, and.

It is to be noted that, although the virtual pixel region R31 has been described in fig. 4 and 5, the same applies to the virtual pixel region R32, that is, one pixel line L includes 11 virtual pixels P3 in the virtual pixel region R32, each of these virtual pixels P3 is a virtual pixel P3A or a virtual pixel P3b, similarly to fig. 5, the arrangement of the virtual pixels P3 in the virtual pixel region R32 represents the base number of the pixel line L expressed in binary number, that is, the arrangement of the 11 virtual pixels P3 in the virtual pixel region R32 is the same as the arrangement of the 11 virtual pixels P3 in the virtual pixel region R31.

Based on an instruction from the controller 40, the two scanning units 20L and 20R (fig. 1) sequentially drive the pixels P1, the light-shielded pixels P2, and the virtual pixels P3 in the pixel array 10 in units of pixel lines L, respectively the scanning unit 20L includes an address decoder 21L, a logic section 22L, and a driving section 23L, similarly, the scanning unit 20R includes an address decoder 21R, a logic section 22R, and a driving section 23R.

The address decoder 21L selects the pixel line L in the pixel array 10 based on the address signal ADR supplied from the controller 40, the pixel line L corresponds to the address indicated by the address signal ADR, the logic section 22L generates the signals STG1, SRST1, and SSE L corresponding to each pixel line L based on an instruction from the address decoder 21L, the driving section L5 generates the control signals STG, SRST, and SSE L corresponding to each pixel line L based on the signals STG1, SRST1, and SSE L corresponding to each pixel line L, the same applies to the address decoder 21R, the logic section 22R, and the driving section 23R, the address signal ADR supplied to the address decoder 21R is the same as the address signal ADR supplied to the address decoder 21L, and therefore, the address decoders 21L and 21R select the same pixel line L based on the address signal ADR 639 and the scanning unit 20 in turn from the pixel array 10 and the pixel line 828653 in the pixel array.

The readout section 30 performs AD conversion based on the signal SIG supplied from the pixel array 10 through the signal line SG L, thereby generating an image signal DATA 0.

Fig. 6 illustrates a configuration example of the readout section 30. It is noted that fig. 6 also depicts the controller 40 in addition to the readout section 30. The readout section 30 includes a readout controller 31, a reference signal generator 32, a plurality of Analog-to-Digital (AD) converters ADC [0], ADC [1], ADC [2], … …, a plurality of switches SW (switches SW [0], SW [1], SW [2], … …), and a bus wiring (bus wiring) 100.

The readout controller 31 controls the readout operation of the readout section 30 based on an instruction from the controller 40, specifically, the readout controller 31 supplies a control signal to the reference signal generator 32 so that the reference signal generator 32 generates a reference signal ref (described below). furthermore, the readout controller 31 supplies a clock signal C L K and a control signal CC to the plurality of AD converters ADC so as to control the AD conversion operation of the plurality of AD converters ADC.

The reference signal generator 32 generates a reference signal REF. The reference signal REF has a so-called ramp waveform in which the voltage level gradually decreases with the passage of time in the P-phase period TP and the D-phase period TD. Then, the reference signal generator 32 supplies the generated reference signal REF to the plurality of AD converters ADC.

Each AD converter ADC performs AD conversion based on the signal SIG supplied from the pixel array 10 to convert the voltage of the signal SIG into a digital code a plurality of AD converters ADC are provided in association with a plurality of signal lines SG L specifically, the 0 th AD converter ADC [0] is provided in association with the 0 th signal line SG L [0], the 1 st AD converter ADC [1] is provided in association with the 1 st signal line SG L [1], and the 2 nd AD converter ADC [2] is provided in association with the 2 nd signal line SG L [2 ].

Each AD converter ADC includes capacitors 33 and 34, a current source 35, a comparator 36, a counter 37, and a latch 38, one end of the capacitor 33 is supplied with a reference signal REF, and the other end is connected to a positive input terminal of the comparator 36, one end of the capacitor 34 is connected to a signal line SG L, and the other end is connected to a negative input terminal of the comparator 36, the current source 35 allows a current having a predetermined current value to flow from the signal line SG L to the ground, the comparator 36 compares an input voltage at the positive input terminal with an input voltage at the negative input terminal, and outputs the comparison result as a signal CMP, the comparator 36 has a positive input terminal supplied with the reference signal REF through the capacitor 33 and a negative input terminal supplied with the signal SIG through the capacitor 34, the comparator 36 also has a function of performing zeroing, which makes the positive input terminal and the negative input terminal electrically connected for a predetermined period before a P-phase period TP, the comparator 37 performs counting based on the signal supplied from the comparator 36 and a clock signal C L K and a control signal CC supplied from the readout controller 31, the counter 38 holds a digital CODE counter 38 as a digital CODE counter 37.

Each switch SW supplies the digital CODE output from the AD converter ADC to the bus wiring 100 based on the control signal SSW supplied from the controller 40. The plurality of switches SW are provided in association with the plurality of AD converters ADC. Specifically, the 0 th switch SW [0] is provided in association with the 0 th AD converter ADC [0], the 1 st switch SW [1] is provided in association with the 1 st AD converter ADC [1], and the 2 nd switch SW [2] is provided in association with the 2 nd AD converter ADC [2 ].

In this example, each switch SW includes the same number of transistors as the number of bits of the digital CODE. These transistors are controlled to be turned on and off based on respective bits of control signals SSW (control signals SSW [0], SSW [1], SSW [2], … …) supplied from the controller 40. Specifically, for example, turning on the respective transistors based on the control signal SSW [0] causes the 0 th switch SW [0] to supply the digital CODE output from the 0 th AD converter ADC [0] to the bus wiring 100. Similarly, for example, turning on the respective transistors based on the control signal SSW [1] causes the 1 st switch SW [1] to supply the digital CODE output from the 1 st AD converter ADC [1] to the bus wiring 100. The same applies to the other switches SW.

The bus wiring 100 includes a plurality of wirings, and transmits the digital CODE output from the AD converter ADC. The readout section 30 sequentially transmits the plurality of digital CODEs CODE supplied from the AD converter ADC to the controller 40 as the image signal DATA0 using the bus wiring 100 (DATA transmission operation).

The controller 40 (fig. 1) supplies control signals to the scanning units 20L and 20R and the readout section 30 to control the operation of the image pickup apparatus 1 the controller 40 includes an address generating section 41, a voltage generating section 42, a column scanning section 43, an image processing section 44, and a diagnostic processing section 45.

The address generating section 41 determines the pixel line L to be driven in the pixel array 10, and generates the address signal ADR indicating an address corresponding to the pixel line L, then, the address generating section 41 supplies the generated address signal ADR to the address decoder 21L of the scanning unit 20L and the address decoder 21R of the scanning unit 20R.

The voltage generating section 42 generates the voltage signal SVR and the power supply voltage VDD the voltage signal SVR is a signal varying between the predetermined voltage VR and the power supply voltage VDD in a period in which both the transistors TG and RST are turned on, the voltage signal SVR is set to the power supply voltage VDD, and in a D-phase period TD, the voltage signal SVR is set to the voltage VR. then the voltage generating section 42 supplies the generated voltage signal SVR to the plurality of voltage supply lines V L0 in the pixel array 10 and supplies the generated power supply voltage VDD to the plurality of power supply lines P L in the pixel array 10.

The column scanning section 43 determines the AD converter ADC to be subjected to the data transfer operation in the readout section 30, and generates the control signal SSW based on the determination result. Then, the column scanning section 43 supplies the generated control signal SSW to the plurality of switches SW of the readout section 30.

The image processing section 44 performs predetermined image processing on the image indicated by the image signal DATA 0. Examples of the predetermined image processing include a dark current correction process of subtracting a contribution part of the dark current of the photodiode PD from the digital CODE included in the image signal DATA 0. Specifically, the image processing section 44 corrects the digital CODE of the pixel P1 based on the digital CODE of the light-shielded pixel P2, thereby performing the dark current correction process. The image processing section 44 performs such predetermined image processing to output an image signal DATA indicating an image on which the image processing has been performed.

The diagnostic processing section 45 performs diagnostic processing based on the address signal ADR and the image signal DATA0 specifically, the diagnostic processing section 45 obtains line identification information INF L based on the digital CODE of the virtual pixel P3 included in the image signal DATA0, and compares the address indicated by the address signal ADR with the line identification information INF L to diagnose whether the image pickup apparatus 1 is performing a desired operation or not, then, the diagnostic processing section 45 outputs the result of the diagnostic processing (diagnostic result RES).

Next, embodiments of the image pickup apparatus 1 are described with reference to some examples.

Fig. 7 illustrates an embodiment E1 of the image pickup apparatus 1 in this embodiment E1, the image pickup apparatus 1 is formed as one semiconductor chip 200, the pixel array 10 is arranged near the center of the semiconductor chip 200, the scanning unit 20L is arranged on the left side of the pixel array 10, and the scanning unit 20R is arranged on the right side of the pixel array 10, the readout section 30 and the column scanning section 43 of the controller 40 are arranged below the pixel array 10, above the pixel array 10, a control unit 40A is formed, the control unit 40A corresponding to a circuit other than the column scanning section 43 of the controller 40.

In this configuration, the address generating section 41 in the control unit 40A supplies the address signal ADR to the scanning units 20L and 20R, the scanning units 20L and 20R supply the control signals STG, SRST, and SSE L to the pixel array 10, the voltage generating section 42 in the control unit 40A supplies the voltage signal SVR and the power supply voltage VDD to the pixel array 10, the pixel array 10 supplies the signal SIG to the readout section 30, the readout section 30 supplies the image signal DATA0 to the image processing section 44 and the diagnostic processing section 45 in the control unit 40A, the image pickup apparatus 1 performs diagnostic processing, which allows the image pickup apparatus 1 to detect, for example, an operation failure of each circuit or a connection failure such as an open or short of various wirings in the semiconductor chip 200.

Fig. 8 illustrates another embodiment E2 of the image pickup apparatus 1. In this embodiment E2, the image pickup device 1 is formed as two semiconductor chips 201 and 202.

In this example, a pixel array 10 is formed in a semiconductor Chip 201, that is, a plurality of pixels P1, a plurality of light-shielded pixels P2, a plurality of dummy pixels P3, control lines TG L, RST L and SE L L1, a power supply line P L, a voltage supply line V L and a signal line SG L are formed in the semiconductor Chip 201, further, electrode regions 201A, 201B and 201C are provided in the semiconductor Chip 201, the electrode region 201A is provided near the left side of the semiconductor Chip 201, the electrode region 201B is provided near the right side of the semiconductor Chip 201, and the electrode region 201C is provided near the lower side of the semiconductor Chip 201. a plurality of electrodes are formed in the electrode region 201A and are connected to the control lines L, L and SE L RST 633, RST 63p 29 and the voltage V5960 in the pixel array 10, for example, Through a plurality of Through-Via holes such as Through-Via-holes (TCV) to the control lines TG 638, the power supply line P638 and the signal line TG L in the semiconductor Chip 201 and the electrode region 201.

In this example, the scan cells 20L and 20R, the control cell 40A, the column scan section 43, and the readout section 30 are formed in the semiconductor chip 202. the control cell 40A, the column scan section 43, and the readout section 30 are arranged near the center of the semiconductor chip 202. the scan cell 20L is arranged to the left of the control cell 40A, the column scan section 43, and the readout section 30, and the scan cell 20R is arranged to the right of the control cell 40A, the column scan section 43, and the readout section 30. furthermore, electrode regions 202A, 202B, and 202C are provided in the semiconductor chip 202 adjacent to the scan cell 20L. the electrode region 202A is provided to the left of the semiconductor chip 202 adjacent to the readout section 20R. the electrode region 202C is provided to the right of the semiconductor chip 202 adjacent to the readout section 30. A plurality of electrodes are formed in the electrode region 202A and connected to the control cell 20, e.g., via TCV electrodes 20 and readout section 30. A and TCV electrodes are connected to the control cell 20, e.g., via the control cell 20A and readout section 30.

In this embodiment E2, the semiconductor chip 201 and the semiconductor chip 202 are bonded to each other. This electrically connects the plurality of electrodes in the electrode region 201A of the semiconductor chip 201 to the plurality of electrodes in the electrode region 202A of the semiconductor chip 202, electrically connects the plurality of electrodes in the electrode region 201B of the semiconductor chip 201 to the plurality of electrodes in the electrode region 202B of the semiconductor chip 202, and electrically connects the plurality of electrodes in the electrode region 201C of the semiconductor chip 201 to the plurality of electrodes in the electrode region 202C of the semiconductor chip 202.

In this configuration, the address generating section 41 in the control unit 40A of the semiconductor chip 202 supplies the address signal ADR to the scanning units 20L and 20R the scanning units 20L and 20R of the semiconductor chip 202 supply the control signals STG, SRST, and SSE L to the pixel array 10 of the semiconductor chip 201 through the plurality of electrodes in the respective electrode regions 201A and 202A and the plurality of electrodes in the respective electrode regions 201B and 202B the voltage generating section 42 in the control unit 40A of the semiconductor chip 202 supplies the voltage signal SVR and the power supply voltage VDD to the pixel array 10 of the semiconductor chip 201 through the plurality of electrodes in the respective electrode regions 201A and 202A and the plurality of electrodes in the respective electrode regions 201B and 202B the pixel array 10 of the semiconductor chip 201 supplies the signal SIG to the readout section 30 of the semiconductor chip 202 through the plurality of electrodes in the respective electrode regions 201C and 201C in the semiconductor chip 202, the readout section 30 supplies the image signal DATA0 to the wiring processing section 44 in the control unit 40A and the semiconductor chip 202, or the semiconductor chip 202 performs the diagnostic operation such as the open circuit or short-fault detection of the semiconductor chip 201, the semiconductor chip 202.

Further, arranging the pixel array 10 mainly in the semiconductor chip 201 in this way makes it possible to manufacture the semiconductor chip 201 by using a semiconductor manufacturing process dedicated to pixels. That is, the semiconductor chip 201 does not include a transistor, but includes the pixel array 10. Therefore, for example, even in the case where the annealing process is performed at 1000 degrees celsius, the circuits other than the pixel array 10 are not affected. Therefore, in the manufacture of the semiconductor chip 201, high-temperature processing, for example, can be introduced as a measure against white spots, and as a result, the characteristics of the imaging apparatus 1 can be improved.

Here, the terminal T1 corresponds to a specific example of the "first terminal" in the present invention, the terminal T2 corresponds to a specific example of the "second terminal" in the present invention, the terminal T3 corresponds to a specific example of the "third terminal" in the present invention, the floating diffusion FD corresponds to a specific example of the "accumulation unit" in the present invention, the transistor TG corresponds to a specific example of the "first transistor" in the present invention, the transistor RST corresponds to a specific example of the "second transistor" in the present invention, the transistors AMP and SE L correspond to a specific example of the "output unit" in the present invention, the pixel circuit CKT of the virtual pixel P3B corresponds to a specific example of the "first pixel circuit" in the present invention, the pixel circuit CKT of the virtual pixel P3A corresponds to a specific example of the "second pixel circuit" in the present invention, the pixel circuit CKT of the pixel P8 corresponds to a specific example of the "third pixel circuit" in the present invention, the pixel circuit CKT of the virtual pixel P3 corresponds to a specific example of the "third pixel circuit" in the present invention, the pixel circuit ckr 4628, the "and the pixel circuit sw 4128 corresponds to the specific example of the pixel circuit of the" fifth pixel circuit sw 469 "diagnostic circuit of the present invention, the" fifth pixel circuit of the "diagnostic circuit" test circuit "in the present invention, the present invention corresponds to the pixel circuit" test.

[ operation and Effect ]

Next, the operation and action of the image pickup apparatus 1 according to the present embodiment are described.

(overview of the Integrated operation)

First, an overview of the overall operation of the image pickup apparatus 1 is described with reference to fig. 1, an address generating section 41 of the controller 40 determines a pixel line L to be driven in the pixel array 10, and generates an address signal ADR indicating an address corresponding to the pixel line L, two scanning units 20L and 20R sequentially drive a pixel P1, a light-shielded pixel P2, and a virtual pixel P3 in the pixel array 10 in units of a pixel line L, respectively, based on an instruction from the controller 40, a voltage generating section 42 of the controller 40 generates a voltage signal SVR and a power supply voltage vdd, the pixel array 10 supplies a signal SIG to the readout section 30, an AD converter ADC of the readout section 30 performs AD conversion based on the signal SIG to generate a digital CODE to be subjected to a DATA transfer operation, a column scanning section 43 of the controller 40 determines a digital CODE ADC to be subjected to a DATA transfer operation, and a switch SW of the readout section 30 generates a control signal SSW based on the determination result, the control signal SSW supplies the digital CODE to the bus line 100 wiring, the readout section 30 generates a DATA signal DATA processing signal representative of the image DATA processing section 40, and the image DATA processing section 40 outputs the image DATA processing signal ADR 64 based on the control signal SSW.

(detailed operation)

In the image pickup apparatus 1, the plurality of pixels P1 in the normal pixel region R1 accumulate electric charges according to the light receiving amount, respectively, and output a pixel voltage Vpix corresponding to the light receiving amount as a signal SIG. This operation is described in detail below.

Fig. 9 illustrates an example of an operation of scanning the pixels P1 in the normal pixel region R1 fig. 10 illustrates an operation example (a) of the image pickup apparatus 1 illustrates waveforms of the horizontal synchronization signal XHS (B) to (D) illustrate waveforms of the control signals SRST [0], STG [0] and SSE L [0] in the control lines RST L [0], TG L [0] and SE L [0], respectively, the control lines RST L [0], TG L [0] and SE L [0] correspond to the control signals SRST [0], TG L [0] and SE 584 [0] in the 0-th pixel line L [0] (E) to (G) illustrate waveforms of the control signals RST L [1], STG [1] and SSE L [1] in the control lines RST L [0], TG L [1] and SE L [1], respectively, and the control signals RST 592 [1], RST LL [1] and RST 869 [1] correspond to the control signals SRST [1], RST L [ 862 ] and the control signals [ 863 ] L [0] and st [0] and SE L [0] and st [0] and SE 367 [0 ].

As shown in fig. 9, the image pickup apparatus 1 performs accumulation start driving D1 on the pixels P1 in the normal pixel region R1 in order from the top in the vertical direction during the period from the time t0 to the time t 1.

Specifically, for example, as shown in fig. 10, in the horizontal period H from the time t21, the voltage generating section 42 first changes the voltage of the voltage signal SVR from the voltage VR to the power supply voltage VDD ((K) of fig. 10) at a time t21 next, the scanning units 20L and 20R change the voltage of the control signal SRST [0] from the low level to the high level at a time t22 ((B) of fig. 10), and change the voltage of the control signal STG [0] from the low level to the high level at a time t23 ((C) of fig. 10), which turns on both the transistors TG and the diffusion section in the pixel P1 belonging to the 0 th pixel line L [0], and sets the voltage of the floating diffusion section FD and the voltage of the cathode of the photodiode PD to the power supply voltage VDD, then, the scanning units 20L and 20R change the voltage of the control signal STG [0] from the high level to the low level at a time t1 of fig. 10, which turns off the voltage of the pixel P62 is changed from the voltage of the pixel P9 to the high level at a time t L, and the voltage of the scanning unit 20R generates the charge accumulation signal SRST [ 42 ] from the pixel accumulation start time t 630, which is changed to the pixel accumulation period t L, which is started at a time t 633, and the pixel voltage of the pixel accumulation period t L, which is changed to the pixel P in accordance with the pixel accumulation control signal SRST 633, which is changed to the pixel voltage of the pixel P L.

In the horizontal period H from the time t21, the light-shielded pixels P2 and the dummy pixels P3 belonging to the 0 th pixel line L [0] are driven similarly to the pixels P1 belonging to the pixel line L [0 ]. that is, the pixels P1, the light-shielded pixels P2, and the dummy pixels P3 belonging to the pixel line L [0] are connected to the same control line TG L, the same control line RST L, and the same control line SE LL, and are thus driven similarly.

In the light-shielded pixel P2 belonging to this pixel line L [0], both the transistors TG and RST are turned on in a period from time t23 to time 24, and the voltage of the floating diffusion FD and the voltage of the cathode of the photodiode PD are set to the power supply voltage vdd.

Further, the dummy pixel P3 belonging to this pixel line L [0] does not include the photodiode PD, and therefore the operation of the dummy pixel P3 is slightly different from the operation of the pixel P1 and the light-shielded pixel P2 in the dummy pixel P3A, as shown in fig. 3A, the source of the transistor TG is connected to the power supply line P L, and therefore, when both the transistor TG and the RST are turned on in a period from time t23 to time t24, the voltage of the floating diffusion FD is set to the power supply voltage VDD. furthermore, in the dummy pixel P3B, as shown in fig. 3B, the source of the transistor TG is connected to the voltage supply line V L0, and therefore, when both the transistor TG and the RST are turned on, the voltage of the floating diffusion FD is set to the power supply voltage VDD, that is, as shown in fig. 10 (K), the voltage of the voltage signal SVR in the voltage V L is set to the power supply line VDD in a period from time t23 to time t24, and therefore, the voltage of the floating diffusion FD 890 that is set to the floating voltage of the power supply line V L, which is possible to reduce the possibility of a large current flowing from the power supply.

Similarly, in the horizontal period H from the time t27, the pixels P1 belonging to the 1 st pixel line L [1] start accumulating electric charges according to the light receiving amount, and in the horizontal period H from the time t28, the pixels P1 belonging to the 2 nd pixel line L [2] start accumulating electric charges according to the light receiving amount.

The image pickup apparatus 1 performs the accumulation start drive D1 in this manner to sequentially cause the pixels P1 to start accumulating electric charges. Then, in each pixel P1, before the readout drive D2 is performed, the electric charge is accumulated within the accumulation period T10.

Then, as shown in fig. 9, the image pickup apparatus 1 performs the readout driving D2 on the pixels P1 in the normal pixel region R1 in order from the top in the vertical direction in the period from the time t10 to the time t 11.

Specifically, for example, as shown in fig. 10, in a horizontal period H starting from a time T31, the voltage generating section 42 first changes the voltage of the voltage signal SVR from the voltage VR to the power supply voltage VDD ((K) of fig. 10) at a time T31, next, the scanning units 20L and 20R then change the voltage of the control signal SSE L [0] from the low level to the high level at a time T32 ((D) of fig. 10), which sets the voltage of the control signal SRST [0] to the high level in the pixel P1 belonging to the 0 th pixel line L [0], and electrically connects the pixel P1 to the readout section 30, next, the scanning units 20L and 20R set the voltage of the control signal SRST [0] to the high level in a period from a time T33 to a time T34 ((B) of fig. 10) in the pixel P1, the transistor is turned on, the floating diffusion section is supplied with the power supply voltage RST FD, and the floating diffusion section is reset signal SIG is reset by the floating transistor SIG generating section L, which is turned on, then, reset the pixel P generating section L, which is reset the pixel P L, which is reset signal SIG from the pixel P36p L to the pixel P36p voltage of the pixel P L, which is read out at a high level after the pixel voltage of the pixel P36p 360, which is read out as the pixel voltage of the pixel FD, which is read-FD, the pixel P voltage of the pixel P L, which is read-FD, and reset signal FD, which is read out from the pixel P voltage of the pixel P L (after the pixel FD, the pixel FD & gt-FD & gt L, the pixel FD & gt-reset signal FD & gt-reset signal-FD & gt voltage under the pixel voltage-FD & gt-reset operation-reset signal-reset operation under the pixel voltage-reset-FD & gt voltage-reset mode (after the pixel voltage-FD & gt voltage under the pixel voltage-FD & gt voltage.

In the horizontal period H from the time t31, the light-shielded pixels P2 and the virtual pixels P3 belonging to the 0 th pixel line L [0] are driven similarly to the pixels P1 belonging to the pixel line L [0 ].

The light-shielded pixel P2 belonging to the pixel line L [0] outputs the reset voltage Vreset as a signal SIG in the P-phase period TP and outputs the pixel voltage Vpix as a signal SIG in the D-phase period TD in the light-shielded pixel P2, light is shielded from entering the photodiode PD, and thus the pixel voltage Vpix is a voltage corresponding to a dark current.

Further, the dummy pixel P3 belonging to this pixel line L [0] does not include the photodiode PD, and therefore the operation of the dummy pixel P3 is slightly different from the operation of the pixel P1 and the light-shielded pixel P2 as shown in fig. 3A, the source of the transistor TG of the dummy pixel P3A is connected to the power supply line P L, and therefore, the dummy pixel P3A outputs the reset voltage Vreset as the signal SIG in the P-phase period TP and outputs the voltage corresponding to the power supply voltage VDD as the signal SIG in the D-phase period TD, and further, as shown in fig. 3B, the source of the transistor TG of the dummy pixel P3B is connected to the voltage supply line V L0, and therefore, the dummy pixel P3B outputs the reset voltage Vreset as the signal SIG in the P-phase period TP and outputs the voltage corresponding to the voltage VR as the signal SIG in the D-phase period TD.

Similarly, in the horizontal period H from the time t37, the pixels P1 belonging to the 1 st pixel line L [1] output the signal SIG, and the readout section 30 performs AD conversion based on the signal SIG, thereby generating the digital CODE-furthermore, in the horizontal period H from the time t38, the pixels P1 belonging to the 2 nd pixel line L [2] output the signal SIG, and the readout section 30 performs AD conversion based on the signal SIG, thereby generating the digital CODE.

In this way, the image pickup apparatus 1 performs the readout driving D2, thereby sequentially performing AD conversion based on the signal SIG (reset voltage Vreset and pixel voltage Vpix) output from the pixel P1 to generate the digital CODE.

The imaging device 1 repeats such accumulation start driving D1 and readout driving D2. Specifically, as shown in fig. 9, the image pickup apparatus 1 performs the accumulation start drive D1 in the period from the time t2 to the time t3, and performs the readout drive D2 in the period from the time t12 to the time t 13. Further, the image pickup apparatus 1 executes the accumulation start drive D1 in the period from the time t4 to the time t5, and executes the readout drive D2 in the period from the time t14 to the time t 15.

Next, the readout driving D2 is described in detail.

Fig. 11 illustrates an operation example of the readout driving D2 in the pixel P1 of interest, (a) illustrates a waveform of the horizontal synchronization signal XHS, (B) illustrates a waveform of the control signal SRST, (C) illustrates a waveform of the control signal STG, (D) illustrates a waveform of the control signal SSE L, (E) illustrates a waveform of the reference signal REF, (F) illustrates a waveform of the signal SIG, (G) illustrates a waveform of the signal CMP output from the comparator 36 of the AD converter ADC, (H) illustrates a waveform of the clock signal C L K, (I) illustrates a count value cnt of the counter 37 of the AD converter ADC here, in fig. 11(E) and (F), the waveforms of the respective signals are plotted on the same axis, a reference signal REF in fig. 11(E) represents a waveform at the positive input terminal of the comparator 36, and a signal SIG in fig. 11(F) represents a negative input waveform of the comparator 36 at the input terminal of the comparator 36.

In the image pickup apparatus 1, first, in a certain horizontal period (H), each of the scanning units 20L and 20R performs a reset operation on the pixel P1, and in the subsequent P-phase period TP, the AD converter ADC performs AD conversion based on the reset voltage Vreset output from the pixel P1, then each of the scanning units 20L and 20R performs a charge transfer operation on the pixel P1, and in the D-phase period TD, the AD converter ADC performs AD conversion based on the pixel voltage Vpix output from the pixel P1.

First, the horizontal period H starts at a time t41, and then each of the scan cells 20L and 20R changes the voltage of the control signal SSE L from the low level to the high level at a time t42 (fig. 11 (D)). this turns on the transistor SE L in the pixel P1. the pixel P1 is electrically connected to the signal line SG L.

Next, at time t43, each of the scan cells 20L and 20R changes the voltage of the control signal SRST from a low level to a high level (fig. 11 (B)). this turns on the transistor RST in the pixel P1 and sets the voltage of the floating diffusion FD to the power supply voltage VDD (reset operation). further, in a period from time t43 to time t45, the comparator 36 performs zeroing, which connects the positive input terminal and the negative input terminal.

Next, at a time t44, each of the scan cells 20L and 20R changes the voltage of the control signal SRST from a high level to a low level (fig. 11 (B)). this turns off the transistor RST in the pixel P1 from then, from this time t44, the pixel P1 outputs a voltage (reset voltage Vreset) corresponding to the voltage of the floating diffusion FD at that time (fig. 11 (F)).

Next, at time t45, comparator 36 terminates the zeroing and electrically disconnects the positive and negative input terminals. Then, at this time t45, the reference signal generator 32 changes the voltage of the reference signal REF to the voltage V1 (fig. 11 (E)).

Next, in the period from the time t46 to the time t48 (P-phase period TP), the readout section 30 performs AD conversion based on the reset voltage Vreset, specifically, first, at the time t46, the readout controller 31 starts generating the clock signal C L K (fig. 11 (H)). at the same time, the reference signal generator 32 starts decreasing the voltage of the reference signal REF from the voltage V1 at a predetermined rate of change (fig. 11 (E)). accordingly, the counter 37 of the AD converter ADC starts a counting operation, thereby sequentially changing the CNT count value (fig. 11(I))

Then, at time t47, the voltage of the reference signal REF drops below the voltage of the signal SIG (reset Vreset) (fig. 11(E) and (F)). Therefore, the comparator 36 of the AD converter ADC changes the voltage of the signal CMP from the high level to the low level (fig. 11 (G)). As a result, the counter 37 stops the counting operation (fig. 11 (I)).

Next, at time t48, the readout controller 31 stops generating the clock signal C L K (fig. 11(H)) at the end of the P-phase period TP, along with which the reference signal generator 32 stops changing the voltage of the reference signal REF, and at subsequent time t49, changes the voltage of the reference signal REF to the voltage V2 (fig. 11 (E)). accordingly, the voltage of the reference signal REF exceeds the voltage of the signal SIG (reset voltage Vreset) (fig. 11(E) and (F)), and therefore, the comparator 36 of the AD converter ADC changes the voltage of the signal CMP from the low level to the high level (fig. 11 (G)).

Next, at time t50, the counter 37 of the AD converter ADC inverts the polarity of the count value CNT based on the control signal CC (fig. 11 (I)).

Next, at time t51, each of the scanning units 20L and 20R changes the voltage of the control signal STG from a low level to a high level (fig. 11 (C)). this turns on the transistor TG in this pixel P1. as a result, the electric charges generated in the photodiode PD are transferred to the floating diffusion FD (electric charge transfer operation). accordingly, the voltage of the signal SIG decreases (fig. 11 (F)).

Then, at a time t52, each of the scan cells 20L and 20R changes the voltage of the control signal STG from a high level to a low level (fig. 11 (C)). this turns off the transistor TG in the pixel P1 from then, from this time t52, the pixel P1 outputs a voltage (pixel voltage Vpix) corresponding to the voltage of the floating diffusion FD at that time (fig. 11 (F)).

Next, in the period from the time t53 to the time t55 (D-phase period TD), the readout section 30 performs AD conversion based on the pixel voltage Vpix, specifically, first, at the time t53, the readout controller 31 starts generating the clock signal C L K (fig. 11 (H)). at the same time, the reference signal generator 32 starts lowering the voltage of the reference signal REF from the voltage V2 at a predetermined rate of change (fig. 11 (E)). accordingly, the counter 37 of the AD converter ADC starts a counting operation, thereby sequentially changing the CNT count value (fig. 11 (I)).

Then, at time t54, the voltage of the reference signal REF drops below the voltage of the signal SIG (pixel voltage Vpix) (fig. 11(E) and (F)). Therefore, the comparator 36 of the AD converter ADC changes the voltage of the signal CMP from the high level to the low level (fig. 11 (G)). As a result, the counter 37 stops the counting operation (fig. 11 (I)). In this way, the AD converter ADC obtains the count value CNT corresponding to the difference between the pixel voltage Vpix and the reset voltage Vreset. Then, the latch 38 of the AD converter ADC outputs the count value CNT while holding the count value CNT as the digital CODE.

Next, at time t55, the readout controller 31 stops generating the clock signal C L K (fig. 11(H)) at the end of the D-phase period TD, along with which the reference signal generator 32 stops changing the voltage of the reference signal REF, and at subsequent time t56 changes the voltage of the reference signal REF to the voltage V3 (fig. 11E)), and therefore, the voltage of the reference signal REF exceeds the voltage of the signal SIG (the pixel voltage Vpix) (fig. 11(E) and (F)), and therefore, the comparator 36 of the AD converter ADC changes the voltage of the signal CMP from the low level to the high level (fig. 11 (G)).

Next, at time t57, each of the scan cells 20L and 20R changes the voltage of the control signal SSE L from the high level to the low level (fig. 11 (D)). this turns off the transistor SE L in the pixel P1, and electrically disconnects the pixel P1 from the signal line SG L.

Then, at time t58, the counter 37 of the AD converter ADC resets the count value CNT to "0" based on the control signal CC (fig. 11 (I)).

As described above, in the image pickup apparatus 1, the counting operation is performed based on the reset voltage Vreset in the P-phase period TP, and after the polarity of the count value CTN is inverted, the counting operation is performed based on the pixel voltage Vpix in the D-phase period TD. This allows the image pickup apparatus 1 to acquire the digital CODE corresponding to the voltage difference between the pixel voltage Vpix and the reset voltage Vreset. In the image pickup apparatus 1, such correlated double sampling is performed, and thus a noise component included in the pixel voltage Vpix can be removed. As a result, the image quality of the captured image can be improved.

The readout section 30 supplies the digital CODEs CODE output from the plurality of AD converters ADC to the image processing section 44 of the controller 40 as the image signal DATA0 through the bus wiring 100. Next, the data transfer operation is described in detail.

Fig. 12 schematically illustrates an example of a data transfer operation of the readout section 30. In fig. 12, thick lines indicate bus lines for a plurality of bits. In fig. 12, for example, "0" in the AD converter ADC represents the 0 th AD converter ADC [0], and "1" represents the 1 st AD converter ADC [1 ].

The column scanning section 43 generates a control signal SSW to cause the plurality of AD converters ADC of the readout section 30 to sequentially perform a data transfer operation. For each bit of control signal SSW, control signal SSW [0], control signal SSW [1], control signal SSW [2], … … are asserted in this order, for example. This first supplies the digital CODE of the 0 th AD converter ADC [0] to the bus wiring 100 in the readout section 30, and then supplies the digital CODE of the 1 st AD converter ADC [1] to the bus wiring 100. Next, the digital CODE of the 2 nd AD converter ADC [2] is supplied to the bus wiring 100. In this way, the digital CODE is transmitted as the image signal DATA0 from the AD converter ADC on the left side to the controller 40 in order (in the transmission order F).

(concerning diagnosis processing)

Next, the diagnosis process of the image pickup apparatus 1 is described in detail.

Fig. 13 schematically illustrates an overall operation example of the diagnosis process of the image pickup apparatus 1. This diagnostic processing is performed in parallel with the normal image capturing operation using the pixels P1 in the normal pixel region R1. The diagnosis unit 49 includes a readout unit 30 and a diagnosis processing unit 45.

The address generating section 41 of the controller 40 first determines the pixel line L to be driven in the pixel array 10 and generates an address signal ADR indicating an address corresponding to the pixel line L, and then, the address generating section 41 supplies the address signal ADR to the scanning units 20L and 20R.

The two scan units 20L and 20R drive the pixels P1, the light-shielded pixels P2, and the dummy pixels P3 belonging to the pixel line L corresponding to the address indicated by the address signal ADR based on an instruction from the controller 40.

The 11 dummy pixels P3 in the dummy pixel region R31 and the 11 dummy pixels P3 in the dummy pixel region R32 of the pixel array 10 generate signals SIG, respectively, and supply the generated signals SIG to the readout section 30. The AD converter ADC of the readout section 30 generates a corresponding digital CODE based on these signals SIG.

Each of the dummy pixels P3 in the dummy pixel regions R31 and R32 is a dummy pixel P3A (fig. 3A) or a dummy pixel P3B (fig. 3B). as shown in fig. 3A, the source of the transistor TG of the dummy pixel P3A is connected to the power supply line P L. therefore, the dummy pixel P3A outputs the reset voltage Vreset as a signal SIG in the P-phase period TP and outputs a voltage corresponding to the power supply voltage VDD as a signal SIG in the D-phase period TD. furthermore, as shown in fig. 3B, the source of the transistor TG of the dummy pixel P3B is connected to the voltage supply line V L0. therefore, the dummy pixel P3B outputs the reset voltage Vreset as a signal SIG in the P-phase period TP and outputs a voltage corresponding to the voltage VR as a signal SIG in the D-phase period TD. the AD converter of the readout section 30 generates a corresponding digital CODE based on these signal SIG.

Fig. 14 illustrates a relationship between the signal SIG and the digital CODE in the virtual pixels P3A and P3B. The dummy pixel P3A outputs a voltage corresponding to the power supply voltage VDD as a signal SIG in the D-phase period TD. This makes the digital CODE converted by the AD converter ADC a CODE close to a zero CODE. Further, the dummy pixel P3B outputs a voltage corresponding to the voltage VR as the signal SIG in the D-phase period TD. In this example, this makes the digital CODE converted by the AD converter ADC a CODE close to a full CODE.

In this way, the plurality of AD converters ADC of the readout section 30 generate digital CODEs CODE, respectively. The column scanning section 43 of the controller 40 generates the control signal SSW to cause the plurality of AD converters ADC of the readout section 30 to sequentially perform the data transfer operation. This causes the readout section 30 to supply the image signal DATA0 to the controller 40. The image signal DATA0 includes 11 digital CODEs for 11 virtual pixels P3 in the virtual pixel region R31 and 11 digital CODEs for 11 virtual pixels P3 in the virtual pixel region R32.

The diagnostic processing section 45 of the controller 40 obtains the line identification information INF L based on the digital CODE of the virtual pixel P3 included in the image signal DATA0, and compares the address indicated by the address signal ADR with the line identification information INF L to diagnose whether the image pickup apparatus 1 is performing a desired operation.

Specifically, the diagnostic processing section 45 first performs binarization processing on each of the 11 digital CODEs of the 11 virtual pixels P3 in the virtual pixel region R31 using a threshold value TH set between zero CODE and full CODE as shown in fig. 14, the digital CODE of the virtual pixel P3A is a CODE close to zero CODE and thus has "0", and the digital CODE of the virtual pixel P3B is a CODE close to full CODE and thus has "1", which causes the diagnostic processing section 45 to obtain a binary number of 11 bits, which is the line identification information INF L shown in fig. 5, and then the diagnostic processing section 45 compares the address indicated by the address signal ADR with the line identification information INF L to diagnose whether the image pickup apparatus 1 is performing a desired operation.

The same applies to the virtual pixel region R32, that is, the diagnostic processing section 45 first performs binarization processing on each of the 11 digital CODEs CODE of the 11 virtual pixels P3 in the virtual pixel region R32 to obtain line identification information INF L then the diagnostic processing section 45 compares the address indicated by the address signal ADR with the line identification information INF L to diagnose whether the image pickup apparatus 1 is performing a desired operation or not, for example, in the case where the address signal ADR indicates the 0 th pixel line L [0], the address indicated by the address signal ADR is "00000000000", in the case where the address signal ADR indicates the 1 st pixel line L [1], the address indicated by the address signal ADR is "00000000001", in the case where the address signal ADR indicates the 2 nd pixel line L [2], the address indicated by the address signal ADR is "00000000010".

For example, in a case where the line identification information INF L acquired from the digital CODE of the virtual pixel region R31 and the address indicated by the address signal ADR match each other and the line identification information INF L acquired from the digital CODE of the virtual pixel region R32 and the address indicated by the address signal ADR match each other, the diagnostic processing section 45 determines that the image pickup apparatus 1 is performing a desired operation.

Further, for example, in the case where the line identification information INF L acquired from the digital CODE of the virtual pixel region R31 and the address indicated by the address signal ADR do not match each other, or in the case where the line identification information INF L acquired from the digital CODE of the virtual pixel region R32 and the address indicated by the address signal ADR do not match each other, the diagnostic processing section 45 determines that the image pickup apparatus 1 has a failure.

For example, a mismatch between the line identification information INF L acquired from the digital CODE of the virtual pixel region R31 and the address indicated by the address signal ADR may be caused by a connection failure between the address generation section 41 and the scanning unit 20L, a failure of the scanning unit 20L, a connection failure between the scanning unit 20L and the virtual pixel P3 in the virtual pixel region R31, a failure of the virtual pixel P3 in the virtual pixel region R31, a connection failure between the virtual pixel P3 in the virtual pixel region R31 and the AD converter ADC, or a failure of the AD converter ADC.

Further, for example, a mismatch between the line identification information INF L acquired from the digital CODE of the virtual pixel region R32 and the address indicated by the address signal ADR may be caused by a connection failure between the address generating section 41 and the scanning unit 20R, a failure of the scanning unit 20R, a connection failure between the scanning unit 20R and the virtual pixel P3 in the virtual pixel region R32, a failure of the virtual pixel P3 in the virtual pixel region R32, a connection failure between the virtual pixel P3 in the virtual pixel region R32 and the AD converter ADC, or a failure of the AD converter ADC.

The diagnostic processing section 45 performs the diagnostic processing in this manner. Then, the diagnosis processing section 45 outputs the result of the diagnosis processing as a diagnosis result RES.

As described above, the image pickup apparatus 1 is provided with the virtual pixel regions R31 and R32 in each pixel line L, the virtual pixel region R31 is provided with a plurality of (11 in this example) virtual pixels P3, and the virtual pixel region R32 is provided with a plurality of (11 in this example) virtual pixels P3 these virtual pixels P3 include the virtual pixel P3A (fig. 3A) or the virtual pixel P3B (fig. 3B) whose sources of the respective transistors TG have different connection destinations, which allows the image pickup apparatus 1 to fix and set information on each pixel line L by using the configuration of the virtual pixel P3 as a so-called mask type Read Only Memory (ROM: Read Only Memory).

In particular, as shown in fig. 5, the image pickup apparatus 1 has 11 virtual pixels P3, these virtual pixels P3 being arranged in an arrangement corresponding to the base number of pixel lines L represented by binary numbers this makes it possible to simplify the configuration of the circuit for comparing the line identification information INF L with the address indicated by the address signal ADR.

Further, the image pickup apparatus 1 is provided with two virtual pixel regions R31 and R32 on the right and left sides of the normal pixel region R1, respectively, in parallel with the normal image pickup operation using the pixels P1 in the normal pixel region R1, for example, this makes it possible to timely detect a failure, that is, for example, in the case where the diagnostic process is performed within the blanking period T20, the blanking period T20 is short, and therefore, it is difficult to perform the diagnostic process on all the pixel lines L within one blanking period T20, and therefore, the diagnostic process is performed on all the pixel lines L by using a plurality of blanking periods T20.

[ Effect ]

In each pixel line L, a plurality of these virtual pixels include two types of pixels whose sources of the respective transistors TG have different connection destinations.

In the present embodiment, the imaging device 1 is provided with two virtual pixel regions on both the right and left sides of the normal pixel region. The diagnostic process is performed in parallel with an ordinary image capturing operation using pixels in an ordinary pixel region. This makes it possible to detect a failure in a timely manner, for example.

[ modified examples 1-1]

In the above-described embodiment, although two scanning units 20L and 20R are provided, this is not restrictive, and instead, as the image pickup apparatus 1B shown in fig. 15, one scanning unit may be provided, the image pickup apparatus 1B includes one scanning unit 20L, a pixel array 10B, a readout section 30B, and a controller 40B, that is, the image pickup apparatus 1B is obtained by removing the scanning unit 20R from the image pickup apparatus 1 (fig. 1) according to the above-described embodiment and replacing the pixel array 10, the readout section 30B, and the controller 40B with the pixel array 10B, the readout section 30B, and the controller 40B, respectively.

The pixel array 10B is obtained by removing the virtual pixel region R31 from the pixel array 10 (fig. 1) according to the above-described embodiment, the readout section 30B performs AD conversion based on the signal SIG supplied from the pixel array 10B through the signal line SG L, thereby generating an image signal data0, the controller 40B supplies a control signal to the scanning unit 20L and the readout section 30B to control the operation of the image pickup apparatus 1B, the controller 40B includes the column scanning section 43B and the diagnostic processing section 45B, the column scanning section 43B determines the AD converter ADC to be subjected to the data transfer operation in the readout section 30B, and generates a control signal ssw based on the determination result, the diagnostic processing section 45B performs binarization processing on each of the 11 digital CODEs CODE of the 11 virtual pixels P3 in the virtual pixel region R32, thereby obtaining line identification information INF L, the diagnostic processing section 45B compares the address indicated by the address signal ADR with the line identification information INF L, thereby diagnosing whether the image pickup apparatus 1 is performing the desired operation.

In the image pickup apparatus 1B, the scanning unit 20L drives, based on an instruction from the controller 40B, 11 dummy pixels P3 in a dummy pixel region R32 belonging to a pixel line L corresponding to an address indicated by the address signal ADR to generate signals SIG, respectively, and supplies the generated signals SIG to the readout section 30B, the scanning unit 20L is arranged on the left side of the pixel array 10B, and the dummy pixel region R32 is provided on the right end of the pixel array 10B, that is, the image pickup apparatus 1B is provided with the dummy pixel region R32 at a position farthest from the scanning unit 20L in the pixel array 10B, and therefore, performs a diagnostic process so that the driving performance of the driving section 23L of the scanning unit 20L can be diagnosed, and further, the image pickup apparatus 1B is provided with the dummy pixel region R32 at a position farthest from the scanning unit 20L in such a manner that the pixel regions PL 32, st 6327, st 638, and the light-shielded pixel regions PL 3527 and the pixel control lines TG L are disconnected from the normal pixel array 10B.

[ modified examples 1 and 2]

In the above embodiment, although the virtual pixel P3 includes any one of the 2 kinds of virtual pixels P3A and P3B, this is not limitative. Instead, for example, any one of 3 or more kinds of virtual pixels may be included. The image pickup apparatus 1C is described in detail below. The virtual pixel P3 of the imaging apparatus 1C includes 4 kinds of virtual pixels P3C, P3D, P3E, and P3F.

Similar to the image pickup apparatus 1 according to the above-described embodiment, the image pickup apparatus 1C includes the pixel array 10C, the readout section 30C, and the controller 40C.

The pixel array 10C includes a plurality of virtual pixels P3 (virtual pixels P3C, P3D, P3E, and P3F). A plurality of virtual pixels P3 are arranged in the virtual pixel regions R31 and R32.

Fig. 16A to 16D illustrate configuration examples of the virtual pixel P3 in each of the virtual pixel regions R31 and R32, respectively fig. 16A illustrates an example of the virtual pixel P3C, fig. 16B illustrates an example of the virtual pixel P3D, fig. 16C illustrates an example of the virtual pixel P3E, fig. 16D illustrates an example of the virtual pixel P3F, the pixel array 10C includes a plurality of voltage supply lines V F to V F3 (described below) in the virtual pixel regions R F and R F the voltage generating section 42C applies a single voltage signal SVR F to the plurality of voltage supply lines V F1, the voltage signal SVR F is a signal that changes between a predetermined voltage SVR F and a power supply voltage VDD, the voltage signal SVR F is set to the voltage vrr 72, the voltage generating section 42C sets the single voltage signal SVR 72 to the voltage generating section 42C when the voltage SVR 72 is lower than the voltage of the VR signal voltage VR voltage V72, the voltage is set to the voltage of the VR signal voltage SVR 72, the voltage of the VR F, the voltage of the VR voltage generating section TD is lower than the voltage of the VR signal SVR F, the VR voltage of the VR voltage generating section F, the VR voltage of the VR F is set to the VR voltage of the VR voltage generating section F, the VR voltage of the VR voltage.

The dummy pixels P3 (dummy pixels P3C to P3F) include pixel circuits ckt, respectively, the sources of the respective transistors TG of the dummy pixels P3C to P3E have different connection destinations, specifically, as shown in fig. 16A, the source of the transistor TG of the dummy pixel P3C is connected to a power supply line P L, as shown in fig. 16B, the source of the transistor TG of the dummy pixel P3D is connected to a voltage supply line V L1, as shown in fig. 16C, the source of the transistor TG of the dummy pixel P3E is connected to a voltage supply line V L2, as shown in fig. 16D, the source of the transistor TG of the dummy pixel P3F is connected to the voltage supply line V L3.

The source of the transistor TG of the dummy pixel P3C is connected to the power supply line P L, and therefore the voltage of the floating diffusion FD is the power supply voltage VDD in the D-phase period TD, which causes the dummy pixel P3C to output a voltage corresponding to the power supply voltage VDD as the signal SIG in the D-phase period TD, furthermore, the source of the transistor TG of the dummy pixel P3D is connected to the voltage supply line V L1, the voltage of the voltage signal SVR1 applied to this voltage supply line V L1 is set to the voltage VR1 in the D-phase period TD, and therefore, the voltage of the floating diffusion FD in the D-phase period TD is the voltage vr1, which causes the dummy pixel P3D to output a voltage corresponding to the voltage VR1 as the signal SIG in the D-phase period TD, similarly, the source of the transistor TG of the dummy pixel P3E is connected to the voltage supply line V L, and therefore, the dummy pixel P3E outputs a voltage corresponding to the voltage of the VR 38 as the voltage SIG in the D-phase period TD, the virtual pixel P3 SIG 3 is connected to the voltage of the virtual pixel P F, and therefore, the source of the dummy pixel P3 is connected to the voltage of the voltage SIG in the D-phase period TG 3, and therefore, the virtual pixel P3 SIG 3 is connected to the virtual.

In this example, the 1 pixel line L includes 6 virtual pixels P3 (virtual pixels P3[5] to P3[0]) in the virtual pixel region R31 each of these virtual pixels P3[5] to P3[0] is any one of the virtual pixel P3C (fig. 16A), the virtual pixel P3D (fig. 16B), the virtual pixel P3E (fig. 16C), and the virtual pixel P3F (fig. 16D).

Fig. 17 illustrates the arrangement of virtual pixels P3C to P3F in the virtual pixel region R31 in fig. 17, "00" represents a virtual pixel P3C, "01" represents a virtual pixel P3D, "10" represents a virtual pixel P3E, and "11" represents a virtual pixel P3f, for example, the 0 th pixel line L [0] has the arrangement of "00", and "00" as a virtual pixel P3, that is, 6 virtual pixels P3[5] to P3[0] are all virtual pixels P3c, the 1 st pixel line L [1] has the arrangement of "00", "3", "00", and "01" as virtual pixels P3, that is, the virtual pixel P3[0] is a virtual pixel P3D, the other virtual pixels P3[5] to P3[1] are virtual pixels P3 "P00", "3600" 3 "and" 3 "are the virtual pixel P3600" 3 "and" 3 "are the virtual pixel lines" 3P 3600 "and" 3 "are the virtual pixel arrangements of the other virtual pixel lines 3600" 3, that are the virtual pixel P3600 "3 and" 3 "3600" 3, that are the virtual pixel P3600 "3 and" 3600 "3" 3600 "3" 3600 "and" 3600 "3" 3600 "3" 3600 "and" 3 "3600" 3 "and" 3600 "3" are the virtual pixel 3 and "3 lines" 3 "3600" 3 and "3600" 3 "3600" 3 "3600" 3 and "3600.

The AD converter ADC of the readout section 30C generates a corresponding digital CODE based on the signal SIG supplied from the pixel array 10C. Then, the readout section 30C supplies the 6 digital CODEs CODE of the 6 virtual pixels P3 in the virtual pixel region R31 and the 6 digital CODEs CODE of the 6 virtual pixels P3 in the virtual pixel region R32 to the controller 40C as the image signal DATA 0.

The diagnostic processing section 45C of the controller 40C obtains the line identification information INF L based on the digital CODE of the virtual pixel P3 included in the image signal DATA0, and compares the address indicated by the address signal ADR with the line identification information INF L to diagnose whether the image pickup apparatus 1C is performing a desired operation.

Fig. 18 illustrates the relationship between the signal SIG and the digital CODE in the virtual pixels P3C to P3F based on the 6 digital CODEs CODE of the 6 virtual pixels P3 in the virtual pixel area R31, the diagnostic processing section 45C first performs conversion into the four CODEs "00", "01", "10", and "11" by using the 3 thresholds TH1 to TH3, each of the 3 thresholds TH1 to TH3 being set between the zero CODE and the full CODE, the digital CODE of the virtual pixel P3C is converted into the CODE "00", the digital CODE of the virtual pixel P3D is converted into the CODE "01", the digital CODE of the virtual pixel P3E is converted into the CODE "10", and the digital CODE of the virtual pixel P3F is converted into the CODE "11", which causes the diagnostic processing section 45C to obtain the line identification information INF 3 illustrated in fig. 17, then the diagnostic processing section 45C compares the address signal with the identification information INF 42 indicating whether the image pickup device is performing the operation as well, and the image pickup device 38r 7371.

[ modified examples 1 to 3]

In the above-described embodiment, although the information indicated by the arrangement of the virtual pixels P3 includes the line identification information INF L, this is not restrictive, for example, as shown in fig. 19, other information may also be included in this example, in addition to the line identification information INF L, the information indicated by the arrangement of the virtual pixels P3 includes the line attribute information INFP of 2 bits indicating the attribute of each pixel line L, this line attribute information INFP may be, for example, information on a color filter of the pixel line L, further, for example, in the case where the pixel size between the pixel lines L is different, the line attribute information INFP may be information on the pixel size, further, for example, in the case where the length of the accumulation period T10 between the pixel lines L is different, the line attribute information INFP may be information on the length of the accumulation period T10.

[ modified examples 1 to 4]

As in embodiment E2 (fig. 8), the image pickup apparatus 1 includes two semiconductor chips 201 and 202 bonded to each other. For example, copper (Cu) wiring is formed on the surface of the semiconductor chip 201, and copper wiring is formed on the surface of the semiconductor chip 202. These copper wirings may be bonded together by so-called Cu — Cu bonding. This configuration is described in detail below.

Fig. 20 illustrates a configuration example of an image pickup device 431 according to the present modification. The image pickup device 431 includes a stack-type semiconductor chip 432 obtained by bonding the first semiconductor chip 426 and the second semiconductor chip 428 together. The pixel array 434 is formed in the first semiconductor chip 426. The logic circuit 455 is formed in the second semiconductor chip 428. The first semiconductor chip 426 corresponds to the semiconductor chip 201, and the second semiconductor chip 428 corresponds to the semiconductor chip 202.

In the first semiconductor chip 426, a semiconductor well 430 is formed on a thinned semiconductor substrate 433, and a pixel array 434 is formed in a region corresponding to the semiconductor well 430. In the pixel array 434, a plurality of pixels are two-dimensionally arranged. The plurality of pixels includes a photodiode PD and a plurality of pixel transistors Tr1 and Tr 2. The photodiodes PD are formed in regions corresponding to the effective pixel array 442 and the optical black region 441 in the pixel array 434. Further, a plurality of MOS transistors are formed on the semiconductor substrate 433. A plurality of MOS transistors are included in a control circuit (not shown) for controlling the pixel array 434. The multilayer wiring layer 437 is formed on the front surface 433a side of the semiconductor substrate 433. The multilayer wiring layer 437 includes the wirings 435 (wirings 435a to 435d) of the first to fourth metal wiring layers M1 to M4 and the connection wiring 436 of the fifth metal wiring layer M5, and the interlayer insulating film 453 is interposed between the wirings 435 and the connection wiring 436. The wiring 435 and the connection wiring 436 are copper (Cu) wirings formed by a dual damascene method. The light shielding film 439 is formed in a region including the optical black region 441 on the rear surface side of the semiconductor substrate 433, and an insulating film 438 is interposed between the light shielding film 439 and the rear surface side of the semiconductor substrate 433. Then, a planarization film 443 is formed on the entire area above, and a color filter 444 and a lens array 445 are formed on this planarization film 443 in an area corresponding to the effective pixel array 442.

In the multilayer wiring layer 437 of the first semiconductor chip 426, the pixel transistor and the wiring 435 are joined to each other through the conductive via 452. Similarly, two wires 435 adjacent to each other in the up-down direction are joined to each other by a conductive via 452. In the multilayer wiring layer 437, the connection wiring 436 of the fifth metal wiring layer M5 is further formed on the bonding surface 440 with the second semiconductor chip 428. The connection wiring 436 is connected to the wiring 435d1 of the fourth metal wiring layer M4 through the conductive via 452.

In the second semiconductor chip 428, a semiconductor well 450 is formed on a second semiconductor substrate 454, and a logic circuit 455 serving as a peripheral circuit is formed in a region corresponding to the semiconductor well 450. The logic circuit 455 includes a plurality of MOS transistors Tr11 to Tr14 having CMOS transistors. The multilayer wiring layer 459 is formed on the front surface side of the second semiconductor substrate 454. The multilayer wiring layer 459 includes the wiring 457 (wiring 457a to 457c) of the first to third metal wiring layers M11 to M13 and the connection wiring 458 of the fourth metal wiring layer M14, and the interlayer insulating film 456 is interposed between the wiring 457 and the connection wiring 458. The wiring 457 and the connection wiring 458 are copper (Cu) wirings formed by a dual damascene method.

In the multilayer wiring layer 459 of the second semiconductor chip 428, the MOS transistors Tr11 to Tr14 and the wiring 457 are joined to each other through the conductive via 464. Two wirings 457 adjacent to each other in the up-down direction are joined to each other through the conductive via 464. In the multilayer wiring layer 459, the connection wiring 458 of the fourth metal wiring layer M14 is further formed on the bonding surface 440 with the first semiconductor chip 426. The connection wiring 458 is connected to the wiring 457c of the third metal wiring layer M13 through the conductive via 464.

The first semiconductor chip 426 and the second semiconductor chip 428 are bonded together so that the multilayer wiring layer 437 and the multilayer wiring layer 459 face each other. The connection wiring 436 and the connection wiring 458 are electrically connected by being directly bonded together via the bonding surface 440. The connection wirings 436 and 458, which are copper (Cu) wirings, are bonded together by thermal diffusion bonding. Further, an insulating film (not shown) may be formed on respective surfaces of the multilayer wiring layer 437 and the multilayer wiring layer 459 to join the connection wirings 436 and 458 together by plasma bonding or the like. The direct bonding of these connection wirings 436 and 458 as copper (Cu) wirings is Cu — Cu bonding.

[ modified examples 1 to 5]

Although the image pickup apparatus 1 includes the two semiconductor chips 201 and 202 bonded to each other as in embodiment E2 (fig. 8), this is not limitative. The image pickup apparatus 1 may include three stacked semiconductor chips (a first semiconductor chip 501, a second semiconductor chip 502, and a third semiconductor chip 503).

For example, the first semiconductor chip 501 may correspond to the semiconductor chip 201, and the third semiconductor chip 503 may correspond to the semiconductor chip 202. For example, a Dynamic Random Access Memory (DRAM) may be formed in the second semiconductor chip 502. The DRAM stores a photographed image (image signal DATA). In this case, the signal SIG output from the pixel array 511 of the first semiconductor chip 501 is directly supplied to the AD converter of the third semiconductor chip 503. Therefore, for example, as shown in fig. 21, a Through electrode 512 such as a Through Silicon Via (TSV) may be used for the connection, for example. The through electrode 512 is connected to a contact of the first semiconductor chip 501, and is connected to an aluminum pad of the third semiconductor chip 503.

Further, for example, a comparator included in an AD converter may be formed in the second semiconductor chip 502, and a counter included in the AD converter may be formed in the third semiconductor chip 503. In this case, the signal SIG output from the pixel array 511 of the first semiconductor chip 501 is supplied to the comparator of the second semiconductor chip 502, and the output signal of the comparator is supplied to the counter of the third semiconductor chip 403. Therefore, as shown in fig. 22, a through electrode 512a such as a TSV may be used for connection between the first semiconductor chip 501 and the second semiconductor chip 502. Similarly, a through electrode 512c such as a TSV may be used for connection between the second semiconductor chip 502 and the third semiconductor chip 503.

[ modified examples 1 to 6]

A wafer level Chip Size Package (WCSP) can be applied to the imaging device 1 according to the present embodiment. The present modification is described in detail below.

Fig. 23 schematically illustrates a configuration example of an image pickup apparatus 801 according to the present modification. The image pickup apparatus 801 includes: a stacked structure 853 in which a first structure 851 and a second structure 852 are stacked; a plurality of external terminals 854; and a protective substrate 858 formed over the first structure 851. It is to be noted that the first structure 851 corresponds to the semiconductor chip 201, and the second structure 852 corresponds to the semiconductor chip 202. A color filter 855 and an on-chip lens 856 are formed on the light incident surface of the first structure 851. Then, a protective substrate 858 is disposed on the on-chip lens 856, and a glass sealing resin 857 is interposed between the protective substrate 858 and the on-chip lens 856. The external terminal 854 is an input/output terminal for exchanging signals with an external circuit of the image pickup device 801, and includes, for example, a solder ball.

Fig. 24 illustrates a circuit configuration example of the image pickup apparatus 801. A pixel array 864 including a plurality of pixels 871 is formed in the first structure 851.

The scanning unit 862 among the pixel peripheral circuit section of the image pickup apparatus 801 is arranged in the first structure 851 and the second structure 852. For example, a driving section of the scanning unit 862 is arranged in the first structure 851, and an address decoder is arranged in the second structure 852. The scanning unit 862 arranged in the first structure 851 is arranged outside the pixel array 864 in the row direction (lateral direction), and at least a part of the scanning unit 862 arranged in the second structure 852 is arranged on the lower layer side of the scanning unit 862 in the first structure 851. The wiring connection unit 869 is arranged outside the scanning unit 862 arranged in the first structure 851 and outside the scanning unit 862 arranged in the second structure 852. The wiring connection unit 869 connects the two scanning units 862 to each other.

A readout section 865 among pixel peripheral circuit sections included in the image pickup device 801 is arranged in the first structure 851 and the second structure 852. For example, the current source and the comparator of the readout section 865 are arranged in the first structure 851, and the counter and the latch are arranged in the second structure 852. The readout section 865 arranged in the first structure 851 is arranged outside the pixel array 864 in the column direction (longitudinal direction), and at least a part of the readout section 865 arranged in the second structure 852 is arranged on the lower layer side of the readout section 865 in the first structure 851. The wiring connection unit 869 is arranged outside the readout section 865 arranged in the first structure 851 and outside the readout section 865 arranged in the second structure 852. A wiring connection unit 869 connects the two readout sections 865 to each other.

The image signal processing unit 866 is arranged inside the scanning unit 862 and the readout section 865 arranged in the second structure 852.

In the second structure 852, a plurality of input/output circuit sections 889 are arranged in a region corresponding to the lower layer side of the pixel array 864 of the first structure 851. A plurality of input/output circuit portions 889 are provided in association with a plurality of corresponding external terminals 854.

Fig. 25 illustrates an example of a sectional structure of an image pickup apparatus 801. Fig. 25 illustrates a sectional structure taken along line a-a' in fig. 24. The pixel array 864 is arranged in a portion including the first structure 851 and above. A pixel transistor region 1001 is provided in a region where the pixel array 864 is formed (pixel array region). The pixel transistor region 1001 is a region where a transistor is formed in a pixel. A plurality of external terminals 854 are arranged in a region corresponding to the pixel array 864 of the first structure 851 on the lower surface of the semiconductor substrate 921 of the second structure 852. The plurality of external terminals 854 are connected to the input/output circuit portion 889 through the through holes 928 and the conductive pads 1022.

The wiring connection structure in which the wirings included in the multilayer wiring layer 942 of the first structure 851 are connected to the wirings included in the multilayer wiring layer 922 of the second structure 852 is referred to as an up/down wiring connection structure. The up/down wiring connection structure is provided in the up/down wiring connection region 1014. The up/down wiring connection region 1014 is provided outside the pixel peripheral circuit region 1013. The up/down wiring connection structure includes a through electrode 949, a through electrode 945, and a connection wiring 946. The Through electrode 949 is a Through Silicon Via (TSV) that penetrates the semiconductor substrate 941 from the upper surface of the first structure 851 to reach the multilayer wiring layer 942. The through electrode 945 is a chip penetrating electrode (chip penetrating electrode) penetrating the semiconductor substrate 941 and the multilayer wiring layer 942 from the upper surface of the first structure 851 to the multilayer wiring layer 922 of the second structure 852. The connection wiring 946 connects the two through electrodes. Such an up/down wiring connection structure is also referred to as a dual contact structure.

Fig. 26 illustrates another example of the sectional structure of the image pickup apparatus 801. The up/down wiring connection structure in this example is different from the up/down wiring connection structure shown in fig. 25. In this example, in the pixel peripheral circuit region 1013, a part of the wirings in the multilayer wiring layer 942 of the first structure 851 is arranged on the lowermost surface of the multilayer wiring layer 942. That is, a part of the wirings in the multilayer wiring layer 942 is arranged on the joint surface between the first structure 851 and the second structure 852. Similarly, a part of the wirings in the multilayer wiring layer 922 of the second structure 852 is arranged on the uppermost surface of the multilayer wiring layer 922. That is, a part of the wiring in the multilayer wiring layer 922 is arranged on the joint surface between the first structure 851 and the second structure 852. These respective portions of the wiring in the multilayer wiring layer 942 and the wiring in the multilayer wiring layer 922 are arranged at substantially the same position on the bonding surface, and these wirings are electrically connected to each other.

Fig. 27 illustrates a configuration example of an image pickup apparatus 801 having a dual contact structure. Fig. 27 illustrates a sectional structure of a portion near the outer periphery of the image pickup device 801.

The multilayer wiring layer 922 is formed on the upper side (the first structure 851 side) of the semiconductor substrate 921 of the second structure 852. The multilayer wiring layer 922 includes a plurality of wiring layers 923 and an interlayer insulating film 924. The plurality of wiring layers 923 include an uppermost wiring layer 923a, an intermediate wiring layer 923b, a lowermost wiring layer 923c, and the like. The uppermost wiring layer 923a is closest to the first structure 851. The lowermost wiring layer 923c is closest to the semiconductor substrate 921. The interlayer insulating film 924 is formed between the wiring layers 923.

At a predetermined position on the semiconductor substrate 921, a Through-Silicon Via 925 that penetrates the semiconductor substrate 921 is formed, and a connection conductor 927 is embedded in an inner wall of the Through-Silicon Via 925, and an insulating film 926 is interposed between the connection conductor 927 and the inner wall of the Through-Silicon Via 925, thereby forming a Through-hole (TSV) 928. The connection conductor 927 of the through hole 928 is connected to the wiring 930 formed on the lower surface side of the semiconductor substrate 921, and the wiring 930 is connected to the external terminal 854. Further, on the lower surface side of the semiconductor substrate 921, a solder resist (solder resist) 931 is formed so as to cover the wiring 930 and the insulating film 926, except for a region where the external terminal 854 is formed.

The multilayer wiring layer 942 is formed on the lower side (second structure 852 side) of the semiconductor substrate 941 of the first structure 851. The multilayer wiring layer 942 includes a plurality of wiring layers 943 and an interlayer insulating film 944. The plurality of wiring layers 943 include an uppermost wiring layer 943a, an intermediate wiring layer 943b, a lowermost wiring layer 943c, and the like. The uppermost wiring layer 943a is closest to the semiconductor substrate 941. The lowermost wiring layer 943c is closest to the second structure 852. An interlayer insulating film 944 is formed between the respective wiring layers 943.

A through electrode 949 as a through-silicon electrode and a through electrode 945 as a chip through electrode are formed in a predetermined region where the color filter 855 or the on-chip lens 856 is not formed on the semiconductor substrate 941. The through electrode 949 connects the wiring layer 943 of the first structure 851 to the connection wiring 946 formed on the upper surface of the semiconductor substrate 941, and the through electrode 945 connects the wiring layer 923 of the second structure 852 to the connection wiring 946. Further, insulating films 947 are formed between the through electrode 949 and the semiconductor substrate 941 and between the through electrode 945 and the semiconductor substrate 941.

A planarization film 948 is formed between the photodiode 891 of the semiconductor substrate 941 and the color filter 855, and a planarization film 950 is also formed between the on-chip lens 856 and the glass sealing resin 857.

Note that the present modification is not limited to such a configuration. For example, as shown in fig. 28A, the external terminal 854 may be formed at a position overlapping with the position of the through-hole 928. This eliminates the necessity of forming a space for the wiring 930 on the rear surface side of the image pickup device 801. Therefore, the external terminals 854 can be arranged more densely as shown in fig. 28B.

Further, for example, as shown in fig. 29, in the stacked structure 853, the wiring layer 943 of the second structure 852 and the wiring layer 923 of the first structure 851 may be connected by two Through electrodes of a Through electrode 949 and a Through electrode 945, and the wiring layer 923 and the external terminal 854 of the first structure 851 may be connected by a Through hole (TSV: Through Silicon Via)928 and a wiring 930.

Further, for example, as shown in fig. 30, the through-hole 928 may be filled with a solder resist film (solder resist) 931 and a portion where the through-hole 928 is formed may be cut.

[ other modifications ]

Further, two or more of these modifications may be combined.

<2 > second embodiment

Next, an image pickup apparatus 2 according to a second embodiment is described. In the present embodiment, identification information of the AD converter ADC is provided for the readout section, and the identification information is used to execute the diagnostic process. Note that the same reference numerals are used to denote substantially the same components as those of the image pickup apparatus 1 according to the first embodiment described above, and the description thereof is omitted as necessary.

Fig. 31 illustrates a configuration example of the image pickup apparatus 2 according to the present embodiment the image pickup apparatus 2 includes a pixel array 50, two scanning units 20L and 20R, a readout section 60, and a controller 70.

The pixel array 50 includes a plurality of pixels P1 and a plurality of light-shielded pixels P2. A plurality of pixels P1 are arranged in the normal pixel region R1, and a plurality of light-shielded pixels P2 are arranged in the light-shielded pixel regions R21 and R22. In this example, in the pixel array 50, the light-shielded pixel region R21, the normal pixel region R1, and the light-shielded pixel region R22 are arranged in this order from left to right in the horizontal direction (lateral direction in fig. 31).

The readout section 60 performs AD conversion based on the signal SIG supplied from the pixel array 50 through the signal line SG L, thereby generating an image signal DATA 0.

Fig. 32 illustrates a configuration example of the readout section 60, note that, in addition to the readout section 60, a controller 70 is drawn in fig. 32, the readout section 60 includes a readout controller 61, a reference signal generator 32, a plurality of AD converters ADC (AD converters ADC [0], ADC [1], ADC [2], … …), a plurality of selectors S L (selectors S L [0], S L [1], S L [2], … …), a plurality of switches SW (switches SW [0], SW [1], SW [2], … …)), and bus wiring 100.

The readout controller 61 controls the readout operation of the readout section 60 based on an instruction from the controller 70, specifically, the readout controller 61 supplies a control signal to the reference signal generator 32 so that the reference signal generator 32 generates the reference signal ref. furthermore, the readout controller 61 supplies a clock signal C L K and a control signal CC to the plurality of AD converters ADC so as to control the AD conversion operation of the plurality of AD converters ADC, further, the readout controller 61 supplies a control signal CT L to the plurality of selectors S L so as to control the respective selection operations of the plurality of selectors S L.

The selector S L selects and outputs one of a digital CODE CODE supplied from the AD converter ADC and a fixed digital CODE CODE2 associated with the AD converter ADC based on a control signal CT L. A plurality of selectors S L are provided in association with the plurality of AD converters ADC concretely, the 0 th selector S L [0] is provided in association with the 0 th AD converter ADC [0], the 1 st selector S L [1] is provided in association with the 1 st AD converter ADC [1], and the 2 nd selector S L [2] is provided in association with the 2 nd AD converter ADC [2 ].

In this example, each digital CODE2 is a 12-bit CODE selector S L includes input terminals to which the 12-bit digital CODE2 is supplied, respectively, readout section 60 includes two voltage supply lines VH L and V LL (described below) voltage generation section 72 applies a high-level voltage VH to voltage supply line VH L, and voltage generation section 72 applies a low-level voltage V L to voltage supply line V LL each input terminal for 12 bits of selector S L is connected to either voltage supply line VH L or voltage supply line V LL, that is, digital CODE2 is fixed and set by connection, respectively.

Fig. 33 illustrates an example of a 12-bit digital CODE 2. For example, the digital CODE2 corresponding to the 0 th AD converter ADC [0] is "000000000000", the digital CODE2 corresponding to the 1 st AD converter ADC [1] is "000000000001", and the digital CODE2 corresponding to the 2 nd AD converter ADC [2] is "000000000010". In this way, the digital CODEs CODE2 are set to be different from each other. In particular, in this example, each digital CODE2 is a CODE corresponding to the base of the AD converter ADC in binary number. In this example, the digital CODE2 is a 12-bit CODE, and thus can represent a radix of 4096 AD converters ADC. That is, the digital CODE2 is used as identification information INFA for identifying the AD converter ADC.

Then, the switch SW supplies the digital code output from the selector S L to the bus wiring 100 based on the control signal SSW supplied from the controller 40.

The controller 70 (fig. 31) supplies control signals to the scanning units 20L and 20R and the readout section 60 to control the operation of the image pickup apparatus 2, the controller 70 includes an address generating section 41, a voltage generating section 72, a column scanning section 73, an image processing section 44, and a diagnostic processing section 75.

The voltage generating section 72 generates a high-level voltage VH, a low-level voltage V L, and a power supply voltage VDD the voltage generating section 72 supplies the generated high-level voltage VH to the voltage supply line VH L in the readout section 60, supplies the generated low-level voltage V L to the voltage supply line V LL in the readout section 60, and supplies the generated power supply voltage VDD to the plurality of power supply lines P L in the pixel array 50.

The column scanning section 73 determines the selector S L to be subjected to the data transfer operation in the readout section 30, and generates the control signal SSW based on the determination result, and then, the column scanning section 43 supplies the generated control signal SSW to the plurality of switches SW of the readout section 60.

The diagnostic processing section 75 performs diagnostic processing based on the control signal SSW generated by the column scanning section 43 and the image signal DATA0, specifically, the diagnostic processing section 75 generates a CODE indicating the selector S L to perform a DATA transfer operation based on the control signal SSW, specifically, for example, in the case where the 0 th selector S L [0] is to perform a DATA transfer operation, the diagnostic processing section 75 generates a CODE "000000000000". in the case where the 1 st selector S L [1] is to perform a DATA transfer operation, the diagnostic processing section 75 generates a CODE "000000000001". in the case where the 2 nd selector S L [2] is to perform a DATA transfer operation, the diagnostic processing section 75 generates a CODE "000000000010". then, the diagnostic processing section 75 compares the CODE generated based on the control signal SSW with the digital CODE2 included in the image signal DATA0 to diagnose whether the image pickup apparatus 2 is performing a desired operation.

Here, the AD converter ADC corresponds to a specific example of "first conversion circuit" and "second conversion circuit" in the present invention, the selector S L corresponds to a specific example of "first selector" and "second selector" in the present invention, the switch SW corresponds to a specific example of "transmission section" in the present invention, and the diagnostic processing section 75 corresponds to a specific example of "diagnostic unit" in the present invention.

Fig. 34 schematically illustrates an overall operation example of the diagnosis process of the imaging apparatus 2.

The readout controller 61 of the readout section 60 supplies a control signal CT L to the plurality of selectors S L based on an instruction from the controller 70, thereby controlling the respective operations of the plurality of selectors S L so that the fixed digital CODE2 is selected and output.

Then, the column scanning section 43 of the controller 70 generates the control signal SSW to cause the selector S L to sequentially perform the DATA transfer operation, which causes the readout section 60 to supply the digital CODEs CODE2 output by the plurality of selectors S L to the controller 70 as the image signal DATA 0.

The diagnostic processing section 75 of the controller 70 generates a CODE indicating the selector S L to which the DATA transfer operation is to be performed based on the control signal SSW then the diagnostic processing section 75 compares the CODE generated based on the control signal SSW with the digital CODE2 included in the image signal DATA0 to diagnose whether the image pickup apparatus 2 is performing a desired operation.

For example, in a case where the CODE generated based on the control signal SSW and the digital CODE2 included in the image signal DATA0 match each other, the diagnostic processing section 75 diagnoses that the image pickup apparatus 2 is performing a desired operation.

Further, for example, in a case where the CODE generated based on the control signal SSW and the digital CODE2 included in the image signal DATA0 do not match each other, the diagnosis processing section 75 diagnoses that the image pickup apparatus 2 has a failure. The mismatch between the generated CODE and the digital CODE2 included in the image signal DATA0 may be caused by, for example, a failure of the column scanning section 73, a failure of the connection between the column scanning section 73 and the plurality of switches SW, a failure of the plurality of switches SW, or a failure of the connection between the readout section 60 and the diagnostic processing section 75.

The diagnostic processing section 75 performs diagnostic processing in this manner. Then, the diagnostic processing section 75 outputs the result of the diagnostic processing as a diagnostic result RES.

As described above, the image pickup apparatus 2 is provided with the selector S L between the AD converter ADC and the switch SW, the selector S L selects and outputs one of the digital CODE supplied from the AD converter ADC and the fixed digital CODE2 associated with the AD converter ADC, and therefore, self-diagnosis is performed so that a failure of data transmission control can be detected.

As described above, in the present embodiment, a selector is provided between the AD converter and the switch. The selector is capable of outputting a fixed digital code associated with the AD converter. Thus, performing self-diagnosis makes it possible to detect a failure of the image pickup apparatus.

[ modification 2-1]

For example, the technique according to the first embodiment and the technique according to the second embodiment may be combined.

[ modified examples 2-2]

The respective modified examples of the above-described first embodiment can be applied to the image pickup apparatus 2 according to the above-described embodiment.

<3. use example of imaging device >

Fig. 35 illustrates a use example of the image pickup apparatuses 1 and 2 according to the above-described embodiments. For example, the above-described image pickup devices 1 and 2 can be used in various cases where light such as visible light, infrared light, ultraviolet light, and X-rays is sensed as follows.

Means for taking images for appreciation, such as digital cameras and mobile devices with camera functions

Devices for traffic use, such as: an in-vehicle sensor that captures images of the front, rear, periphery, interior, and the like of the automobile for safe driving such as automatic parking and recognizing the state of the driver; a monitoring camera for monitoring a running vehicle and a road; and a distance measuring sensor for measuring the distance between the vehicle and the vehicle

Apparatus for household appliances such as televisions, refrigerators, and air conditioners to take images of user gestures and operate the appliances according to the gestures

Devices for healthcare use, such as endoscopes and devices for taking images of blood vessels by receiving infrared light

Devices for security purposes, such as surveillance cameras for crime prevention and cameras for personal authentication

Devices for cosmetic use, such as skin measuring devices taking images of the skin and microscopes taking images of the scalp

Devices for sports use, such as sports cameras and wearable cameras for sports applications

Devices for agricultural use, such as cameras for monitoring fields and crops

<4. application example of moving body >

The technique according to the present invention (present technique) is applicable to various products. For example, the technology according to the present invention may be implemented as an apparatus mounted on any type of moving body such as an automobile, an electric automobile, a hybrid automobile, a motorcycle, a bicycle, a personal mobile device, an airplane, an unmanned aerial vehicle, a ship, or a robot.

Fig. 36 is a block diagram showing an example of a schematic configuration of a vehicle control system as an example of a mobile body control system to which the technique according to the embodiment of the invention can be applied.

The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. In the example shown in fig. 36, the vehicle control system 12000 includes a drive system control unit 12010, a vehicle body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Further, a microcomputer 12051, a sound/image output section 12052, and an in-vehicle network interface (I/F)12053 are illustrated as a functional configuration of the integrated control unit 12050.

The drive system control unit 12010 controls the operations of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 functions as a control device of: a driving force generating device for generating a driving force of the vehicle, such as an internal combustion engine or a driving motor; a driving force transmission mechanism for transmitting a driving force to the wheel; a steering mechanism for adjusting a steering angle of the vehicle; and a brake device for generating a braking force of the vehicle, and the like.

The vehicle body system control unit 12020 controls the operations of various devices provided on the vehicle body according to various programs. For example, the vehicle body system control unit 12020 functions as a control device of a keyless entry system, a smart key system, a power window device, or various lamps such as a headlamp, a tail lamp, a brake lamp, a turn lamp, or a fog lamp. In this case, a radio wave transmitted from a mobile device instead of a key or a signal of various switches may be input to the vehicle body system control unit 12020. The vehicle body system control unit 12020 receives these input radio waves or signals, and controls a door lock device, a power window device, a lamp, or the like of the vehicle.

The vehicle exterior information detection unit 12030 detects information outside the vehicle including the vehicle control system 12000. For example, the vehicle exterior information detection means 12030 is connected to the imaging unit 12031. Vehicle exterior information detection section 12030 causes imaging section 12031 to capture an image of the outside of the vehicle and receives the captured image. Based on the received image, the vehicle exterior information detection unit 12030 may perform processing of detecting an object such as a person, a vehicle, an obstacle, a sign, or a character on a road surface, or performing processing of detecting a distance to the object.

The image pickup section 12031 is an optical sensor that receives light and outputs an electric signal corresponding to the amount of received light. The image pickup unit 12031 may output an electric signal as an image or an electric signal as information of a measured distance. Further, the light received by the image pickup portion 12031 may be visible light, or may be invisible light such as infrared light.

The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 for detecting the state of the driver, for example. The driver state detection unit 12041 includes, for example, a camera for imaging the driver. Based on the detection information input from the driver state detection section 12041, the in-vehicle information detection unit 12040 may calculate the degree of fatigue of the driver or the degree of concentration of the driver, or may determine whether the driver is dozing.

The microcomputer 12051 can calculate a control target value of the driving force generation device, the steering mechanism, or the brake device based on information on the inside and outside of the vehicle obtained by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 may execute cooperative control aimed at realizing functions of an Advanced Driver Assistance System (ADAS) including collision avoidance or impact mitigation of the vehicle, following driving based on a following distance, vehicle speed keeping driving, vehicle collision warning, vehicle lane departure warning, or the like.

Further, based on the information on the inside and outside of the vehicle obtained by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, the microcomputer 12051 can perform cooperative control intended for automatic driving or the like by controlling the driving force generation device, the steering mechanism, the brake device, or the like, which allows the vehicle to travel autonomously without depending on the operation of the driver.

Further, the microcomputer 12051 can output a control command to the vehicle body system control unit 12020 based on the information about the outside of the vehicle obtained by the outside-vehicle information detection unit 12030. For example, the microcomputer 12051 may perform cooperative control intended to prevent glare by controlling headlights to change from high beam to low beam, for example, in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the vehicle exterior information detection unit 12030.

The sound/image output portion 12052 transmits an output signal of at least one of sound and image to an output device capable of visually or aurally notifying an occupant of the vehicle or an outside of the vehicle of information. In the example of fig. 36, an audio speaker 12061, a display portion 12062, and a dashboard 12063 are illustrated as output devices. The display portion 12062 may include, for example, at least one of an in-vehicle display and a flat display.

Fig. 37 is a diagram showing an example of the mounting position of the imaging unit 12031.

In fig. 37, the image pickup portion 12031 includes image pickup portions 12101, 12102, 12103, 12104, and 12105.

The image pickup portions 12101, 12102, 12103, 12104, and 12105 are arranged, for example, at positions of a front nose, side mirrors, a rear bumper, and a rear door of the vehicle 12100 and at a position of an upper portion of a windshield inside the vehicle. The camera portion 12101 provided at the nose and the camera portion 12105 provided at the upper portion of the windshield inside the vehicle mainly obtain an image in front of the vehicle 12100. The image pickup portions 12102 and 12103 provided at the side mirrors mainly obtain images of the side of the vehicle 12100. An image pickup unit 12104 provided at a rear bumper or a rear door mainly obtains an image behind the vehicle 12100. The imaging portion 12105 provided at the upper portion of the windshield inside the vehicle is mainly used to detect a preceding vehicle, a pedestrian, an obstacle, a signal light, a traffic sign, a lane, or the like.

Incidentally, fig. 37 shows an example of the photographing range of the image pickup sections 12101 to 12104. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided at the nose. Imaging ranges 12112 and 12113 represent imaging ranges of the imaging portions 12102 and 12103 provided at the side mirrors, respectively. The imaging range 12114 indicates the imaging range of the imaging unit 12104 provided at the rear bumper or the rear door. For example, by superimposing the image data captured by the imaging sections 12101 to 12104, a bird's eye view image of the vehicle 12100 as viewed from above is obtained.

At least one of the image pickup portions 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the image pickup sections 12101 to 12104 may be a stereo camera composed of a plurality of image pickup elements, or may be an image pickup element having pixels for phase difference detection.

For example, the microcomputer 12051 may determine the distance from each three-dimensional object within the imaging ranges 12111 to 12114 and the change in the distance with time (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging sections 12101 to 12104, thereby extracting, as a preceding vehicle, the closest three-dimensional object that exists particularly on the traveling path of the vehicle 12100 and travels in substantially the same direction as the vehicle 12100 at a predetermined speed (e.g., equal to or greater than 0 km/h). In addition, the microcomputer 12051 may set in advance a following distance to be maintained ahead of the preceding vehicle, and may execute automatic braking control (including following stop control), automatic acceleration control (including following start control), or the like. Therefore, it is possible to perform cooperative control of automatic driving or the like that aims to autonomously run the vehicle without depending on the operation of the driver.

For example, the microcomputer 12051 may classify the three-dimensional object data on the three-dimensional object into three-dimensional object data of two-wheelers, standard-size vehicles, large-sized vehicles, pedestrians, utility poles, and other three-dimensional objects based on the distance information obtained from the image pickup portions 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatically avoiding obstacles. For example, the microcomputer 12051 recognizes obstacles around the vehicle 12100 as obstacles that can be visually recognized by the driver of the vehicle 12100 and obstacles that are difficult for the driver of the vehicle 12100 to visually recognize. Then, the microcomputer 12051 determines a collision risk indicating a danger of collision with each obstacle. In the case where the collision risk is equal to or higher than the set value and thus there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display portion 12062, and performs forced deceleration or evasive steering via the drive system control unit 12010. The microcomputer 12051 can thus assist driving to avoid a collision.

At least one of the image pickup portions 12101 to 12104 may be an infrared camera for detecting infrared rays. The microcomputer 12051 can recognize a pedestrian, for example, by determining whether or not a pedestrian is present in the captured images of the image capturing sections 12101 to 12104. This identification of pedestrians is performed, for example, by the following procedure: a process of extracting feature points in the captured images of the cameras 12101 to 12104 as infrared cameras; and a process of determining whether or not it is a pedestrian by performing a pattern matching process on a series of feature points representing the outline of the object. When the microcomputer 12051 determines that a pedestrian is present in the captured images of the imaging portions 12101 to 12104 and thereby recognizes a pedestrian, the sound/image output portion 12052 controls the display portion 12062 so that a square outline for emphasis is displayed in a manner superimposed on the recognized pedestrian. The sound/image output portion 12052 may also control the display portion 12062 so that an icon or the like representing a pedestrian is displayed at a desired position.

The example of the vehicle control system to which the technique according to the invention can be applied has been described above. The technique according to the present invention can be applied to the image pickup portion 12031 among the above-described components. Therefore, in the vehicle control system 12000, the diagnosis process is performed so that whether or not the imaging section 12031 is operating normally can be diagnosed. Then, when the imaging unit 12031 has a failure, the microcomputer 12051 is notified of the diagnosis result, for example. This allows the vehicle control system 12000 to recognize that the image pickup portion 12031 has a failure. For example, this allows the vehicle control system 12000 to perform appropriate processing such as drawing the attention of the driver or the like, so that the reliability can be increased. Further, in the vehicle control system 12000, the function of controlling the vehicle may be limited based on the result of the diagnosis process. Specific examples of the function of controlling the vehicle include a function of collision avoidance or impact mitigation of the vehicle, a function of follow-up driving based on a distance between the vehicle and the vehicle, a function of vehicle speed keeping driving, a function of vehicle collision warning, a function of vehicle lane departure warning, and the like. In the case where it is determined by the result of the diagnosis process that the image pickup section 12031 has a failure, the function of controlling the vehicle may be limited or disabled. This allows the vehicle control system 12000 to prevent an accident caused by a detection error based on a failure in the imaging section 12031.

The present technology has been described above by using some embodiments, modifications, and specific application examples thereof. However, the present technology is not limited to these embodiments and the like, and may be modified in various ways.

For example, the technique according to the first embodiment and the technique according to the second embodiment may be combined.

It is to be noted that the effects described in the present specification are only illustrative and not restrictive. Other effects may be included.

Note that the present technology may be configured as follows.

(1) An image pickup apparatus, comprising:

a plurality of pixel circuits including a first terminal, a second terminal, a third terminal, an accumulation unit configured to accumulate electric charges, a first transistor configured to connect the third terminal to the accumulation unit based on a voltage of the first terminal, a second transistor configured to supply a predetermined voltage to the accumulation unit based on a voltage of the second terminal, and an output unit configured to output a signal corresponding to the voltage in the accumulation unit, respectively, the plurality of pixel circuits including a first pixel circuit, a second pixel circuit, and a third pixel circuit;

a first control line extending in a first direction and connected to the respective first terminals of the first, second, and third pixel circuits;

a second control line extending in the first direction and connected to the respective second terminals of the first, second, and third pixel circuits;

a first voltage supply line connected to the third terminal of the first pixel circuit;

a second voltage supply line connected to the third terminal of the second pixel circuit;

a first light receiving element connected to the third terminal of the third pixel circuit; and

a diagnostic unit configured to perform diagnostic processing based on a first signal output from the output unit of the first pixel circuit and a second signal output from the output unit of the second pixel circuit.

(2) The image pickup apparatus according to (1), further comprising:

an address generating section configured to generate an address signal; and

a driving unit configured to drive the first control line and the second control line based on the address signal, wherein

The diagnostic unit performs the diagnostic process based on the address signal, the first signal, and the second signal.

(3) The image pickup apparatus according to (2), wherein the diagnosis unit includes:

a conversion circuit configured to generate a first digital code by performing AD conversion based on the first signal and a second digital code by performing AD conversion based on the second signal, an

Diagnostic circuitry configured to perform the diagnostic processing based on the address signal, the first digital code, and the second digital code.

(4) The image pickup apparatus according to (2) or (3), wherein

The first control line, the second control line, the first voltage supply line, the second voltage supply line, the plurality of pixel circuits, and the first light receiving element are formed on a first semiconductor substrate

The address generating section and the driving unit are formed on a second semiconductor substrate bonded to the first semiconductor substrate.

(5) The image pickup apparatus according to any one of (1) to (4), wherein

The plurality of pixel circuits respectively belong to any one of a plurality of pixel lines,

the first pixel circuit, the second pixel circuit, and the third pixel circuit belong to a first pixel line of the plurality of pixel lines,

a predetermined number of pixel circuits belong to respective ones of the plurality of pixel lines, the respective third terminals of the predetermined number of pixel circuits are connected to the first voltage supply line or the second voltage supply line, the predetermined number is greater than or equal to 2, and

the number of the plurality of pixel lines is less than or equal to the number represented by a connection combination of the respective third terminals and the first voltage supply line or the second voltage supply line in the predetermined number of pixel circuits.

(6) The image pickup apparatus according to (5), wherein the first information includes second information, the first information being represented by a connection combination of the respective third terminals of the predetermined number of pixel circuits belonging to the first pixel line and the first voltage supply line or the second voltage supply line, the second information being configured to identify the first pixel line.

(7) The image pickup apparatus according to (6), wherein the first information further includes third information indicating a property of the first pixel line.

(8) The image pickup apparatus according to any one of (1) to (7), further comprising:

third and fourth control lines extending in the first direction, respectively; and

a signal line connected to the output unit of the first pixel circuit, wherein

The plurality of pixel circuits includes a fourth pixel circuit,

the first terminal of the fourth pixel circuit is connected to the third control line,

the second terminal of the fourth pixel circuit is connected to the fourth control line,

the output unit of the fourth pixel circuit is connected to the signal line, and

the third terminal of the fourth pixel circuit is connected to the second voltage supply line.

(9) The image pickup apparatus according to any one of (1) to (8), further comprising a second light receiving element whose light is shielded, wherein

The plurality of pixel circuits includes a fifth pixel circuit,

the first terminal of the fifth pixel circuit is connected to the first control line,

the second terminal of the fifth pixel circuit is connected to the second control line, and

the third terminal of the fifth pixel circuit is connected to the second light receiving element.

(10) The image pickup device according to any one of (1) to (9), further comprising a voltage supply section configured to apply a first voltage signal having a first voltage and a second voltage to the first voltage supply line.

(11) The image pickup apparatus according to (10), wherein

The first voltage comprises the predetermined voltage, and

the first voltage signal has the first voltage in a first period in which both the first transistor and the second transistor are turned on, and the second voltage in a second period other than the first period.

(12) The image pickup device according to any one of (1) to (11), further comprising a third voltage supply line, wherein

The plurality of pixel circuits includes a sixth pixel circuit,

the first terminal of the sixth pixel circuit is connected to the first control line,

the second terminal of the sixth pixel circuit is connected to the second control line, and

the third terminal of the sixth pixel circuit is connected to the third voltage supply line.

(13) The image pickup apparatus according to any one of (1) to (12), further comprising a first driving unit configured to drive the first control line, wherein

The first control line has a first end and a second end, the first end is connected with the first driving unit,

the first pixel circuit and the second pixel circuit are arranged in a first region,

the third pixel circuit is arranged in the second region, and

the first region and the second region are arranged in order in a direction from the second end to the first end.

(14) The image pickup apparatus according to (13), further comprising a second driving unit that is connected to the second end of the first control line and is configured to drive the first control line.

(15) The image pickup apparatus according to (14), wherein

The plurality of pixel circuits includes a seventh pixel circuit and an eighth pixel circuit,

the respective first terminals of the seventh pixel circuit and the eighth pixel circuit are connected to the first control line,

the respective second terminals of the seventh pixel circuit and the eighth pixel circuit are connected to the second control line,

the third terminal of the seventh pixel circuit is connected to the first voltage supply line,

the third terminal of the eighth pixel circuit is connected to the second voltage supply line,

the seventh pixel circuit and the eighth pixel circuit are arranged in the third region, and

the first region, the second region, and the third region are arranged in order in a direction from the second end to the first end.

(16) An image pickup apparatus, comprising:

a plurality of pixel circuits including a first terminal, a second terminal, a third terminal, an accumulation unit configured to accumulate electric charges, a first transistor configured to connect the third terminal to the accumulation unit based on a voltage of the first terminal, a second transistor configured to supply a predetermined voltage to the accumulation unit based on a voltage of the second terminal, and an output unit configured to output a signal corresponding to the voltage in the accumulation unit, respectively, the plurality of pixel circuits including a first pixel circuit, a second pixel circuit, and a third pixel circuit;

a first control line extending in a first direction and connected to the respective first terminals of the first, second, and third pixel circuits;

a second control line extending in the first direction and connected to the respective second terminals of the first, second, and third pixel circuits;

a first voltage supply line connected to the third terminal of the first pixel circuit;

a second voltage supply line connected to the third terminal of the second pixel circuit; and

a first light receiving element connected to the third terminal of the third pixel circuit.

(17) An image pickup apparatus, comprising:

a first pixel circuit;

a first signal line connected to the first pixel circuit;

a first conversion circuit configured to generate a first digital code by performing AD conversion based on a signal in the first signal line;

a first selector including a first input terminal supplied with the first digital code and a second input terminal supplied with a first fixed digital code, the first selector being configured to select and output any one of the first digital code and the first fixed digital code;

a transmission section configured to transmit the digital code output from the first selector; and

a diagnostic unit configured to perform a diagnostic process based on the first fixed digital code transmitted by the transmission section.

(18) The image pickup apparatus according to (17), further comprising:

a second pixel circuit;

a second signal line connected to the second pixel circuit;

a second conversion circuit configured to generate a second digital code by performing AD conversion based on a signal in the second signal line; and

a second selector including a first input terminal supplied with the second digital code and a second input terminal supplied with a second fixed digital code, the second selector being configured to select and output any one of the second digital code and the second fixed digital code, wherein

The second fixed digital code comprises a digital code different from the first fixed digital code,

the transmission section also transmits the digital code output from the second selector, and

the diagnostic unit executes the diagnostic process based on the first fixed digital code and the second fixed digital code, which are transmitted by the transmission section.

(19) The image pickup apparatus according to (17) or (18), wherein the first fixed digital code includes information configured to identify the first conversion circuit.

This application claims priority to japanese priority patent application JP2017-234360, filed on 6.12.2017 with the office, and is hereby incorporated by reference in its entirety.

It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may be made depending on design requirements and other factors as long as they are within the scope of the appended claims or their equivalents.