阅读说明：本技术 电子器件 (Electronic device ) 是由 P·莫恩斯 A·巴纳尔吉 P·范米尔贝克 F·J·G·德克勒克 A·斯托克曼 于 2020-01-07 设计创作，主要内容包括：本发明公开了一种电子器件。所述电子器件可包括高电子迁移率晶体管,所述高电子迁移率晶体管包括掩埋区,覆盖在所述掩埋区上面的沟道层,栅极电极,以及覆盖在所述掩埋区上面的漏极电极。所述掩埋区可朝向所述栅极电极延伸并且不在所述栅极电极下面。在特定方面,所述电子器件还可包括覆盖在所述沟道层上面的p型半导体构件。所述栅极电极可覆盖在所述沟道层上面,并且p型半导体构件覆盖在所述沟道层上面。所述漏极电极可覆盖在所述掩埋区和所述p型半导体构件上面并与其接触。所述p型半导体构件可被设置在所述栅极电极和所述漏极电极之间。在另一个实施方案中,除了或代替耦接到所述漏极电极的所述掩埋区,可以使用源极侧掩埋区。(The invention discloses an electronic device. The electronic device may include a high electron mobility transistor including a buried region, a channel layer overlying the buried region, a gate electrode, and a drain electrode overlying the buried region. The buried region may extend toward and not under the gate electrode. In a particular aspect, the electronic device may further include a p-type semiconductor member overlying the channel layer. The gate electrode may overlie the channel layer, and a p-type semiconductor member overlies the channel layer. The drain electrode may cover and contact the buried region and the p-type semiconductor member. The p-type semiconductor member may be disposed between the gate electrode and the drain electrode. In another embodiment, a source side buried region may be used in addition to or instead of the buried region coupled to the drain electrode.)

1. An electronic device, comprising:

a high electron mobility transistor, the high electron mobility transistor comprising:

a first buried region;

a channel layer overlying the first buried region;

a gate electrode; and

a drain electrode overlying the first buried region,

wherein the first buried region extends toward and is not under the gate electrode.

2. The electronic device of claim 1, wherein the first buried region comprises a p-type semiconductor material.

3. The electronic device of claim 1 or 2, wherein the high electron mobility transistor further comprises a source electrode and a second buried region below the source electrode.

4. The electronic device of claim 3, wherein:

the high electron mobility transistor is a bidirectional transistor,

the drain electrode is a drain/source electrode for the bidirectional transistor, and

the source electrode is a source/drain electrode for the bidirectional transistor.

5. The electronic device of claim 3, wherein the second buried region comprises a first portion and a second portion, wherein the first portion is under the gate electrode and is thicker than the second portion, and:

the source electrode is closer to the second portion than the first portion, or

The drain electrode is closer to the second portion than the first portion.

6. The electronic device of claim 5, wherein a portion of the channel layer overlies the first portion of the second buried region, and the thickness of the portion of the channel layer is in a range of 20nm to 95 nm.

7. The electronic device of claim 1 or 2, wherein a lateral spacing between the first buried region and the gate electrode is:

y≥7.5(x)+0.3，

wherein the content of the first and second substances,

y is the lateral spacing between the first buried region and the gate electrode, in microns, and

x is a rated voltage of the high electron mobility transistor, wherein the rated voltage is in kV.

8. The electronic device of claim 1, wherein:

the high electron mobility transistor is an enhancement mode transistor,

the high electron mobility transistor further includes a buffer layer, a source electrode and a barrier layer,

the first buried region comprises a p-type semiconductor material,

the buffer layer is below the channel layer, has the same base semiconductor material as the channel layer, and has a higher dopant concentration than the channel layer,

the channel layer and the first buried region include Al_xGa_(1-x)N, wherein x is more than or equal to 0 and less than or equal to 0.1,

the first buried region overlies a portion but not all of the buffer layer,

the barrier layer overlies the channel layer and underlies the gate electrode, wherein the barrier layer comprises Al_yGa_(1-y)N, wherein 0<y ≦ 1 and wherein y>x，

A first portion of the drain electrode extends through the barrier layer and contacts the first buried region, and a second portion of the drain electrode extends over and contacts the barrier layer and

the source electrode overlies and contacts the barrier layer and is spaced apart from the channel layer.

9. An electronic device, comprising:

a high electron mobility transistor, the high electron mobility transistor comprising:

a first buried region;

a channel layer overlying the first buried region;

a gate electrode overlying the channel layer;

a p-type semiconductor member overlying the channel layer and disposed between the gate and drain electrodes; and

a drain electrode overlying the first buried region, wherein the drain electrode, the first buried region, and the p-type semiconductor member are connected to one another at a node.

10. The electronic device of claim 9, wherein the first buried region comprises a first portion and a second portion, wherein the first portion is thicker than the second portion, and the drain electrode is closer to the second portion than the first portion.

Technical Field

The present disclosure relates to electronic devices, and more particularly, to electronic devices including high electron mobility transistors having buried regions.

Background

The high electron mobility transistor may be an enhancement mode transistor. One type of such transistor may include a p-type GaN gate structure. In one configuration, the barrier layer is etched and p-type GaN is formed within the opening. Transistors with p-type GaN gate structures typically have high dynamic on-state resistance due to plasma-induced damage caused by pGaN etching in the access region. Transistors may also have relatively high on-state gate leakage compared to depletion mode high electron mobility transistors. When p-type GaN contains Mg, some of the Mg may diffuse into the GaN channel layer and increase the on-state resistance. Alternatively, the enhancement transistor may be formed with a dielectric layer as part of the gate structure.

The barrier layer may be etched and cause plasma damage that creates interface states or traps between the etched (plasma damaged) semiconductor surface and the subsequently deposited gate dielectric. This may result in high hysteresis, unstable threshold voltage, relatively high gate leakage, and relatively low gate voltage overload compared to depletion mode hemts. It would be desirable to further improve enhancement mode high electron mobility transistors without the aforementioned disadvantageous complications.

Disclosure of Invention

The problem to be solved by the present invention is to reduce the number of trapped electrons and to reduce or eliminate the dynamic on-state resistance.

According to an aspect of the present invention, an electronic device is provided. The electronic device may include a high electron mobility transistor including a first buried region, a channel layer overlying the first buried region, a gate electrode, and a drain electrode overlying the first buried region. The first buried region may extend toward and not under the gate electrode.

In one embodiment, the first buried region includes a p-type semiconductor material.

In another embodiment, the high electron mobility transistor further includes a source electrode and a second buried region under the source electrode.

In yet another embodiment, the high electron mobility transistor is a bidirectional transistor, the drain electrode is a drain/source electrode for the bidirectional transistor, and the source electrode is a source/drain electrode for the bidirectional transistor.

In yet another embodiment, the second buried region includes a first portion and a second portion, wherein the first portion is under the gate electrode and is thicker than the second portion, and either (1) the source electrode is closer to the second portion than the first portion, or (2) the drain electrode is closer to the second portion than the first portion.

In further embodiments, a portion of the channel layer overlies the first portion of the second buried region, and the portion of the channel layer has a thickness in a range of 20nm to 95 nm.

In another embodiment, the lateral spacing between the first buried region and the gate electrode is: ,

y≥7.5(x)+0.3

wherein the content of the first and second substances,

y is a lateral spacing between the first buried region and the gate electrode, in microns, and

x is of a high electron mobility transistor, wherein the rated voltage is in kV. Rated voltage

In another embodiment, the high electron mobility transistor is an enhancement mode transistor; the high electron mobility transistor further comprises a buffer layer, a source electrode and a barrier layer; the first buried region comprises a p-type semiconductor material; a buffer layer underlying the channel layer, having the same base semiconductor material as the channel layer, and having a higher dopant concentration than the channel layer; the channel layer and the first buried region contain Al_xGa_(1-x)N, wherein x is more than or equal to 0 and less than or equal to 0.1; the first buried region overlies a portion but not all of the buffer layer; a barrier layer overlying the channel layer and underlying the gate electrode, wherein the barrier layerThe layer contains Al_yGa_(1-y)N, wherein 0<y is less than or equal to 1, and wherein y>x; a first portion of the drain electrode extends through the barrier layer and contacts the first buried region, and a second portion of the drain electrode extends over and contacts the barrier layer, and the source electrode overlies and contacts the barrier layer and is spaced apart from the channel layer.

In a further aspect, an electronic device is provided. The electronic device may include a high electron mobility transistor including a buried region; a channel layer overlying the buried region; a gate electrode overlying the channel layer; a p-type semiconductor member overlying the channel layer and disposed between the gate electrode and the drain electrode; and a drain electrode overlying the buried region. The drain electrode, the buried region, and the p-type semiconductor member may be connected to each other at a node.

In further embodiments, the buried region includes a first portion and a second portion, wherein the first portion is thicker than the second portion, and the drain electrode is closer to the second portion than the first portion.

The technical effect achieved by the present invention is to have the drain side buried region below the channel layer and electrically connected to the drain electrode of the high electron mobility transistor. In one embodiment, the drain-side buried region may extend toward and not under a gate electrode of the transistor. In another embodiment, the p-type semiconductor member may be between the drain electrode and the gate electrode; and the drain electrode, the first buried region, and the p-type semiconductor member are connected to each other at a node.

Drawings

Embodiments are shown by way of example in the drawings and the embodiments are not limited thereto.

Fig. 1 includes an illustration of a cross-sectional view of a portion of a workpiece including a substrate, a superlattice structure, a buffer layer, and a drain-side buried region.

Fig. 2 includes an illustration of a cross-sectional view of the workpiece of fig. 1 after forming a channel layer, a barrier layer, and a gate electrode.

Fig. 3 includes an illustration of a cross-sectional view of the workpiece of fig. 2 after substantially completing formation of an enhancement mode HEMT structure, according to one embodiment.

Fig. 4 includes a plot of the minimum lateral spacing between the buried region and the gate electrode versus the rated voltage of the HEMT.

Fig. 5 includes an illustration of a cross-sectional view of a HEMT structure according to another embodiment that further includes a source side buried region.

Fig. 6 includes an illustration of a cross-sectional view of the HEMT structure of fig. 5 further including a conductive region according to another embodiment.

Fig. 7 includes an illustration of a cross-sectional view of the HEMT structure of fig. 5 further including a conductive region according to another embodiment.

Fig. 8 includes an illustration of a cross-sectional view of the HEMT structure of fig. 5 having a different source side buried region with thicker and thinner portions, according to another embodiment.

Fig. 9 includes an illustration of a cross-sectional view of a reverse blocking enhancement mode HEMT according to another embodiment.

Fig. 10 includes an illustration of a cross-sectional view of a HEMT structure having a source side buried region coupled to a back-blocking electrode according to another embodiment.

Fig. 11 includes an illustration of a cross-sectional view of a HEMT structure including a buried region according to further embodiments, wherein the HEMT is configured as a bidirectional transistor.

Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.

Detailed Description

The following description, in conjunction with the drawings, is provided to assist in understanding the teachings disclosed herein. The following discussion will focus on specific implementations and embodiments of the teachings. This focus is provided to help describe the teachings and should not be construed as limiting the scope or applicability of the teachings. However, other embodiments may be employed based on the teachings as disclosed in this application.

III-V material is intended to mean a material comprising at least one group 13 element and at least one group 15 element. III-N materials are intended to mean semiconductor materials comprising at least one group 13 element and nitrogen.

The term "base semiconductor material" is intended to mean a semiconductor material regardless of the presence, absence or type of aliovalent dopant relative to the semiconductor material. For example, unintentionally doped GaN, p-doped GaN and n-doped GaN all have GaN as base semiconductor material. GaN and Al_aGa_(1-a)N is a different base semiconductor material, of which 0.1<a≤1。

The term "transverse" and variations thereof, with respect to direction and dimension, refers to a direction or dimension along a major surface of a workpiece or a plane parallel to the major surface. The major surface may correspond to a surface of a layer within the workpiece. The two components may be located at different heights and spaced apart in the x-axis, the y-axis, or both the x-axis and the y-axis, where the x-axis and the y-axis are perpendicular to each other. The lateral dimension does not take into account vertical or z-axis offset.

The terms "normal operation" and "normal operation state" refer to conditions under which an electronic component or apparatus is designed to operate. The conditions may be obtained from a data table or other information about voltage, current, capacitance, resistance, or other electrical parameters. Thus, normal operation does not include operating an electronic component or device outside of its design limits.

The terms "comprises," "comprising," "includes," "including," "has," "having" or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a method, article, or apparatus that comprises a list of features is not necessarily limited to only those features but may include other features not expressly listed or inherent to such method, article, or apparatus. In addition, unless expressly stated to the contrary, "or" means an inclusive or, rather than an exclusive or. For example, condition a or B is satisfied by either: a is true (or present) and B is false (or not present), a is false (or not present) and B is true (or present), and both a and B are true (or present).

In addition, "a" or "an" is used to describe elements and components described herein. This is done merely for convenience and to give a general sense of the scope of the invention. The description is to be construed as including one, at least one, or the singular also includes the plural and vice versa unless it is explicitly stated that the contrary is intended. For example, when a single item is described herein, more than one item may be used in place of a single item. Similarly, where more than one item is described herein, a single item may be substituted for the more than one item.

The use of the words "about", "about" or "substantially" is intended to mean that the value of a parameter is close to a specified value or location. However, a slight difference may prevent the value or position from being exactly as specified. Thus, from an ideal target as fully described, a difference of at most ten percent (10%) for the value is a reasonable difference.

The group numbers correspond to columns in the periodic table of the elements based on the IUPAC periodic table, version 28/11/2016.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The materials, methods, and examples are illustrative only and not intended to be limiting. Many details regarding specific materials and processing acts are conventional and may be found in textbooks and other sources within the semiconductor and electronics arts, without being described herein.

An enhancement mode High Electron Mobility Transistor (HEMT) may include a buried region that has better performance than an enhancement mode HEMT without any buried region. In some embodiments, the diode is located between a buried region and a two-dimensional electron gas (2DEG), wherein the buried region is an anode of the diode. In the off state, the diode may be forward biased and the buried region may inject holes into the channel layer to recombine with trapped electrons and reduce or eliminate the dynamic on-state resistance. The lateral spacing between the drain side buried regions may be selected so that holes may be injected along all channel layers laterally between the gate electrode and the drain electrode. In addition, the drain side buried region may reduce the maximum electric field at the drain edge in the drain region when in the off state. The drain side field plate may or may not be used with the drain side buried region and the drain side buried region or the combination of the drain side field plate and the drain side buried region may be optimized and designed to achieve the desired electric field. In the on-state, the buried region, which is at a positive potential relative to the 2DEG, may increase the electron density within the 2DEG and decrease the on-state resistance (Rdson).

In another embodiment, the source side buried region may be coupled to the source electrode or the back blocking electrode. A relatively thick portion of the source side buried region under the gate electrode can contribute to double depletion of the channel of the HEMT, and a relatively thin portion relatively farther away from the 2DEG contributes to increasing the 2DEG electron density. The thicker portion may be replaced by another relatively thinner portion (the source side buried region may have a substantially uniform thickness similar to the thinner portion), which is advantageous for third quadrant (3Q) operation. A portion of the source side buried region may extend past the gate electrode to help shield the 2DEG from the substrate voltage.

In one aspect, an electronic device may include a high electron mobility transistor including a buried region, a channel layer overlying the buried region, a gate electrode, and a drain electrode overlying the buried region. The buried region may extend toward and not under the gate electrode.

In a further aspect, an electronic device may include a high electron mobility transistor including a buried region, a channel layer overlying the buried region, a gate electrode overlying the channel layer, a p-type semiconductor member overlying the channel layer, and a drain electrode overlying and in contact with the buried region and the p-type semiconductor member. The p-type semiconductor member may be disposed between the gate electrode and the drain electrode.

Fig. 1 includes a cross-sectional view of a portion of a workpiece 100 that may include a substrate 102, a superlattice structure (S L S)104, a buffer layer 106, and a buried region 108, the substrate 102 may include silicon, sapphire (single crystal Al), and a silicon-based material₂O₃) Silicon carbide (SiC), aluminum nitride (AlN), gallium oxide (Ga)₂O₃) Spinel (MgAl)₂O₄) Another suitable substantially single crystal material, etc. The selection of the particular material and crystal orientation along the major surface may be selected according to the composition of the overlying semiconductor layer.

S L S104 may include a III-V semiconductor base material, such as a III-N semiconductor base material in one embodiment, S L S may include Al_xGa_(1-x)S L S104 may have a composition that varies with thickness such that the closer S L S104 is to the substrate 102, the higher its aluminum content is relative and the higher its gallium content is relative to the channel layer in certain embodiments, the cation (metal atom) content in S L S104 near the substrate 102 may be 10 atomic% to 100 atomic% Al, the remainder Ga, and the cation content in S L S104 near the channel layer may be 0 atomic% to 50 atomic% Al, the remainder Ga. in another embodiment, S L S104 may include multiple films S L S104 may have a thickness in the range of 0.5 microns to 10 microns.

The buffer layer 106 may comprise a III-V semiconductor base material, such as a III-N semiconductor base material. In one embodiment, the buffer layer 106 may comprise Al_aGa (1-a) N, wherein a is more than or equal to 0 and less than or equal to 0.1. In a particular embodiment, the buffer layer comprises GaN (a ═ 0). The buffer layer 106 may include an electron acceptor, and the acceptor may be carbon. In one embodiment, when Metal Organic Chemical Vapor Deposition (MOCVD) is used to form buffer layer 106, the carbon may be from a source gas (e.g., Ga (CH)₃)₃) The dopant concentration may be at least 1 × 10¹⁷Atom/cm³In one embodiment, the dopant concentration may be at most 1 × 10²¹Atom/cm³. The buffer layer 106 may have a thickness in a range of 50nm to 500 nm.

The buried region 108 may comprise a p-type semiconductor material including a III-V semiconductor base material, such as a III-N semiconductor base material. The buried region 108 may be initially formed as all of the buffer layer 106An overlying III-V semiconductor layer. The III-V semiconductor layer may comprise Al_xGa_(1-x)N, where 0 ≦ x ≦ 0.3. in particular embodiments, the III-V semiconductor layer is a GaN layer (x ≦ 0). P-type dopants may include Mg, Ca, Cd, C, and the like¹⁶Atom/cm³At least 1 × 10¹⁷Atom/cm³Or at least 1 × 10¹⁸Atom/cm³In one embodiment, the dopant concentration may be at most 1 × 10²¹Atom/cm³. In one embodiment, the III-V semiconductor layer may have a thickness in a range of 5nm to 500 nm. The III-V semiconductor layer may be patterned to form a buried region 108. The positional relationship between the buried region 108 and other subsequently formed components of the HEMT structure will be described later in this specification.

In one embodiment, the S L S104, buffer layer 106, and III-V semiconductor layers for the buried region 108 may be formed between any one or more of the formed layers without exposing the workpiece to air.

Fig. 2 includes a workpiece after forming a channel layer 206 having a major surface 207, a barrier layer 208, and a gate electrode 210. The channel layer 206 may include a III-V semiconductor base material, such as a III-N semiconductor base material. In one embodiment, the buffer layer 106 and the channel layer 206 may have the same base semiconductor material. In one embodiment, the channel layer 206 may comprise Al_xGa_(1-x)N, wherein x is more than or equal to 0 and less than or equal to 0.1. In a particular embodiment, the channel layer 206 is a GaN layer (x ═ 0). The channel layer 206 may be inadvertently doped or doped with an electron donor (n-type) dopant or an electron acceptor (p-type) dopant. The 2DEG 200 is formed near the interface of the channel layer 206 and the barrier layer 208 and is in a conductive state when in a conductive stateIn this state, it is responsible for the high mobility and low resistivity of the transistor structure. The buried region 108 may affect the electron density within the 2DEG 200. Any reduction in the electron density within the 2DEG 200 will increase the on-resistance of the transistor. In one embodiment, the concentration of acceptors (when the carriers are electrons) or donors (when the carriers are holes) in the channel layer 206 may be reasonably kept as low as possible.

Thus, the channel layer 206 has a significantly lower dopant concentration (e.g., C content) than the buffer layer 106¹⁷Atom/cm³In other embodiments, the carrier impurity concentration is at 1 × 10¹³Atom/cm³To 1 × 10¹⁷Atom/cm³Within the range of (1).

The thickness of the channel layer 206 is selected such that the buried region 108 is deep enough from the major surface 207 not to deplete the 2DEG disposed along the interface between the channel layer 206 and the barrier layer 208. In addition, the thickness of the channel layer 206 may be selected such that the major surface 207 is planar over the workpiece, including regions where the buried regions 108 are not present. If the channel layer 206 is too thick, the effectiveness of the buried region 108 and the buffer layer 106 may be greatly reduced. As used herein, unless stated to the contrary, the thickness of the channel layer 206 corresponds to a thickness spaced apart from the buried region 108. Referring to fig. 2, the thickness of the channel layer 206 corresponds to the distance between the buffer layer 106 and the barrier layer 208. In one embodiment, the channel layer 206 may have a thickness of at least 20nm, and in another embodiment, the channel layer 206 may have a thickness of at most 4000 nm. In a particular embodiment, the channel layer 206 has a thickness in a range of 50nm to 500 nm.

The barrier layer 208 may comprise a III-V semiconductor base materialA material such as a III-N semiconductor base material. In particular embodiments, the barrier layer may comprise Al_yIn_zGa_(1-y-z)N, wherein 0<y is not less than 1.0, z is not less than 0 and not more than 0.3, and 0<(y + z) is less than or equal to 1.0. The barrier layer 208 may comprise a single film or multiple films. When the barrier layer 208 includes multiple films, the aluminum content may remain substantially the same or increase with increasing distance from the channel layer 206. As the aluminum content in the barrier layer 208 increases, the thickness of the barrier layer 208 may be relatively thin. In one embodiment, the barrier layer 208 has a thickness of at least 5nm, and in another embodiment, the barrier layer 208 has a thickness of at most 150 nm. In a particular embodiment, the barrier layer 208 has a thickness in the range of 10nm to 90 nm.

The gate electrode 210 may have any of the compositions, thicknesses, and formation techniques previously discussed with respect to the buried region 108. The gate electrode 210 may have the same or different composition as compared to the buried region 108, the gate electrode 210 may have the same or different thickness as compared to the buried region 108, and the gate electrode 210 may be formed using the same or different techniques as compared to the buried region 108. In one implementation, the gate electrode 210 may be thicker than the buried region 108.

In one embodiment, the channel layer 206, the barrier layer 208, and the III-V semiconductor layer for the gate electrode 210 may be formed without exposing the workpiece to air between any one or more of the forming layers. In one embodiment, each of the channel layer 206, the barrier layer 208, and the III-V semiconductor layer may be epitaxially grown from its corresponding underlying layer. In particular embodiments, channel layer 206, barrier layer 208, and the III-V semiconductor layer may be formed using MOCVD, MBE, or the like.

The presence of the buried region 108 and the gate electrode 210 allows the areal density of electrons within the 2DEG 200 to be lower at regions laterally between and near the edges of the buried region 108 and the gate electrode 210 as compared to other regions of the 2DEG 200. The buried region 108 and the gate electrode 210 are laterally spaced from each other by a lateral spacing 222. The minimum suggested value of the lateral spacing 222 depends on the voltage that the HEMT structure is to support. Consideration of the value of lateral spacing 222 is explained in more detail with respect to fig. 4.

Fig. 3 shows the hemt after the formation of the interlayer dielectric (I L D) layer 300, drain electrode 322, gate interconnect 324 and source electrode 326 the illustration in fig. 3 is a simplified version of the I L D layer 300, drain electrode 322, gate interconnect 324 and source electrode 326 a more accurate depiction and description can be found in US 9673311 which is incorporated due to its description of the insulating and conductive layers used to form the I L D layer, electrodes, interconnects and field plates (also known as shields).

A portion of the contact opening for the drain electrode 322 extends through the I L D layer 300, the barrier layer 208, and the channel layer 206. in one embodiment, the buried region 108 is located along a portion of the contact opening for the drain electrode 322. a portion of the drain electrode 322 can be formed at this time when forming the contact opening for the source electrode 326 and the gate interconnect 324 and the conductive layer, a contact opening for the drain electrode 322 and other portions of the conductive layer can be formed the uppermost layer of the source electrode 326 and the gate interconnect 324 can include field plates 3262 and 3242. the field plate 3262 extends over and beyond the gate electrode toward the drain electrode 322 and the field plate 3242 extends over the gate electrode 210 toward the drain electrode 322 as shown in fig. 3, the field plate 3262 extends further laterally toward the drain electrode 322 than 3242. in another embodiment, the field plates 3242 and 3262 can extend a different lateral distance than those described.

The buried region 108 and the gate electrode 210 are separated by a lateral spacing 222. The lateral spacing 222 may have a lower value because, inside the semiconductor material, a critical electric field may be maintained that is higher than an electric field at an interface (e.g., the interface between the barrier layer 208 and the dielectric layer 300). This is due to the better crystalline quality inside the semiconductor material. Due to the higher critical field, a smaller distance is needed to maintain the same voltage. Fig. 4 includes a graph of voltage as a function of minimum lateral spacing between buried region 108 and gate electrode 210. Generally, for a lateral HEMT transistor, the rated voltage (Vrated) is 2/3 of the breakdown voltage (Vbd). To support a given Vrated, the lateral spacing may be:

y≥7.5(x)+0.3

wherein: in units of micrometers, and

y is the lateral spacing.

x is Vrated in kV.

The characteristics of HEMT structures are noteworthy. Because the buried region 108 is far from the 2DEG and therefore does not significantly interfere with the field plates 3242 and 3262, the field plates help to deplete the 2DEG 200 when the HEMT is in the off state. The buried region 108 is deep enough so that it does not deplete the 2DEG 200 from the increase in the conduction band energy. When in the off state, the diode formed along the interface of the buried region 108 and the channel layer 206 is forward biased, and the buried region 108 may inject holes into the channel layer 206. These holes may recombine with trapped electrons within the channel layer 206 and, as a result, the dynamic on-state resistance is greatly reduced or eliminated. Because the buried region 108 extends significantly toward the gate electrode 210, holes may be injected along substantially all of the lateral gap between the gate electrode 210 and the drain electrode 322. In the off-state, the buried region 108 may act as a field plate and reduce the maximum electric field at the edge of the drain electrode 322 and in the drift region of the 2DEG 200 laterally between the gate electrode 210 and the drain electrode 322. When the HEMT is in the on-state, the buried region 108 can be at a positive potential with respect to the 2DEG 200 and helps to increase the electron density within the 2DEG 200 and reduce the on-Rdson.

Other embodiments may be used. In one embodiment (not shown), an additional layer similar to buffer layer 106 may be formed after forming buried region 108 and before forming channel layer 206. The additional layer may have any of the composition, thickness, and the buffer layer 106, and may be formed using any of the techniques used to form the buffer layer 106. The additional layer may help to spread the holes to provide a greater hole concentration. In one embodiment, the additional layer may have a thickness in the range of 10nm to 500 nm.

In further embodiments, a buried region may be used on the source side of the HEMT. Fig. 5 includes an illustration of such an embodiment with a drain side buried region 508 and a source side buried region 518. The source side buried region 518 may help to raise the energy of the conduction band and help to increase the threshold voltage. The source side buried region 518 may eliminate the need for a shield plate overlying the 2DEG 200, as will be described later in this specification. Buried regions 508 and 518 are spaced apart and may have a lateral spacing 522 having any of the values previously described with respect to lateral spacing 222.

The drain-side buried region 508 is similar to the buried region 208 having the relatively thin portion 5082, and further includes a relatively thick portion 5080 under the drain electrode 322. The source-side buried region 518 is a mirror image of the drain-side buried region 508, and has a relatively thick portion 5180 below the source electrode 526 and a relatively thin portion 5182 extending from the thick portion 5180 toward the drain-side buried region 508. The relatively thicker portions of buried regions 508 and 518 may allow more process margin when forming drain electrode 322 and source electrode 526 to reduce the likelihood of etching through buried regions 508 and 518 and to buffer layer 106. The thinner portions 5082 and 5182 of buried regions 508 and 518 may have thicknesses as previously described with respect to buried region 108, and the thickness of the thicker portions 5080 and 5180 may be in the range of 1.5 to 10 times the thickness of the thinner portions 5082 and 5182. In particular embodiments, the thickness of thicker portions 5080 and 5180 can be in the range of 50nm to 900 nm.

In another implementation, the source side buried region 518 may be used without the drain side buried region 508. In one implementation, the source side buried region 518 may have a higher resistivity than desired. Thus, in another embodiment, the conductive region 618 may underlie all of the source side buried region 518, as shown in fig. 6, or may underlie a portion of the source side buried region 518, as shown in fig. 7. The conductive region 618 may help reduce the voltage difference along the length of the source side buried region 518. In one embodiment, the conductive region 618 may provide a positive charge and comprise Al_jGa_(1-j)N, wherein 0<j is less than or equal to 1. In such embodiments, conductive region 618 may extend along all of buried region 518.

In further implementations, the conductive region 618 may comprise heavily n-doped Al_kGa_(1-k)N, wherein k is more than or equal to 0 and less than or equal to 1. n-type doped Al_kGa_(1-k)The doping concentration of N may be any of the concentrations previously described with respect to the buried region 108. In particular embodiments, Al_kGa_(1-k)N may be GaN and have a higher dopant concentration than the p-type dopant concentration of the source-side buried region 518. n-type doped Al_kGa_(1-k)N may be used along all of the buried regions 518 as shown in fig. 6. In another embodiment, a portion of the buried region 518 may extend along a lateral end of the conductive region 618, as shown in fig. 7. Portions of the buried region 518 may form a blocking diode that reduces leakage current between the source and drain of the HEMT structure.

The source electrode 526 in fig. 5-7 may have a structure similar to the drain electrode 322. A portion of source electrode 526 may overlie and contact the upper surface of barrier layer 208 and another portion of source electrode 526 may contact the underlying region. For the embodiment shown in fig. 5, the drain electrode 322 and the source electrode 526 may be formed using the same process sequence. With respect to the embodiments shown in fig. 6 and 7, a portion of the contact opening may extend to make ohmic contact with the conductive region 618.

Fig. 8 includes a cross-sectional view of another embodiment in which source side buried region 818 includes portions 8180, 8182, 8184, and 8186. Portions 8180 and 8184 are relatively thicker than portions 8182 and 8186 and provide a local back barrier under gate electrode 210, resulting in double depletion of the channel. The local back barrier may be connected to the source electrode 526 by the stepped profile of buried region 818. Portion 8182 is relatively thinner than portion 8184 and extends from portion 8184 toward source electrode 526. The portion 8182 is relatively farther from the 2DEG 200 in the source-gate access region than the portion 8184 to increase the 2DEG electron density. Portion 8186 is relatively thinner than portion 8184 and extends from portion 8184 toward drain electrode 322. The portion 8186 may help shield the voltage of the substrate 102 from the 2DEG 200.

Portions 8182 and 8186 may have thicknesses as previously described with respect to buried region 108. The thickness of portion 8184 may be in a range of 1.5 to 10 times the thickness of portions 8182 and 8186. In particular embodiments, the thickness of portion 8184 may be in a range of 50nm to 900 nm.

Channel layer 206 may be deposited to form major surface 207 such that major surface 207 is substantially planar. In one embodiment, a portion of the channel layer 206 over the portion 8184 may have a thickness in a range of 20nm to 95 nm. The thickness of the channel layer 206 at a location laterally spaced from the buried regions 508 and 818 may be any of the thicknesses of the channel layer 106 previously described with respect to figure 1. Lateral spacing 822 between portion 8186 of buried region 818 and buried region 508 may have any of the values previously described with respect to lateral spacing 222.

Fig. 9 includes an embodiment that includes a reverse blocking hemt. The right part of the structure resembles a gated diode. The structure includes a p-type semiconductor member 910 over the barrier layer 108, and the p-type semiconductor member 910 may include any of the compositions, thicknesses, and be formed using any of the techniques previously described with respect to the gate electrode 210. The structure also includes a drain side buried region 908 and a source side buried region 918. Drain-side buried region 908 includes relatively thicker portions 9080 and 9084 and a relatively thinner portion 9082 between portions 9080 and 9084, and source-side buried region 918 includes relatively thicker portions 9180 and 9184 and a relatively thinner portion 9182 between portions 9180 and 9184. Portion 9084 is under the p-type semiconductor member 910, and portion 9184 is under the gate electrode 210.

Portions 9082 and 9182 may have a thickness as previously described with respect to buried region 108. The thickness of the portions 9080, 9084, 9180, and 9184 may be in the range of 1.5 to 10 times the thickness of the portions 9082 and 9182. The channel layer 206 may have the thickness considerations as previously described with respect to fig. 8. The lateral spacing 922 between the portion 9184 of the buried region 918 and the portion 9084 of the buried region 908 may have any of the values previously described with respect to the lateral spacing 222.

The drain electrode 922 is similar to the drain electrode 322 and also includes a portion that contacts the p-type semiconductor member 910. Although not shown in the implementation of fig. 9, buried region 918 may include a portion that extends laterally through the gate electrode toward drain electrode 922, similar to portion 8186 of buried region 818 in fig. 8.

Fig. 10 includes another embodiment in which the buried region 1018 is contacted by a back barrier electrode 1028, the buried region 1018 includes portions 10180, 10182 and 10184 having thicknesses as previously described with respect to portions 9180, 9182 and 9184 of the buried region 918, this configuration allows the buried region 1018 to be controlled independently of the source electrode 326, the gate electrode 324 or both, an implant region 1006 may be formed within the channel layer 206 between the back barrier electrode 1028 and the 2DEG 200 below the source electrode 326 such that the 2DEG 200 does not extend to the back barrier electrode 1028, the implant will break the lattice and thus reduce the 2DEG, effectively isolating the material¹¹/cm²To 1 × 10¹⁵/cm²。

The implant depth is such that the implanted species covers the depth of the 2DEG, i.e. deeper than the thickness of layer 208. The diode 1028 is located between the portion 10184 and the 2DEG 200 of the buried region 1018, wherein the portion 10184 is an anode and the 2DEG 200 is a cathode. When holes are injected from the portion 10184 into the channel layer 206 that modularizes the electron density within the 2DEG 200 under the gate electrode 324, the positive potential on the portion 10184 (anode) helps to lower the energy of the conduction band (Ec) and lower Rdson until the diode 1028 becomes forward biased. The negative potential on portion 10184 (anode) helps to increase Ec and increase the threshold voltage (Vth).

The HEMT may be used as a high-side transistor or a low-side transistor in a switching circuit, where the source of the high-side transistor and the drain of the low-side transistor are coupled at a node and provide power to a load or other similar application. Table 1 includes a list of states and voltages. In the table, VBB is the voltage on the back blocking electrode 1028, and Vth is the threshold voltage of the HEMT.

TABLE 1 operating states of HEMTs in FIG. 10

In the off-state, the negative voltage of VBB increases the Vth of the HEMT (high Vth in table 1) and reduces the electron density within the 2DEG 200 under the gate electrode 324 to help keep the off-state current lower than it would be in the absence of the buried region 1018 and the back blocking electrode 1028. In the on state, the positive voltage of VBB reduces the Vth of the HEMT (low Vth in table 1) and allows Rdson lower than it would be without the buried region 1018 and back blocking electrode 1028. During the switching operation, the negative voltage VBB and high Vth can help reduce the ratio of gate-to-drain charge divided by gate-to-source charge. This configuration may be useful when the HEMT is a low-side transistor when switching from an off-state to an on-state, and when the HEMT is a high-side transistor when switching from a 3Q operation to an on-state. During 3Q operation, positive VBB and low Vth may help reduce dead time loss.

In fig. 10, the drain electrode 1022 is similar to the source electrode 326, and the buried region is not under the drain electrode 1022. In another embodiment, the drain side buried region 108 and the drain electrode 322 may be used in conjunction with the buried region 1018 and the back blocking electrode 1028. The lateral spacing between the drain-side buried region and the buried region 1018 may have any of the values previously described with respect to the lateral spacing 222.

Fig. 11 includes an illustration of a HEMT configured as a bidirectional transistor with a buried region. The HEMT comprises a drain/source electrode 1122 overlying and contacting the buried region 1108; a source/drain electrode 1126 overlying and contacting the buried region 1118; gate electrode 1110 and its corresponding gate interconnect 1124; and another gate electrode 1112 and its corresponding gate interconnect 1125. As can be seen in fig. 11, the right side of the HEMT is a mirror image of the left side of the HEMT. Buried region 1108 includes portions 11080, 11082, 11084, and 11086, and buried region 1118 includes portions 11180, 11182, 11184, and 11186. The composition and thickness of buried regions 1108 and 1118 and their counterparts can be any of those previously described with respect to buried region 818 in fig. 8. The lateral separation 1132 may have any of the values previously described with respect to the lateral separation 222. As previously described with respect to another embodiment, the channel layer 206 may be formed such that the major surface 207 is planar.

Other embodiments may be used without departing from the concepts described herein. In one embodiment, portions of either of the drain and source electrodes and the gate interconnect (overlying gate electrode 324) may or may not have portions that act as field plates. The drain-side buried region may help reduce the need for a field plate for the drain electrode, while the source-side buried region may help reduce the need for a field plate for either or both of the source electrode and the gate interconnect. In another embodiment, both the field plate and the buried region can be used along either the drain side or the source side of the HEMT structure. In further embodiments, buried regions 818, 918, and 1018 may have underlying conductive regions similar to conductive regions 618 as shown in fig. 6 and 7. In another implementation, the gate electrode 210 and the gate interconnect 324 may be replaced by a gate dielectric layer and a gate electrode. In another embodiment, the source electrode and the gate electrode may be electrically connected to each other such that the HEMT structure is a gated diode.

Embodiments as described herein can help form an enhancement mode HEMT with buried regions that has better performance than an enhancement mode HEMT without any buried regions. In some embodiments, the diode is located between the buried region and the 2DEG, wherein the buried region is an anode of the diode. In the off state, the diode may be forward biased and the buried region injects holes into the channel layer to recombine with trapped electrons and reduce or eliminate the dynamic on-state resistance. The lateral spacing may be selected such that holes are injected along all channel layers laterally between the gate electrode and the drain electrode. In addition, the drain side buried region can reduce the maximum electric field at the drain edge and in the drain region when in the off state. The drain side field plate may or may not be used with the drain side buried region. The drain side buried region or the combination of the drain side field plate and the drain side buried region can be optimized and designed to achieve the desired electric field. In the on state, the buried region, which is at a positive potential with respect to the 2DEG, may increase the electron density within the 2DEG and decrease Rdson.

The source side buried region may be coupled to the source electrode or the back blocking electrode. A relatively thick portion of the source side buried region under the gate electrode can contribute to double depletion of the channel of the HEMT structure, and the relatively thin portion of the source side buried region is relatively farther away from the 2DEG than the thick portion. The relatively large distance between the thinner portion of the source side buried region and the 2DEG increases the 2DEG electron density. The thicker portion may be replaced by another relatively thinner portion (the source side buried region may have a substantially uniform thickness similar to the thinner portion), which is advantageous for 3Q operation. A portion of the source side buried region may extend past the gate electrode to help shield the 2DEG from the substrate voltage.

Further control of the HEMT may be achieved when the source side buried region is coupled to the back blocking electrode. Such a configuration may be useful when the HEMT is a high-side transistor or a low-side transistor in a switching circuit. The back blocking electrode may be at a positive potential that lowers the Vth of the HEMT or may be at a negative potential that increases the Vth of the HEMT. In the off-state, off-state current may be reduced, and in the on-state, Rdson may be reduced, as compared to a HEMT without a source side buried and back blocking electrode. This configuration can help reduce the ratio of Qgd/Qgs and reduce dead time loss during switching and 3Q operations.

Many different aspects and embodiments are possible. Some of those aspects and embodiments are described below. Upon reading this specification, skilled artisans will appreciate that those aspects and embodiments are exemplary only, and do not limit the scope of the invention. Implementations may be in accordance with any one or more of the items listed below.