阅读说明：本技术 一种基于fpga的小区搜索粗同步的实现方法 (Method for realizing coarse synchronization of cell search based on FPGA ) 是由 程方 钟储苓 彭亚男 于 2020-03-17 设计创作，主要内容包括：本发明涉及一种基于FPGA的小区搜索粗同步的实现方法,属于通信工程领域。接收10ms数据,对10ms的数据进行频谱搬移,对数据进行降采样,降采样是通过对输入有效位进行计数,计数满16的时候输出有效位就拉高,降采样之后,对数据进行归一化,归一化是采用32个数据除以这32个数据的最大值的方式来实现。将38656个数据分别存储在RAM中,存满数据后,将RAM中的数据与本地的ROM数据进行互相关,本地ROM储存的是本地生成序列。比较三组ID的峰均比,最后判断小区搜索是否成功,小区搜索成功则返回小区ID号以及最大值的位置,失败则继续进行小区搜索。本发明可以解决小区搜索粗同步的问题。(The invention relates to a method for realizing coarse synchronization of cell search based on an FPGA (field programmable gate array), belonging to the field of communication engineering. Receiving 10ms data, carrying out frequency spectrum shifting on the 10ms data, carrying out down-sampling on the data, wherein the down-sampling is realized by counting input effective bits, pulling up the output effective bits when the counting is full of 16, and normalizing the data after the down-sampling is realized by dividing 32 data by the maximum value of the 32 data. 38656 data are stored in RAM, and after the data are stored in RAM, the data in RAM are correlated with local ROM data, which stores the locally generated sequence. And comparing the peak-to-average ratios of the three groups of IDs, finally judging whether the cell search is successful, if the cell search is successful, returning the ID number of the cell and the position of the maximum value, and if the cell search is failed, continuing the cell search. The invention can solve the problem of coarse synchronization of cell search.)

1. A method for realizing coarse synchronization of cell search based on FPGA is characterized in that: the method comprises the following steps:

s1: carrying out spectrum transfer on the received data, wherein the spectrum transfer is carried out by using a rotate IP core of vivado software to obtain the data after the spectrum transfer;

s2: performing FIR filtering on the received data after the frequency spectrum shift, wherein the FIR filtering uses an FIR IP core of vivado software;

s3: down-sampling the filtered data, and pulling up an output effective bit when the count is full of 16 by counting the effective bits of the input data;

s4: normalizing the down-sampled data, wherein the normalization is to compare every 32 data to obtain a larger value of a real part absolute value maximum value and an imaginary part absolute value, and divide the 32 data by the maximum value to obtain a normalized value;

s5: storing the first 38656 data in RAM;

s6: performing cross-correlation on data in the RAM and a locally generated sequence stored in the ROM;

s7: calculating the first 30 maximum values by bubbling, calculating the sum of the cross-correlations, and subtracting the first 30 maximum values from the sum; further calculating the peak-to-average ratio;

s8: and comparing the sizes of the three groups of ids after the peak-to-average ratio is calculated, if the maximum value of the group with the maximum value in the 3 groups of ids is larger than a preset standard value, the coarse synchronization is successful, and the positions of the cell id number and the maximum value are returned, otherwise, the coarse synchronization fails.

2. The method for implementing cell search coarse synchronization based on FPGA according to claim 1, characterized in that: in step S4, the normalizing the down-sampled data specifically includes separating the real part and the imaginary part of the down-sampled data, and converting the real part and the imaginary part into absolute values to be compared, where each 32 data is a group; meanwhile, the data is cached by using the fifo IP core of the vivado software, 32 data are output every time 32 data are fully stored, the maximum value of the absolute value of the 32 data is calculated, and then the 32 data are divided by the maximum value of the absolute value, so that the normalization is completed.

3. The method for implementing cell search coarse synchronization based on FPGA according to claim 1, characterized in that: in step S5, the data stored in the RAM are stored in 8 RAMs with depth of 4832 one by one, and when the data in the RAM is fetched and the index is 0, the 0 th data in the 8 RAMs is fetched; when the index is 1, the 1 st data of the 1 st RAM and the 0 th data of the 2 nd to 8 th data are fetched.

4. The method for implementing cell search coarse synchronization based on FPGA according to claim 1, characterized in that: in step S6, the nature of the cross-correlation is a sliding window operation, and 3 groups of locally generated sequences corresponding to different id numbers are divided into 8 groups and stored in 8 ROMs; multiplying the data in the RAM by the data in the ROM by using a multiplier; the sum of every 256 products is the result of a sliding window.

5. The method for implementing cell search coarse synchronization based on FPGA according to claim 1, characterized in that: in step S7, accumulating the result of each sliding window, entering the 30-stage pipeline as the result of each sliding window, assigning the entered data to the register when the entered data is greater than the data in the pipeline register, and sending the data to the next-stage pipeline; if the incoming data is smaller than the data in the pipeline register, the incoming data is streamed into the next stage pipeline, the data in the register remains unchanged, and 30 maximum values are obtained.

Technical Field

The invention belongs to the field of communication engineering, and relates to a method for realizing coarse synchronization of cell search based on an FPGA (field programmable gate array).

Background

The cell search process in the 5G terminal simulator system is the first step of the communication connection between the terminal and the base station, the coarse synchronization is the first step of the cell search, and the accuracy of the coarse synchronization and whether the coarse synchronization can be completed within a specified time are important. In the 5G terminal simulator system, IQ data are received, and the peak-to-average ratio is obtained through spectrum shifting, FIR filtering, down-sampling, normalization, RAM storage, cross-correlation, maximum value searching and peak-to-average ratio calculation. At present, fpga implementation aiming at cell search coarse synchronization is few, and in order to achieve completion of cell search within a specified time, 256 multiplications are completed within 32 clocks by adopting 8-way multipliers. The operation rate is effectively improved.

Disclosure of Invention

In view of this, the present invention provides a method for implementing coarse synchronization of cell search based on FPGA, which solves the FPGA implementation problem of coarse synchronization of cell search.

In order to achieve the purpose, the invention provides the following technical scheme:

a method for realizing coarse synchronization of cell search based on FPGA comprises the following steps:

s1: carrying out spectrum transfer on the received data, wherein the spectrum transfer uses a rota IP core of vivado software to obtain the data after the spectrum transfer;

s2: performing FIR filtering on the received data after the frequency spectrum shift, wherein the FIR filtering uses a FIRIP core of vivado software;

s3: down-sampling the filtered data, and pulling up an output effective bit when the count is full of 16 by counting the effective bits of the input data;

s4: normalizing the down-sampled data, wherein the normalization is to compare every 32 data to obtain a larger value of a real part absolute value maximum value and an imaginary part absolute value, and divide the 32 data by the maximum value to obtain a normalized value;

s5: storing the first 38656 data in RAM;

s6: performing cross-correlation on data in the RAM and a locally generated sequence stored in the ROM;

s7: calculating the first 30 maximum values by bubbling, calculating the sum of the cross-correlations, and subtracting the first 30 maximum values from the sum; further calculating the peak-to-average ratio;

s8: and comparing the sizes of the three groups of ids after the peak-to-average ratio is calculated, if the maximum value of the group with the maximum value in the 3 groups of ids is larger than a preset standard value, the coarse synchronization is successful, and the positions of the cell id number and the maximum value are returned, otherwise, the coarse synchronization fails.

Optionally, in step S4, the normalizing the down-sampled data specifically includes separating the real part from the imaginary part of the down-sampled data, and converting the real part and the imaginary part into absolute values to be compared, where each 32 data is a group; meanwhile, data are cached by fifo IP core of vivado software, 32 data are output every time 32 data are fully stored, the maximum value of the absolute value of the 32 data is calculated, and then the 32 data are divided by the maximum value of the absolute value, so that normalization is completed.

Optionally, in step S5, the data stored in the RAM are stored in 8 RAMs with a depth of 4832 one by one, and when the data in the RAM is fetched and the index is 0, the 0 th data in the 8 RAMs is fetched; when the index is 1, the 1 st data of the 1 st RAM and the 0 th data of the 2 nd to 8 th data are fetched.

Optionally, in step S6, the nature of the cross-correlation is a sliding window operation, and 3 groups of locally generated sequences corresponding to different id numbers are divided into 8 groups and stored in 8 ROMs; multiplying the data in the RAM by the data in the ROM by using a multiplier; the sum of every 256 products is the result of a sliding window.

Optionally, in step S7, accumulating the result of each sliding window, and entering the result of each sliding window into a 30-stage pipeline, and when the entered data is greater than the data in the pipeline register, assigning the entered data to the register, and sending the data of the register to the next-stage pipeline; if the incoming data is smaller than the data in the pipeline register, the incoming data is streamed into the next stage pipeline, the data in the register remains unchanged, and 30 maximum values are obtained.

The invention has the beneficial effects that: the invention meets the requirement of 5G terminal simulator cell search coarse synchronization on time, and each path of id has 8 multipliers in a 3-path id parallel mode. In the case of cross-correlation, the sum of 256 multiplications is calculated in 32 clocks by an 8-way multiplier as a result of one sliding window. Next, the first 30 maximums are found through a 30-stage pipeline. Specifically, the invention mainly adopts the following technologies:

(1) sliding window technique for 8-way multiplier: the coarse synchronization is mainly completed within the specified time, and the time is saved.

(2) Find 30 maximum values in the data stream technique: by bubble ordering like mathematics, only 30 more clocks are needed to find the 30 maxima than the data stream.

Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the means of the instrumentalities and combinations particularly pointed out hereinafter.

Drawings

For the purposes of promoting a better understanding of the objects, aspects and advantages of the invention, reference will now be made to the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1 is a flow chart of the present invention;

FIG. 2 shows a storage form of 38656 data in RAM cache;

fig. 3 is a diagram of searching 30 maxima and finding the peak-to-average ratio.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention in a schematic way, and the features in the following embodiments and examples may be combined with each other without conflict.

Wherein the showings are for the purpose of illustrating the invention only and not for the purpose of limiting the same, and in which there is shown by way of illustration only and not in the drawings in which there is no intention to limit the invention thereto; to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.

The same or similar reference numerals in the drawings of the embodiments of the present invention correspond to the same or similar components; in the description of the present invention, it should be understood that if there is an orientation or positional relationship indicated by terms such as "upper", "lower", "left", "right", "front", "rear", etc., based on the orientation or positional relationship shown in the drawings, it is only for convenience of description and simplification of description, but it is not an indication or suggestion that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes, and are not to be construed as limiting the present invention, and the specific meaning of the terms may be understood by those skilled in the art according to specific situations.

Referring to fig. 1 to 3, the method specifically includes the following steps:

s1: the receiving end successfully receives the normalized data, and the normalized data are sequentially stored in 8 RAMs;

s2: the count is 38656 digits full and storage is terminated.

Searching 30 maximum values and solving a peak-to-average ratio processing flow, specifically: delaying the correlated data by 32 clocks and 64 clocks, respectively; counting the data delayed by 32 clocks, assigning the cross-correlation data without delay, the value of a counter and the data delayed by 64 clocks to a register when the data is larger than the value of the register in the first-stage pipeline, wherein the data without delay is the value at the left end of the maximum value, the value delayed by 64 clocks is the value at the right end of the maximum value, and the value of the counter is the position of the maximum value; the maximum 30 values are compared in a 30-stage pipeline mode; and accumulating the sum of the cross-correlations to obtain the peak-to-average ratio. The invention can complete the coarse synchronization part within the time for cell search specified in the 5G protocol in the communication system, and the whole process is about 10 ms.

Finally, the above embodiments are only intended to illustrate the technical solutions of the present invention and not to limit the present invention, and although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that modifications or equivalent substitutions may be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions, and all of them should be covered by the claims of the present invention.