阅读说明：本技术 一种多晶硅的沉积方法及其应用 (Deposition method of polycrystalline silicon and application thereof ) 是由 李相遇 熊文娟 蒋浩杰 李亭亭 罗军 于 2020-04-10 设计创作，主要内容包括：本发明涉及一种多晶硅的沉积方法及其应用。一种多晶硅的沉积方法,包括下列步骤：在半导体载体沉积多晶硅膜,然后离子注入,再进行退火处理；其中,所述离子注入采用的离子为硅离子或金属离子。本发明可以在较低的温度下消除硅沉积时产生的缝隙或孔洞,从而减少后续工艺可能发生的缺陷。(The invention relates to a deposition method of polycrystalline silicon and application thereof. A method for depositing polysilicon, comprising the steps of: depositing a polycrystalline silicon film on a semiconductor carrier, then performing ion implantation, and then performing annealing treatment; wherein, the ions adopted by the ion implantation are silicon ions or metal ions. The invention can eliminate gaps or holes generated during silicon deposition at lower temperature, thereby reducing the possible defects of the subsequent process.)

1. A method for depositing polycrystalline silicon, comprising the steps of:

Depositing polycrystalline silicon on a semiconductor carrier, then implanting ions, and then carrying out annealing treatment;

Wherein, the ions adopted by the ion implantation are silicon ions or metal ions.

2. The deposition method of claim 1, wherein the semiconductor carrier is a semiconductor structure etched with contacts (contacts).

3. The deposition method of claim 1, which Characterized in that the process conditions for implanting ions are as follows: the implantation energy is 28-32 keV, and the implantation dose is 0.8-1.2E ¹⁶/cm²。

4. The deposition method according to claim 1, wherein the annealing treatment is performed under a vacuum atmosphere or a hydrogen atmosphere.

5. The deposition method according to claim 4, wherein the annealing treatment is performed under a vacuum atmosphere under the following process conditions: the temperature is 500-900 ℃, and the time is more than or equal to 10 min.

6. The deposition method according to claim 4, wherein the annealing treatment is performed under a hydrogen atmosphere under the process conditions of: the temperature is 500-900 ℃, the pressure is 0.1-200 torr, and the time is more than or equal to 10 min.

7. The deposition method of claim 1, wherein the metal ions are Ge ions.

8. The deposition method of any of claims 1-7, further comprising, after the ion implantation and before the annealing:

And implanting hydrogen ions.

9. The deposition method according to claim 8, wherein the process conditions for implanting hydrogen ions are: the implantation energy is 1-20 keV, and the implantation dosage is not less than 1E ¹³/cm²。

10. The deposition method of claim 1, further comprising, after said depositing polysilicon and before said ion implanting: chemical mechanical polishing or pitting.

11. The deposition method of claim 1, wherein the method of depositing polysilicon is a chemical vapor deposition method or an atomic layer deposition method.

12. a method of fabricating a bit L ine Contact (Data L ine Contact) and a storage node Contact of a DRAM, comprising:

Providing a semiconductor substrate, wherein the substrate comprises a buried channel transistor;

Etching the substrate to form a bit line contact part and a storage node contact part;

And a method of depositing polycrystalline silicon as claimed in any one of claims 1 to 11, wherein the semiconductor carrier is a storage node contact.

13. use of the deposition method according to any of claims 1 to 11 for the preparation of bit line (Data line) and capacitor hole structures.

14. Use of the deposition method of any of claims 1 to 11 in the manufacture of a semiconductor device.

15. Use according to claim 14, wherein the semiconductor device is an integrated circuit device or a capacitor.

Technical Field

The invention relates to the field of semiconductor preparation, in particular to a deposition method of polycrystalline silicon and application thereof.

Background

As the size of the capacitor hole of the DRAM device is gradually reduced along with the miniaturization of the DRAM device, the required depth-to-width ratio of the trench is larger, which results in that a hole or a gap is easily formed when depositing the polysilicon forming the capacitor hole, and the hole (void) or the gap (seam) can cause a defect such as resistance increase and the like when a subsequent process is performed if the hole or the gap is not processed.

To solve the above problems, US7157327B2 discloses a treatment method: after the polysilicon is deposited, annealing treatment is carried out in a hydrogen atmosphere, so that gaps or holes are eliminated by utilizing the migration of silicon atoms in the annealing process, however, the annealing step in the technology needs to be carried out at an extremely high temperature, and the process difficulty is increased.

Disclosure of Invention

The invention aims to provide a method for depositing polycrystalline silicon, which can eliminate gaps or holes generated during silicon deposition at lower temperature so as to reduce possible defects in subsequent processes.

In order to achieve the above purpose, the invention provides the following technical scheme:

A method for depositing polysilicon, comprising the steps of:

Depositing a polycrystalline silicon film on a semiconductor carrier, then performing ion implantation, and then performing annealing treatment;

Wherein, the ions adopted by the ion implantation are silicon ions or metal ions.

Compared with the prior art, the method adds ion implantation before annealing, so that the interior and the surface of the polysilicon film can be modified to generate a swelling effect, and silicon atoms can be migrated only by low-temperature annealing treatment to eliminate gaps or holes generated during deposition. The annealing treatment is generally carried out by the above method, and it is only required to be 500 ℃ or higher.

The deposition methods described above can be used to prepare capacitive pore structures.

The above deposition methods may also be used to prepare semiconductor devices including, but not limited to: integrated circuit devices or capacitors (e.g., DRAM, 2D NAND, 3D NAND, etc.).

a method of fabricating a bit line Contact (Data L ine Contact) and a storage node Contact of a DRAM, comprising:

Providing a semiconductor substrate, wherein the substrate comprises a buried channel transistor;

Etching the substrate to form a bit line contact part and a storage node contact part;

And a method of depositing polysilicon as described above, wherein the semiconductor carrier is a storage node contact.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings.

FIG. 1 is a schematic diagram of the structure after deposition of polysilicon in making B L bit line contacts;

FIG. 2 is a cross-sectional view of FIG. 1;

FIG. 3 is a schematic diagram of a structure after deposition of polysilicon and recess etching in fabricating cell capacitor holes;

FIG. 4 is a cross-sectional view of FIG. 3;

Fig. 5 to 9 are schematic views of a plurality of methods for depositing polysilicon according to the present invention.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.

Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.

in the process of B L Bit line Contact (Bit line Contact) formation, polysilicon 101 is deposited and patterned as shown in fig. 1, with a cross-sectional profile as shown in fig. 2, which shows a gap 102 in the deposited polysilicon that can cause defects in subsequent processes.

The same problem as above is also present in the cell capacitor hole fabrication process, where polysilicon is deposited and the undercut polysilicon 201 is patterned as shown in fig. 3, with a cross-sectional profile as shown in fig. 4, showing a gap 202 defect.

In order to solve the problems, the invention adopts the following measures after depositing the polysilicon:

Depositing polycrystalline silicon on a semiconductor carrier, then implanting ions, and then carrying out annealing treatment;

Wherein, the ions adopted by the ion implantation are silicon ions or metal ions.

For example, in the defects shown in fig. 2 and 4, the interior and surface of the polysilicon film are modified by ion implantation to generate a "swelling" effect, which facilitates the migration of silicon atoms during the subsequent annealing.

In the ion implantation step, the ions are selected to be non-destructive or beneficial to the electrical characteristics of the device, such as silicon ions, Si, or metal ions, including but not limited to Ge, W, etc. Suitable process conditions may differ for different ions, but suitable conditions for modification of polysilicon are typically selected in the following ranges: the implantation energy is 28-32 keV, and the implantation dose is 0.8-1.2E ¹⁶/cm²Wherein the more preferable condition is an implantation energy of 30keV and an implantation dose of 1E ¹⁶/cm²。

A direct anneal process may be selected after ion implantation is complete. The annealing treatment of the invention only needs to be carried out at a lower temperature, and the purpose of eliminating gaps and holes is achieved. The annealing treatment has a bond effect on the appearance improvement of the polysilicon deposition, and the annealing treatment conditions of different atmospheres are different. For example, the process conditions for performing the annealing treatment under a vacuum atmosphere are preferably: the temperature is 500-900 ℃, and the time is more than or equal to 10 min. The process conditions for carrying out the annealing treatment under a hydrogen atmosphere are preferably: the temperature is 500-900 ℃, the pressure is 0.1-200 torr, and the time is more than or equal to 10 min.

In order to improve the improvement effect on the polysilicon deposition morphology, a working procedure can be added after the ion implantation and before the annealing treatment: and implanting hydrogen ions. The process conditions for implanting hydrogen ions are preferably: the implantation energy is 1-20 keV, and the implantation dosage is not less than 1E ¹³/cm²。

although the present invention has been described with reference to the use of B L bit line contacts and cell capacitor holes, the present invention is not limited in its application to the fabrication of any semiconductor structure, and is particularly advantageous for use in semiconductor structures etched with trenches, where the trench aspect ratio is high and the occurrence of gaps and voids is more severe.

for example, methods of fabricating a bit L ine Contact (Data L ine Contact) and a storage node Contact of a DRAM include providing a semiconductor substrate including a buried channel transistor therein, etching the substrate to form the bit L ine Contact and the storage node Contact, and a method of depositing polysilicon of any of the above embodiments, wherein the semiconductor carrier is the storage node Contact.

In conjunction with the above, the primary deposition methods of the present invention include, but are not limited to, the methods of fig. 5-9.

In addition, in the manufacture of semiconductors, polishing or recessing is generally performed after deposition of polysilicon, and therefore, in order to avoid unnecessary workload of ion implantation and annealing treatment, it is recommended to perform polishing or recessing after deposition of polysilicon and before ion implantation.

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.