阅读说明：本技术 散热集成半导体晶体管及其制备方法 (Heat dissipation integrated semiconductor transistor and preparation method thereof ) 是由 刘杰 谷昊周 程知群 刘艳 董志华 严丽平 周涛 刘国华 李世琦 于 2020-03-10 设计创作，主要内容包括：本发明公开一种散热集成半导体晶体管及其制备方法,该方法包括步骤：在半导体衬底的正面沉积电极层,形成半导体晶体管；对半导体晶体管的表面进行预处理,以增加半导体晶体管表面的形核密度；在半导体晶体管的表面沉积纳米级金刚石层；在纳米级金刚石层的表面沉积微米级金刚石层,形成散热集成半导体晶体管。通过本发明方案,可以有效提升半导体晶体管的散热效率,通过实验表明,相同尺寸下,使用金刚石集成设计的半导体晶体管将拥有更大的功率密度。(The invention discloses a heat dissipation integrated semiconductor transistor and a preparation method thereof, wherein the method comprises the following steps: depositing an electrode layer on the front surface of the semiconductor substrate to form a semiconductor transistor; pretreating the surface of the semiconductor transistor to increase the nucleation density of the surface of the semiconductor transistor; depositing a nanoscale diamond layer on a surface of a semiconductor transistor; and depositing the micron-scale diamond layer on the surface of the nano-scale diamond layer to form the heat dissipation integrated semiconductor transistor. The scheme of the invention can effectively improve the heat dissipation efficiency of the semiconductor transistor, and experiments show that the semiconductor transistor which is integrally designed by using diamond has higher power density under the same size.)

1. A method for preparing a heat dissipation integrated semiconductor transistor is characterized by comprising the following steps:

depositing an electrode layer on the front surface of the semiconductor substrate to form a semiconductor transistor;

pretreating the surface of the semiconductor transistor to increase the nucleation density of the surface of the semiconductor transistor;

depositing a nanoscale diamond layer on a surface of a semiconductor transistor;

and depositing the micron-scale diamond layer on the surface of the nano-scale diamond layer to form the heat dissipation integrated semiconductor transistor.

2. The method of claim 1, wherein the surface of the semiconductor transistor comprises a front surface and a back surface, and further comprising the steps of:

step S00, depositing an electrode layer on the front surface of the semiconductor substrate to form a semiconductor transistor;

step S10, preprocessing the back surface of the semiconductor transistor to increase the nucleation density of the back surface of the semiconductor transistor;

step S20, depositing a nanoscale diamond layer on the back surface of the semiconductor transistor;

step S30, preprocessing the front surface of the semiconductor transistor to increase the nucleation density of the front surface of the semiconductor transistor;

step S40, depositing a nanoscale diamond layer on the front surface of the semiconductor transistor, wherein the nanoscale diamond layer covers the electrode layer;

step S50, depositing a micron-sized diamond layer on the surface of the nano-sized diamond layer on the back surface of the semiconductor transistor;

step S60, depositing a micron-sized diamond layer on the surface of the nano-sized diamond layer on the front surface of the semiconductor transistor;

step S70, photoetching the micron-scale diamond layer and the nanometer-scale diamond layer on the front surface of the semiconductor transistor to expose the electrodes and form the heat dissipation integrated semiconductor transistor,

the front surface of the semiconductor transistor is opposite to the front surface of the semiconductor substrate, and the back surface of the semiconductor transistor is opposite to the front surface of the semiconductor substrate.

3. The method of claim 2, further comprising, after step S00 and before step S10:

and thinning and polishing the middle part of the back surface of the semiconductor transistor to ensure that the thickness of the middle part of the semiconductor substrate is smaller than the thickness of the two sides of the semiconductor substrate, wherein the thickness of the middle part of the semiconductor substrate is vertical to the extending direction of a channel of the semiconductor transistor.

4. The method as claimed in claim 3, wherein the thickness of the diamond layer at each position on the back surface of the semiconductor transistor is uniform, and the outer surface of the diamond layer at each position on the back surface of the semiconductor transistor is flush.

5. The method of claim 2, further comprising, after step S50 and before step S60:

grinding the micron-sized diamond layer on the back surface of the semiconductor transistor;

and grinding the nanoscale diamond layer on the front surface of the semiconductor transistor, and performing ultrasonic treatment by using diamond powder.

6. The method of claim 5, further comprising, after step S60 and before step S70:

and grinding and polishing the micron-sized diamond layer on the front surface of the semiconductor transistor.

7. The method for manufacturing a heat sink integrated semiconductor transistor according to any of claims 1 to 6, wherein the surface of the semiconductor transistor is pre-treated, in particular comprising the steps of:

grinding and polishing the surface of the semiconductor transistor;

the surface of a semiconductor transistor is subjected to ultrasonic treatment in an alcohol solution by using diamond powder.

8. The method of fabricating a heat dissipating integrated semiconductor transistor according to any of claims 1 to 6 wherein the temperature at which the micro-scale diamond layer is deposited is greater than the temperature at which the nano-scale diamond layer is deposited; and the pressure at which the micro-scale diamond layer is deposited is less than the pressure at which the nano-scale diamond layer is deposited.

9. A heat sinking integrated semiconductor transistor, comprising:

the semiconductor transistor comprises a semiconductor substrate and an electrode layer arranged on the front surface of the semiconductor substrate;

the semiconductor transistor comprises a nanoscale diamond layer and a micron-scale diamond layer, wherein the nanoscale diamond layer and the micron-scale diamond layer are sequentially deposited outwards on the front face and the back face of the semiconductor transistor, and the electrode layer is exposed on the micron-scale diamond layer.

10. The heat dissipating integrated semiconductor transistor according to claim 9, wherein a thickness of the middle portion of the semiconductor substrate is smaller than thicknesses of both sides, perpendicular to an extending direction of a channel of the semiconductor transistor.

Technical Field

The invention relates to the technical field of semiconductors, in particular to a heat dissipation integrated semiconductor transistor and a preparation method thereof.

Background

At present, with the further development of the third generation semiconductor transistor, it realizes high forbidden band width and high electron mobility, so that it can operate at higher frequency and higher voltage. However, when a semiconductor transistor operates at high frequency and high voltage, a large amount of heat is generated. However, in the prior art, the serious thermal effect of the semiconductor transistor prepared by using SiC or GaN as the semiconductor substrate material restricts the improvement of the power density. Thus, although the semiconductor transistor can operate at higher power, the service life of the device is obviously reduced due to the accumulation of the thermal effect of the semiconductor transistor, and the operation stability of the power tube is also influenced.

Disclosure of Invention

The invention discloses a heat dissipation integrated semiconductor transistor and a preparation method thereof, which are used for solving the problem of low heat dissipation efficiency of the semiconductor transistor in the prior art.

In order to solve the problems, the invention adopts the following technical scheme:

a method for preparing a heat dissipation integrated semiconductor transistor is provided, which comprises the following steps:

depositing an electrode layer on the front surface of the semiconductor substrate to form a semiconductor transistor;

pretreating the surface of the semiconductor transistor to increase the nucleation density of the surface of the semiconductor transistor;

depositing a nanoscale diamond layer on a surface of a semiconductor transistor;

and depositing the micron-scale diamond layer on the surface of the nano-scale diamond layer to form the heat dissipation integrated semiconductor transistor.

Optionally, the surface of the semiconductor transistor includes a front surface and a back surface, and then the method specifically includes the steps of:

step S00, depositing an electrode layer on the front surface of the semiconductor substrate to form a semiconductor transistor;

step S10, preprocessing the back surface of the semiconductor transistor to increase the nucleation density of the back surface of the semiconductor transistor;

step S20, depositing a nanoscale diamond layer on the back surface of the semiconductor transistor;

step S30, preprocessing the front surface of the semiconductor transistor to increase the nucleation density of the front surface of the semiconductor transistor;

step S40, depositing a nanoscale diamond layer on the front surface of the semiconductor transistor, wherein the nanoscale diamond layer covers the electrode layer;

step S50, depositing a micron-sized diamond layer on the surface of the nano-sized diamond layer on the back surface of the semiconductor transistor;

step S60, depositing a micron-sized diamond layer on the surface of the nano-sized diamond layer on the front surface of the semiconductor transistor;

step S70, photoetching the micron-scale diamond layer and the nanometer-scale diamond layer on the front surface of the semiconductor transistor to expose the electrodes and form the heat dissipation integrated semiconductor transistor,

the front surface of the semiconductor transistor is opposite to the front surface of the semiconductor substrate, and the back surface of the semiconductor transistor is opposite to the front surface of the semiconductor substrate.

Optionally, after the step S00 and before the step S10, the method further includes the steps of:

and thinning and polishing the middle part of the back surface of the semiconductor transistor to ensure that the thickness of the middle part of the semiconductor substrate is smaller than the thickness of the two sides of the semiconductor substrate, wherein the thickness of the middle part of the semiconductor substrate is vertical to the extending direction of a channel of the semiconductor transistor.

Optionally, the thicknesses of the nanoscale diamond layers at the positions on the back surface of the semiconductor transistor are consistent, and the outer surfaces of the micron-sized diamond layers at the positions on the back surface of the semiconductor transistor are flush.

Optionally, after the step S50 and before the step S60, the method further includes the steps of:

grinding the micron-sized diamond layer on the back surface of the semiconductor transistor;

and grinding the nanoscale diamond layer on the front surface of the semiconductor transistor, and performing ultrasonic treatment by using diamond powder.

Optionally, after the step S60 and before the step S70, the method further includes the steps of:

and grinding and polishing the micron-sized diamond layer on the front surface of the semiconductor transistor.

Optionally, the surface of the semiconductor transistor is pretreated, specifically including the steps of:

grinding and polishing the surface of the semiconductor transistor;

the surface of a semiconductor transistor is subjected to ultrasonic treatment in an alcohol solution by using diamond powder.

Optionally, the temperature at which the micron-scale diamond layer is deposited is greater than the temperature at which the nanoscale diamond layer is deposited; and the pressure at which the micro-scale diamond layer is deposited is less than the pressure at which the nano-scale diamond layer is deposited.

There is also provided a heat dissipating integrated semiconductor transistor comprising:

the semiconductor transistor comprises a semiconductor substrate and an electrode layer arranged on the front surface of the semiconductor substrate;

the semiconductor transistor comprises a nanoscale diamond layer and a micron-scale diamond layer, wherein the nanoscale diamond layer and the micron-scale diamond layer are sequentially deposited outwards on the front face and the back face of the semiconductor transistor, and the electrode layer is exposed on the micron-scale diamond layer.

Optionally, the thickness of the middle portion of the semiconductor substrate is smaller than the thickness of the two sides of the semiconductor substrate, perpendicular to the extending direction of the channel of the semiconductor transistor.

The technical scheme adopted by the invention can achieve the following beneficial effects:

the nanoscale diamond layer is arranged on the surface of the semiconductor transistor, the semiconductor transistor is protected by the nanoscale diamond layer, and the semiconductor transistor is prevented from being regulated and damaged by high temperature and high pressure deposited by the next micron-scale diamond layer; the diamond layer can be directly grown on the surface of the semiconductor transistor, so that other medium layers are prevented from being introduced, and the influence of thermal resistance of other medium layer materials is eliminated, so that the semiconductor transistor directly radiates heat through the diamond, and the problem of radiation of the semiconductor transistor is effectively solved;

the diamond grows on the surface of the semiconductor transistor in a high-resistance state micron-scale form, so that the heat dissipation efficiency of the semiconductor transistor can be effectively improved; simultaneously, the micron-sized diamond layer in a high resistance state is deposited on the surface of the grid electrode layer, so that on one hand, the thermal conduction efficiency of the device can be further improved, and on the other hand, the normal use of the transistor is not influenced.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below to form a part of the present invention, and the exemplary embodiments and the description thereof illustrate the present invention and do not constitute a limitation of the present invention. In the drawings:

fig. 1 is a schematic flow chart of a method for manufacturing a heat dissipation integrated semiconductor transistor according to an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a semiconductor transistor according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a structure after a nanoscale diamond layer is deposited on the back surface of a semiconductor transistor according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a semiconductor transistor according to an embodiment of the present disclosure after a nanoscale diamond layer has been deposited on the front surface of the semiconductor transistor;

FIG. 5 is a schematic diagram of a structure after a micron-sized diamond layer is deposited on the back surface of a semiconductor transistor according to an embodiment of the present invention;

FIG. 6 is a schematic illustration showing a structure of a semiconductor transistor after a micron-sized diamond layer is deposited on a front surface thereof according to an embodiment of the present invention;

FIG. 7 is a schematic top view of a front micro-diamond layer and a front nano-diamond layer of a semiconductor transistor after lithography according to an embodiment of the present invention;

fig. 8 is a schematic diagram illustrating a polished structure of the nano-scale diamond layer on the front surface of the semiconductor transistor according to an embodiment of the present invention.

Wherein the following reference numerals are specifically included in figures 1-8:

a semiconductor transistor-1; a nanoscale diamond layer-2; a micron-sized diamond layer-3; a semiconductor substrate-11; an electrode layer-12; a groove-111; front side-A; back side-B.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the specific embodiments of the present invention and the accompanying drawings. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The technical solutions disclosed in the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

The method for manufacturing a heat dissipation integrated semiconductor transistor of the present invention, as shown in fig. 1, includes the following steps.

In step S1, as shown in fig. 2, electrode layer 12 is deposited on front surface a of semiconductor substrate 11 to form semiconductor transistor 1.

In this step, the material of the semiconductor substrate 11 may be SiC, GaN, a compound in which GaN and AiN are mixed, or the like. The formed semiconductor transistor 1 may be a MOS transistor 1, a CMOS transistor 1, a TFT transistor 1, or the like. The specific process of forming the semiconductor transistor 1 is the same as usual and will not be described in detail here.

In step S2, the surface of the semiconductor transistor 1 is pretreated to increase the nucleation density of the surface of the semiconductor transistor 1.

In this step, the pretreatment of the surface of the semiconductor transistor 1 specifically includes the steps of: firstly, grinding and polishing the surface of the semiconductor transistor 1; then, the surface of the semiconductor transistor 1 was subjected to ultrasonic treatment in an alcohol solution using diamond powder. The ultrasonic treatment of the diamond powder is to make the diamond powder continuously impact the surface of the semiconductor transistor 1 to form a certain defect, so that tiny nano-diamond powder can be attached to the surface of the semiconductor transistor 1, and a low-barrier energy layer is formed on the other hand, so that the nucleation density of the surface of the semiconductor transistor 1 is improved, the pores on the surface of the semiconductor transistor 1 are reduced, and the nucleation process in the diamond deposition process is facilitated.

The diamond powder can be formed by mixing diamond powder with the diameter of 10-20 nm and diamond powder with the diameter of 100-200 nm according to the ratio of 1: 1. If diamond powder of a larger size is used, it is disadvantageous to leave diamond powder on the surface of the semiconductor transistor 1, and the effect of deposition thereafter becomes poor, and if diamond powder of an excessively small size is used, a certain degree of agglomeration occurs.

In addition, the surface of the semiconductor transistor 1 may be a back side B of the semiconductor transistor 1 (which faces opposite to the front side a of the semiconductor substrate 11) and/or a front side a of the semiconductor transistor 1 (which faces the same as the front side a of the semiconductor substrate 11). That is, the micron-sized diamond layer 3 for heat dissipation may be finally deposited on the front side a of the semiconductor transistor 1 and/or on the back side B of the semiconductor transistor 1. The front side a of the semiconductor transistor 1 is pretreated while depositing a micrometer-sized diamond layer 3 for heat dissipation on the front side a of the semiconductor transistor 1. The back side B of the semiconductor transistor 1 is pretreated while depositing a micron-sized diamond layer 3 for heat dissipation on the back side B of the semiconductor transistor 1.

The back surface B of the semiconductor transistor 1 is different in configuration from the front surface a of the semiconductor transistor 1. The semiconductor transistor 1 has a rear side B formed by a rear side B of the semiconductor substrate 11. The front surface a of the semiconductor transistor 1 is formed by a front surface a of the electrode layer 12 (facing the same direction as the front surface a of the semiconductor substrate 11, specifically including the gate (G) electrode layer 12, the source (S) electrode layer 12, and the drain (D) electrode layer 12) and the front surface a of the semiconductor substrate 11 exposed to the outside.

In step S3, as shown in fig. 3 and 4, the nanoscale diamond layer 2 is deposited on the surface of the semiconductor transistor 1.

In this step, the nanoscale diamond layer 2 means that the diameter of the diamond powder in this layer is on the nanoscale. While the micro-scale diamond layer 3 for heat dissipation is deposited on the front surface a of the semiconductor transistor 1, the nano-scale diamond layer 2 is deposited on the front surface a of the semiconductor transistor 1. While the micro-scale diamond layer 3 for heat dissipation is deposited on the back surface B of the semiconductor transistor 1, the nano-scale diamond layer 2 is deposited on the back surface B of the semiconductor transistor 1. The thickness of the nanoscale diamond layer 2 can be set according to actual requirements, for example, when the nanoscale diamond layer 2 is deposited on the back surface B of the semiconductor transistor 1, the nanoscale diamond layer 2 only needs to cover the surface layer of the semiconductor transistor 1; when the nanoscale diamond layer 2 is deposited on the front surface a of the semiconductor transistor 1, the nanoscale diamond layer 2 covers the electrode layer 12.

By the above arrangement, the semiconductor transistor 1 can be prevented from being etched by hydrogen plasma; some compound semiconductor substrates 11 are easy to decompose, the appropriate low-temperature growth of the nano-scale diamond layer 2 can avoid the decomposition of the semiconductor substrate 11 when the micro-scale diamond layer 3 grows on the semiconductor substrate 11, the nano-scale diamond layer 2 protects the semiconductor transistor 1, and the semiconductor transistor 1 is prevented from being damaged by the high-temperature and high-pressure conditions of the deposition of the next micro-scale diamond layer 3; and the diamond layer directly grows on the surface of the semiconductor transistor 1, so that other medium layers are prevented from being introduced, and the influence of thermal resistance of other medium layer materials is eliminated, so that the semiconductor transistor 1 directly radiates heat through the diamond, and the heat radiation problem of the semiconductor transistor 1 is effectively solved.

During Deposition, the nano-scale diamond layer 2 may be deposited by using MPCVD (Microwave Plasma Chemical Vapor Deposition) technique and controlling the ratio of argon to hydrogen (the size of the grown diamond is changed by adjusting the atmosphere, and the content of argon may be controlled to about 88%, specifically, for example, 88% argon, 2% methane, and 10% hydrogen). In the deposition process, the deposition temperature is 300-700 ℃, the deposition pressure is 9-13 kPa, the pressure can be controlled by the gas inlet and outlet flow, and the temperature can be controlled by the deposition height and the deposition power of the diamond layer, so that the damage to the semiconductor transistor 1 is reduced on the premise of ensuring the density of the nanoscale diamond layer 2.

In step S4, as shown in fig. 5 and 6, the micro-scale diamond layer 3 is deposited on the surface of the nano-scale diamond layer 2, and the heat dissipation integrated semiconductor transistor is formed.

In this step, the micron-sized diamond layer 3 means that the diameter of the diamond powder in this layer is in the micron size. The thickness of the micron-sized diamond layer 3 may be between 50 and 200 microns. The diamond is a substrate 11 material with the highest thermal conductivity in the natural world at present, grows on the surface of the semiconductor transistor 1 in a high-resistance state, and can effectively improve the heat dissipation efficiency of the semiconductor transistor 1; meanwhile, the diamond layer in the high-resistance state is deposited on the surface of the gate electrode layer 12, so that on one hand, the thermal conduction efficiency of the device can be further improved, and on the other hand, the normal use of the semiconductor transistor 1 is not influenced.

During Deposition, the micron-sized diamond layer 3 may be deposited by using MPCVD (Microwave Plasma Chemical Vapor Deposition) technique and controlling the argon-hydrogen ratio (in this case, the hydrogen content may be controlled to be about 80%, specifically, for example, 10% for argon, 2% for methane, and 88% for hydrogen). The temperature at which the micro-scale diamond layer 3 is deposited is greater than the temperature at which the nano-scale diamond layer 2 is deposited, for example, between 600 and 800 c during deposition. The pressure when depositing the diamond layer 3 of micron order is less than the pressure when depositing the diamond layer 2 of nanometer order, in the diamond layer 3 of micron order deposits the course, the grain size is generally more close with the relation of the atmosphere, and while changing the atmosphere, in order to make plasma more stable, will change the pressure properly, in the microwave plasma apparatus that adopts, a large amount of argon gas is added, although it is easier to stimulate plasma, but need to keep 9 to 13 kilopascals, the plasma is more stable, however the diamond of micron order generally takes hydrogen as the leading, in the course of depositing actually, 7 to 10 kilopascals plasma can make the diamond of micron order grow steadily, therefore the concrete deposition pressure when depositing the diamond layer 3 of micron order is between 7 kilopascals and 10 kilopascals. Through the above mode setting, guarantee the thermal conductivity of micron order diamond layer 3 under the prerequisite of micron order diamond layer 3's density.

In addition to the above steps, when the micron-sized diamond layer 3 is deposited on the back side B of the semiconductor transistor 1, it may be possible to first, before step S2, along the extending direction of the channel of the semiconductor transistor 1, the middle part of the back surface B of the semiconductor transistor 1, in particular the semiconductor substrate 11, is subjected to a thinning polishing so as to be finally perpendicular to the extension direction of the channel of the semiconductor transistor 1, the thickness of the middle part of the semiconductor substrate 11 is smaller than the thickness of both sides, that is, the middle portion of the back surface B of the semiconductor substrate 11 is provided with a groove 111 extending in the channel direction, and the groove 111 is filled with the nano-diamond layer 2 and the micro-diamond layer 3, so that the micro-diamond layer 3 is closer to the channel, therefore, a large amount of heat generated at the channel can be effectively transferred out through the micron-sized diamond layer 3 on the back surface B of the semiconductor transistor 1, and the heat dissipation capacity of the semiconductor transistor 1 is greatly improved.

When the groove 111 is etched, substantially the entire semiconductor substrate 11 under the channel can be etched, i.e. the depth of the groove 111 should be close to the channel of the semiconductor transistor 1 but not to break down to the channel, in other words, the nanoscale diamond layer 2 is substantially close to the channel of the semiconductor transistor 1. Theoretically, the thickness of the nanoscale diamond layer 2 at each position B on the back surface of the semiconductor transistor 1 is uniform to reduce the time taken to deposit the nanoscale diamond layer 2; the thickness of the micron-sized diamond layer 3 at the position of the groove 111 is thicker, and the thickness of the micron-sized diamond layer 3 at other positions is thinner, so that the outer surfaces of the micron-sized diamond layers 3 at the positions of the back surface B of the semiconductor transistor 1 are flush, and the subsequent processes are facilitated.

When the micrometric diamond layer 3 is deposited on the front surface a of the semiconductor transistor 1, the micrometric diamond layer 3 and the nanometric diamond layer 2 cover the electrode layer 12, and therefore it is also necessary to perform photolithography on the micrometric diamond layer 3 and the nanometric diamond layer 2, as shown in fig. 7, to expose the electrode layer 12. The photoetching step specifically comprises the following steps: coating photoresist on the surface of the micron-sized diamond layer 3 and covering a layer of mask (the mask plate exposes the electrode area of the semiconductor transistor 1); then, the semiconductor transistor 1 is sent into a photoetching machine for photoetching, and the solubility of photoresist above the electrode is changed; placing the semiconductor transistor 1 into a developing solution to wash away the photoresist above the electrode area; the diamond layer of the electrode area is etched using oxygen gas, exposing the electrode layer 12 of the semiconductor transistor 1.

In addition, the nanoscale diamond layer 2 and the micron-sized diamond layer 3 on the front surface A of the semiconductor transistor 1 can be ground according to requirements, so that the smoothness of the nanoscale diamond layer 2 and the micron-sized diamond layer 3 is guaranteed, and the subsequent processes are facilitated.

The following describes in detail a method for manufacturing a heat-dissipating integrated semiconductor transistor, taking as an example that a micron-sized diamond layer 3 is deposited on both the front surface a and the back surface B of the semiconductor transistor 1, the method specifically comprising the steps of:

step S00, depositing electrode layer 12 on front surface a of semiconductor substrate 11 to form semiconductor transistor 1;

step S10, preprocessing the back surface B of the semiconductor transistor 1;

step S20, depositing the nanoscale diamond layer 2 on the back surface B of the semiconductor transistor 1;

step S30, preprocessing the front surface a of the semiconductor transistor 1;

step S40, depositing the nanoscale diamond layer 2 on the front surface a of the semiconductor transistor 1, wherein the nanoscale diamond layer 2 covers the electrode layer 12, and theoretically, the thickness of the nanoscale diamond layer 2 at each position may be substantially the same;

step S50, depositing a micro-scale diamond layer 3 on the surface of the nano-scale diamond layer 2 on the back side B of the semiconductor transistor 1;

step S60, depositing a micro-scale diamond layer 3 on the surface of the nano-scale diamond layer 2 on the front surface a of the semiconductor transistor 1;

step S70, performing photolithography on the micro-scale diamond layer 3 and the nano-scale diamond layer 2 on the front surface a of the semiconductor transistor 1 to expose electrodes, thereby forming a heat dissipation integrated semiconductor transistor.

Wherein, after the step S00 and before the step S10, the method further comprises the steps of: the middle of the back surface B of the semiconductor transistor 1 is thinned and polished so that the thickness of the middle of the semiconductor substrate 11 is smaller than the thickness of both sides in the direction perpendicular to the extension direction of the channel of the semiconductor transistor 1.

After the step S50 and before the step S60, the method further comprises the steps of: grinding the micron-sized diamond layer 3 on the back surface B of the semiconductor transistor 1; as shown in fig. 8, the nano-scale diamond layer 2 on the front surface a of the semiconductor transistor 1 was polished so that the nano-scale diamond layer 2 on the front surface a of the semiconductor transistor 1 was planar, and the nano-scale diamond layer 2 on the front surface a of the semiconductor transistor 1 was subjected to ultrasonic processing in an alcohol solution using diamond powder.

After the step S60 and before the step S70, the method further comprises the steps of: the micron-sized diamond layer 3 on the front surface a of the semiconductor transistor 1 is polished.

In the method, the preparation process of the heat dissipation integrated semiconductor transistor is reasonable and compact; the high configuration of the micron-sized diamond layer 3 is effectively ensured, and the normal use of the semiconductor transistor 1 is not influenced.

Of course, in other embodiments, the front surface a of the semiconductor transistor 1 may be pretreated and the nanoscale diamond layer 2 may be deposited, and then the back surface B of the semiconductor transistor 1 may be pretreated and the nanoscale diamond layer may be deposited; or the nano-scale diamond layer 2 on the back surface B of the semiconductor transistor 1 is subjected to polishing treatment or the like.

The heat dissipation integrated semiconductor transistor of the present invention includes: a semiconductor transistor 1 including a semiconductor substrate 11 and an electrode layer 12 provided on a front surface a of the semiconductor substrate 11; the nanoscale diamond layer 2 and the micron-scale diamond layer 3, the nanoscale diamond layer 2 and the micron-scale diamond layer 3 are sequentially deposited on the front surface A and the back surface B of the semiconductor transistor 1 outwards, and the electrode layer 12 is exposed out of the micron-scale diamond layer 3.

In the heat dissipation integrated semiconductor transistor, the semiconductor transistor 1 can be prevented from being etched by hydrogen plasma; some compound semiconductor substrates 11 are easy to decompose, the appropriate low-temperature growth of the nano-scale diamond layer 2 can avoid the decomposition of the semiconductor substrate 11 when the micro-scale diamond layer 3 grows on the semiconductor substrate 11, the nano-scale diamond layer 2 protects the semiconductor transistor 1, and the semiconductor transistor 1 is prevented from being regulated and damaged by the high temperature and high pressure deposited by the next micro-scale diamond layer 3; and the diamond layer directly grows on the surface of the semiconductor transistor 1, so that other medium layers are prevented from being introduced, and the influence of thermal resistance of other medium layer materials is eliminated, so that the semiconductor transistor 1 directly radiates heat through the diamond, and the heat radiation problem of the semiconductor transistor 1 is effectively solved. The diamond is a substrate 11 material with the highest thermal conductivity in the natural world at present, and grows on the surface of the semiconductor transistor 1 in a high-resistance state micron-scale mode, so that the heat dissipation efficiency of the semiconductor transistor 1 can be effectively improved; meanwhile, the micron-sized diamond layer 3 in a high resistance state is deposited on the surface of the grid electrode layer 12, so that on one hand, the thermal conduction efficiency of the device can be further improved, and on the other hand, the normal use of the transistor 1 is not influenced.

Further, the thickness of the middle portion of the semiconductor substrate 11 is smaller than the thickness of both sides, perpendicular to the extending direction of the channel of the semiconductor transistor 1. So set up, make micron order diamond layer 3 more be close to the channel to a large amount of heats that make channel department produce can effectively go out the heat transfer through the micron order diamond layer 3 of the 1 back B of semiconductor transistor, promoted semiconductor transistor 1's heat dissipation ability greatly.

While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.