阅读说明：本技术 包括控制信号增益的电子电路的装置 (Arrangement comprising an electronic circuit for controlling the gain of a signal ) 是由 尹永昌 闵东奎 安奎焕 李相昊 于 2020-01-10 设计创作，主要内容包括：本公开涉及包括控制信号增益的电子电路的装置,该装置包括：路径单元,该路径单元被配置为形成用于控制输入信号的增益的第一阻抗。该装置还包括分流单元,该分流单元被配置为形成第二阻抗以在路径单元与接地之间进行衰减,其中,该路径单元使用至少一个晶体管的导通电阻来形成第一阻抗。(The present disclosure relates to an apparatus comprising an electronic circuit controlling a signal gain, the apparatus comprising: a path unit configured to form a first impedance for controlling a gain of an input signal. The apparatus also includes a shunt unit configured to form a second impedance to attenuate between the path unit and ground, wherein the path unit forms the first impedance using an on-resistance of the at least one transistor.)

1. An apparatus comprising an electronic circuit, the apparatus comprising:

a path unit configured to form a first impedance for controlling a gain of an input signal; and

a shunt unit configured to form a second impedance to attenuate between the path unit and a ground,

wherein the path unit forms the first impedance using an on-resistance of at least one transistor.

2. The apparatus of claim 1, the apparatus further comprising:

an attenuation enabling unit configured to turn on or off a path between the path unit and the shunt unit,

wherein the attenuation enabling unit conducts the path if the electronic circuit attenuates a gain of the input signal.

3. The apparatus of claim 1, wherein the path unit comprises a plurality of paths forming different impedance values, and

each of the plurality of paths includes at least one transistor that functions as a switch.

4. The apparatus of claim 3, wherein at least one transistor included in a first path of the plurality of paths corresponding to a gain variation of the input signal is conductive, and

at least one transistor included in at least one path remaining after excluding the first path from the plurality of paths is turned off.

5. The apparatus of claim 3, wherein the plurality of paths comprises a pass-through path that provides minimal gain variation, and

the through path includes a transistor and an inductor connected in parallel.

6. The apparatus of claim 3, wherein at least one of the plurality of paths comprises a plurality of transistors connected in a stack structure.

7. The apparatus of claim 1, the apparatus further comprising:

an input matching unit connected to an input of the input signal,

wherein the input matching unit includes at least one inductor for performing compensation related to a parasitic capacitance of the at least one transistor.

8. The apparatus of claim 1, wherein the at least one transistor is controlled to be in a reverse bias state.

Technical Field

The present disclosure relates to electronic circuits, and more particularly to an apparatus including an electronic circuit for controlling a gain of a signal.

Background

In various electronic circuits that handle Radio Frequencies (RF), it is desirable to control the gain of a signal for various purposes. For example, a device performing communication may need to control a gain in order to perform effective signal processing in the device or to efficiently transmit a signal to the outside.

The circuit that controls the gain of the signal is called an attenuator. Depending on the detailed circuit design, the attenuator may have a gain control range and may have a limited linearity. The attenuator has a larger gain range and higher linearity, so the utilization rate of the attenuator can be improved.

The above information is presented merely as background information to aid in understanding the present disclosure. No determination is made as to whether any of the above can be used as prior art with respect to the present disclosure, nor is an assertion made.

Disclosure of Invention

An aspect of the present disclosure is to provide an apparatus including an electronic circuit configured to effectively control a gain of a signal.

An aspect of the present disclosure is to provide an apparatus including an electronic circuit that implements an attenuator having a wide gain control range and high linearity.

According to an aspect of the disclosure, an apparatus comprising electronic circuitry may comprise: a path unit configured to form a first impedance for controlling a gain of an input signal; and a shunt unit configured to form a second impedance to attenuate between the path unit and a ground, and the path unit may form the first impedance using an on-resistance of at least one transistor.

According to an aspect of the present disclosure, the apparatus may include an attenuation enabling unit configured to turn on or off a path between the path unit and the shunt unit, and the attenuation enabling unit may turn on the path if an electronic circuit attenuates a gain of an input signal.

According to an aspect of the present disclosure, the path unit may include a plurality of paths forming different impedance values, and each of the plurality of paths may include at least one transistor serving as a switch.

According to an aspect of the present disclosure, at least one transistor included in a first path corresponding to a gain variation of the input signal among the plurality of paths is turned on, and at least one transistor included in at least one path remaining after excluding the first path from the plurality of paths is turned off.

According to an aspect of the disclosure, the plurality of paths may include a through path providing a minimum gain variation, and the through path may include a transistor and an inductor connected in parallel.

According to an aspect of the present disclosure, at least one of the plurality of paths may include a plurality of transistors connected in a stack structure.

According to an aspect of the disclosure, the apparatus may further include: an input matching unit connected to an input end of the input signal; and the input matching unit may include at least one inductor for performing compensation related to a parasitic capacitance of the at least one transistor.

According to an aspect of the present disclosure, the at least one transistor may be controlled to be in a reverse bias state.

According to the apparatus of various embodiments, the attenuator is implemented using the on-resistance of the transistor, and a small circuit size and low voltage volume temperature (PVT) variation can be ensured.

Effects obtainable by the present disclosure are not limited to the above-described effects, and other effects not mentioned may be clearly understood by those skilled in the art from the following description.

Before proceeding with the following detailed description, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms "include" and "comprise," as well as derivatives thereof, mean inclusion without limitation; the term "or" is inclusive, meaning and/or; the phrases "and. The term "controller" refers to any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely.

Further, the various functions described below may be implemented or supported by one or more computer programs, each formed from computer-readable program code and embodied in a computer-readable medium. The terms "application" and "program" refer to one or more computer programs, software components, sets of instructions, procedures, functions, objects, classes, instances, related data, or a portion thereof, adapted for implementation in suitable computer readable program code. The phrase "computer readable program code" includes any type of computer code, including source code, object code, and executable code. The phrase "computer readable medium" includes any type of medium capable of being accessed by a computer, such as Read Only Memory (ROM), Random Access Memory (RAM), a hard disk drive, a Compact Disc (CD), a Digital Video Disc (DVD), or any other type of memory. A "non-transitory" computer-readable medium does not include a wired, wireless, optical, or other communication link that transmits transitory electrical or other signals. Non-transitory computer readable media include media that can permanently store data as well as media that can store data and later overwrite data, such as a rewritable optical disc or an erasable memory device.

Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.

Drawings

The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

FIG. 1 shows a diagram of an electronic circuit for controlling gain, in accordance with various embodiments;

FIG. 2 shows a diagram of a configuration of a gain control circuit, in accordance with various embodiments;

FIG. 3A illustrates a diagram of a configuration of a path unit of a gain control circuit, in accordance with various embodiments;

fig. 3B illustrates a diagram of an example of an implementation of a path unit of a gain control circuit, in accordance with various embodiments;

fig. 4A illustrates a diagram of an example of an implementation of a through path of a gain control circuit, in accordance with various embodiments; FIG. 4B illustrates a diagram of an implementation of a through path of a gain control circuit, in accordance with various embodiments; fig. 4C is a diagram illustrating an example of an implementation of a through path of a gain control circuit in accordance with various embodiments;

fig. 5A shows a graph comparing performance of an example of an implementation of a through path of a gain control circuit according to various embodiments; fig. 5B shows a graph comparing performance of an example of an implementation of a through path of a gain control circuit according to various embodiments;

fig. 6A shows a diagram of an example of an implementation of an input matching unit and an output matching unit of a gain control circuit, in accordance with various embodiments; fig. 6B shows a diagram of an example of an implementation of an input matching unit and an output matching unit of a gain control circuit, in accordance with various embodiments; and fig. 6C shows a diagram of an example of an implementation of an input matching unit and an output matching unit of a gain control circuit, in accordance with various embodiments;

fig. 7A shows a diagram of characteristics of an example of an implementation of an input matching unit and an output matching unit of a gain control circuit, in accordance with various embodiments; FIG. 7B is a diagram illustrating characteristics of an example of an implementation of an input matching unit and an output matching unit of a gain control circuit, in accordance with various embodiments; fig. 7C shows a diagram of characteristics of an example of an implementation of an input matching unit and an output matching unit of a gain control circuit, in accordance with various embodiments;

fig. 8 shows a diagram of an example of an implementation of an attenuation enable unit of a gain control circuit, in accordance with various embodiments;

fig. 9A illustrates a diagram of a configuration of a shunt unit of a gain control circuit, in accordance with various embodiments;

fig. 9B illustrates a diagram of an example of an implementation of a shunting unit of a gain control circuit, in accordance with various embodiments;

fig. 10A shows a diagram illustrating a reverse bias state of a transistor caused by a bias providing unit in a gain control circuit according to various embodiments; FIG. 10B is a diagram illustrating a reverse bias state of a transistor caused by a bias providing unit in a gain control circuit according to various embodiments;

fig. 11 shows a diagram of an example of an implementation of a gain control circuit in accordance with various embodiments; and

FIG. 12A shows a graph of performance of a gain control circuit in accordance with various embodiments; and fig. 12B is a graph of performance of a gain control circuit according to various embodiments.

Detailed Description

Fig. 1 through 12B, discussed below, and the various embodiments used to describe the principles of the present disclosure in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the disclosure. Those skilled in the art will understand that the principles of the present disclosure may be implemented in any suitably arranged system or device.

The terminology used in the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. Unless defined differently in context, singular expressions may include plural expressions. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms such as those defined in commonly used dictionaries may be interpreted as having a meaning that is consistent with their contextual meaning in the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. In some cases, even terms defined in the present disclosure should not be construed to exclude embodiments of the present disclosure.

Hereinafter, various embodiments of the present disclosure will be described based on a hardware method. However, various embodiments of the present disclosure include techniques that use both hardware and software, and thus may not preclude a software perspective.

In the following, the present disclosure relates to an apparatus comprising an electronic circuit for controlling the gain of a signal. In particular, the present disclosure relates to the implementation of attenuators, and describes the structure of the circuit of the attenuator implemented using the on-resistance of the transistor.

Hereinafter, for convenience of description, terms for representing signals, terms for materials, terms for structures, terms for shapes, and the like are used. Accordingly, the present disclosure is not limited to the terms used in the specification, and other terms having the same technical meaning may be used.

Fig. 1 shows a diagram of an electronic circuit for controlling gain according to various embodiments. Referring to fig. 1, the electronic circuit includes a gain control circuit 110 and a controller 120.

The gain control circuit 110 may include an input terminal (IN) and an output terminal (OUT), and may control (e.g., increase, decrease, or maintain) a gain of a signal input via the input terminal (IN) and output a signal whose gain is controlled via the output terminal (OUT). The signal may comprise a Radio Frequency (RF) signal.

The controller 120 may control the operation of the gain control circuit 110. The controller 120 may determine a variation in gain to be controlled by the gain control circuit 110 according to the magnitude of a desired output signal, and may generate and output a signal for controlling the operation of the gain control circuit 110. According to an embodiment, the controller 120 may convert the desired gain change value into a control signal for directly controlling the elements in the gain control circuit 110. To this end, the controller 120 may include at least one of: the device comprises a processor, a microprocessor, a microcontroller, a memory and a control signal generating circuit.

Fig. 2 shows a diagram of a configuration of a gain control circuit, in accordance with various embodiments. Referring to fig. 2, the gain control circuit 110 may include a path unit 210, an input matching unit 220a, an output matching unit 220b, an attenuation enabling unit 230, a shunt unit 240, and a bias providing unit 250.

The path unit 210 may form an impedance for controlling a gain of the signal. According to various embodiments, the path unit 210 may include at least one element forming a resistance and at least one element performing a switching. For example, the path unit 210 may include at least one transistor, and switching may be performed by controlling a voltage applied to a gate terminal of the transistor, and a resistance may be formed using an on-resistance of the transistor. Here, the on-resistance represents the resistance of the transistor itself determined by the length and width of the transistor. As the attenuation amount of the signal gain increases, the path unit 210 may form a greater impedance.

The input matching unit 220a may form an input impedance of the gain control circuit 110, and the output matching unit 220b may form an output impedance of the gain control circuit 110. The input matching unit 220a and the output matching unit 220b may form an input/output impedance (e.g., 50 Ω) of a predetermined size. The input matching unit 220a and the output matching unit 220b may include at least one element (e.g., an inductor or a capacitor) selected based on a characteristic of another element (e.g., the path unit 210, etc.). According to an embodiment, the input matching unit 220a and the output matching unit 220b may be excluded.

The attenuation enabling unit 230 may selectively connect the path unit 210 and the shunt unit 240. The attenuation enabling unit 230 may connect the path unit 210 and the shunt unit 240 if the gain control circuit 110 performs attenuation. In contrast, if the gain control circuit 110 passes a signal without performing attenuation, the attenuation enabling unit 230 may disconnect (open) the path between the path unit 210 and the shunt unit 240. To this end, the attenuation enabling unit 230 may include at least one switch.

When the gain control circuit 110 performs attenuation, the shunt unit 240 may form a desired impedance and an additional path. According to various embodiments, the shunt unit 240 may include at least one element forming a resistance and at least one element performing switching. For example, the path unit 210 may include at least one transistor, and switching may be performed by controlling a voltage applied to a gate terminal of the transistor, and a resistance may be formed using an on-resistance of the transistor. As the attenuation amount of the signal gain increases, the shunt unit 240 may form a larger impedance.

The bias providing unit 250 may provide a bias voltage to enable a transistor included in at least one of the path unit 210, the attenuation enabling unit 230, and the shunt unit 240 to operate in a reverse bias state. The bias supply unit 250 may supply voltages of predetermined magnitudes to the source terminal and the drain terminal to increase the linearity of the transistor in an off-state. To this end, the bias providing unit 250 may include at least one voltage source.

Fig. 3A illustrates a diagram of a configuration of a path unit of a gain control circuit, in accordance with various embodiments. Referring to fig. 3A, path unit 210 may include a through path 310 and a plurality of attenuation paths 320-1 to 320-N.

The through path 310 is a path through which a signal flows when the variation in gain is minimal. The through-path 310 may form an impedance value that is less than an impedance value of each of the plurality of attenuation paths 320-1 through 320-N. The plurality of attenuation paths 320-1 to 320-N are paths for providing different gain variations, and may form different impedance values.

The on-resistance of the transistor may be used to form the impedance value in the through path 310 and each of the plurality of attenuation paths 320-1 through 320-N. Accordingly, the through path 310 and each of the plurality of attenuation paths 320-1 through 320-N may include a set of transistors, the number and size of which may be different from each other. The through path 310 and the plurality of attenuation paths 320-1 through 320-N may be implemented as shown in fig. 3B.

Fig. 3B illustrates a diagram of an example of an implementation of a path cell of a gain control circuit, in accordance with various embodiments. The path unit 210 may be implemented as shown in fig. 3B. In this case, the example of the implementation of fig. 3B does not limit the present disclosure, and the path unit 210 may be implemented differently. Fig. 3B shows a case where one through path and four attenuation paths are implemented.

Referring to fig. 3B, the through path 310 may include a transistor 311 and an inductor 312. Transistor 311 may act as a switch and the on-resistance of transistor 311 and the inductance of inductor 312 may form the impedance of through-path 310. One end of the inductor 312 is connected to the drain terminal of the transistor 311 and the other end of the inductor 312 is connected to the source terminal of the transistor 311. As a switch, on/off of the transistor 311 may be controlled according to a control signal supplied to the gate terminal.

The first attenuation path 320-1 may form an impedance value greater than that of the through path 310 and less than that of the second, third, and fourth attenuation paths 320-2, 320-3, and 320-4. The first attenuation path 320-1 may include a transistor 321. The on-resistance value of the transistor 321 may be larger than the on-resistance of the transistor 311. For this reason, the width or length of the transistor 321 may be smaller than that of the transistor 311.

The second attenuation path 320-2 may form an impedance value greater than that of the through path 310 and the first attenuation path 320-1 and less than that of the third attenuation path 320-3 and the fourth attenuation path 320-4. The second attenuation path 320-2 may include a transistor 322 and a transistor 323 connected (stacked) in a stack structure. The sum of the on-resistance values of the transistor 322 and the transistor 323 can be larger than the on-resistance value of the transistor 321.

The third attenuation path 320-3 may form an impedance value greater than that of the through path 310, the first attenuation path 320-1, and the second attenuation path 320-2, and less than that of the fourth attenuation path 320-4. The third attenuation path 320-3 may include a transistor 324, a transistor 325, and a transistor 326 connected in a stack structure. The sum of the on-resistance values of the transistor 324, the transistor 325, and the transistor 326 may be larger than the sum of the on-resistance values of the transistor 322 and the transistor 323.

The fourth attenuation path 320-4 may form an impedance value greater than that of the through path 310, the first attenuation path 320-1, the second attenuation path 320-2, and the third attenuation path 320-3. The fourth attenuation path 320-4 may include a transistor 327, a transistor 328, and a transistor 329. The sum of the on resistance values of the transistor 327, the transistor 328, and the transistor 329 can be larger than the sum of the on resistance values of the transistor 324, the transistor 325, and the transistor 326.

In the structure shown in fig. 3B, the transistors included in the same path can be controlled to be equivalently turned on/off. If one of the plurality of paths 310, 320-1, 320-2, 320-3, and 320-4 is turned on and the remaining paths are turned off, a signal flows in a single path in an on state and a gain of the signal may be attenuated according to an impedance value formed in the corresponding path. The state in which the through path 310 is turned on is referred to as a "through mode", and the state in which one of the attenuation paths 320-1, 320-2, 320-3, and 320-4 is turned on is a "attenuation mode". For example, to impose a minimum gain variation, i.e., in the case of the through mode, transistor 311 in through path 310 is turned on and attenuation paths 320-1 to 320-4 are turned off. To disconnect attenuation paths 320-1 through 320-4, transistor 321 in first attenuation path 320-1 may be turned off, at least one or all of transistors 322 and 323 in second attenuation path 320-2 may be turned off, at least one or all of transistors 324 and 326 in third attenuation path 320-3 may be turned off, and at least one or all of transistors 327 and 329 in fourth attenuation path 320-4 may be turned off.

According to an embodiment, path unit 210 may be implemented as shown in FIG. 3B. In the example of fig. 3B, the through path 310 may include a single transistor and a single inductor. According to another embodiment, the pass-through path 310 may be implemented as shown in fig. 4A, 4B, or 4C.

Fig. 4A illustrates a diagram of an example of an implementation of a through path of a gain control circuit, in accordance with various embodiments; fig. 4B illustrates a diagram of an example of an implementation of a through path of a gain control circuit, in accordance with various embodiments; and fig. 4C is a diagram illustrating an example of an implementation of a through path of a gain control circuit, in accordance with various embodiments. The through path 310 may be implemented as shown in fig. 4A, 4B, or 4C. In this case, examples of the implementations of fig. 4A, 4B, or 4C may not limit the present disclosure, and the through path 310 may be implemented differently.

According to an embodiment, the through path 310 may be configured with a transistor 411, as shown in fig. 4A.

According to another embodiment, as shown in fig. 4B, the through path 310 may be configured with two transistors 421 and 422 connected in a stack structure, and a transistor 423 connected to a node for connecting the two transistors 421 and 422 through a drain terminal.

According to a further embodiment, the through-path 310 may be configured with a transistor 431 and an inductor 432 connected in parallel, as shown in fig. 4C. Here, the inductor 432 may be used to eliminate parasitic capacitance caused by the transistor 431.

Depending on the structure of the through-path 310, which may be implemented as shown in fig. 4A, 4B, or 4C, the minimum attenuation and the maximum attenuation of the gain control circuit 110 may be different. For example, as the width of the transistor included in the through path 310 becomes wider, the minimum attenuation becomes lower. As the width of the transistor becomes narrower, the maximum attenuation of the two embodiment examples shown in fig. 4A and 4B becomes higher. As the width of the transistor becomes narrower, the maximum attenuation of the implementation example shown in fig. 4C becomes lower. The minimum attenuation for the three examples of implementations shown in fig. 4A, 4B, or 4C is shown in fig. 5A, and the maximum attenuation is shown in fig. 5B.

Fig. 5A shows a graph comparing performance of an example of an implementation of a through path of a gain control circuit according to various embodiments; and fig. 5B shows a graph comparing performance of examples of implementations of the through path of the gain control circuit according to various embodiments. Fig. 5A and 5B relate to three examples of implementation, fig. 5A showing the minimum attenuation according to the width of the transistor, and fig. 5B showing the maximum attenuation according to the width of the transistor. Referring to fig. 5A, the implementation of fig. 4C may provide the lowest minimum attenuation. Additionally, referring to FIG. 5B, the implementation of FIG. 4C may provide the highest maximum attenuation within a predetermined width (e.g., 192 μm). Thus, it can be appreciated that the implementation of FIG. 4C may show the best performance. However, depending on the purpose of implementation, the through path 310 may be implemented as shown in fig. 4A, 4B, or 4C, or may be implemented in another structure.

Fig. 6A shows a diagram of an example of an implementation of an input matching unit and an output matching unit of a gain control circuit, in accordance with various embodiments; fig. 6B shows a diagram of an example of an implementation of an input matching unit and an output matching unit of a gain control circuit, in accordance with various embodiments; and fig. 6C shows a diagram of an implementation of an input matching unit and an output matching unit of a gain control circuit, according to various embodiments. The input matching unit 220a and the output matching unit 220B may be implemented as shown in fig. 6A, 6B, or 6C. In this case, the example of the implementation of fig. 6A, 6B, or 6C may not limit the present disclosure, and the input matching unit 220a and the output matching unit 220B may be implemented differently.

According to an embodiment, the input matching unit 220a and the output matching unit 220b may be omitted, as shown in fig. 6A.

According to another embodiment, as shown in fig. 6B, the input matching unit 220a and the output matching unit 220B may be configured with an inductor 621a or an inductor 621B connected in parallel. Referring to fig. 6B, one end of the input matching unit 220a is connected to the input terminal of the path unit 210, and the other end includes a ground inductor 621 a. One end of the output matching unit 220b is connected to the input terminal of the path unit 210, and the other end includes a ground inductor 621 b. Inductors 621a and 621b may be used to perform compensation associated with parasitic capacitance caused by transistors included in path unit 210.

According to yet another embodiment, as shown in fig. 6C, the input matching unit 220a and the output matching unit 220b may be configured with an inductor 631a or 631b connected in parallel, a capacitor 632a or 632b connected in parallel, and a switch 633a or 633b connected to the capacitor 632a or 632 b. Inductors 631a and 631b may be used to perform compensation associated with parasitic capacitance caused by transistors included in path cell 210. Capacitors 632a and 632b may be used to compensate for the difference in parasitic capacitance between the on state and the off state of through path 310. Accordingly, the switches 633a and 633b can be controlled according to the on/off state of the through path 310. For example, when the through path 310 is on, the switch may be closed, and when the through path 310 is open, the switch may be open.

The input impedance and the output impedance may be different according to the structures of the input matching unit 220a and the output matching unit 220B, which may be implemented as shown in fig. 6A, 6B, or 6C. The input/output impedance values according to the implementations of fig. 6A, 6B, or 6C may be plotted on a smith chart as shown in fig. 7A-7C.

Fig. 7A shows a diagram of characteristics of an example of an implementation of an input matching unit and an output matching unit of a gain control circuit, in accordance with various embodiments; FIG. 7B is a diagram illustrating characteristics of an example of an implementation of an input matching unit and an output matching unit of a gain control circuit, in accordance with various embodiments; and fig. 7C is a diagram illustrating characteristics of an example of implementation of an input matching unit and an output matching unit of a gain control circuit according to various embodiments. Fig. 7A to 7C show input/output impedance values when one of the five paths of the path unit 210 is used. Fig. 7A is an example of the input matching unit 220a and the output matching unit 220b implemented as shown in fig. 6A. Fig. 7B is an example of the input matching unit 220a and the output matching unit 220B implemented as shown in fig. 6B. Fig. 7C is an example of the input matching unit 220a and the output matching unit 220b implemented as shown in fig. 6C. Referring to fig. 7A-7C, the implementation of fig. 6B or 6C may provide impedance values closer to 50 Ω when compared to the implementation of fig. 6A.

Fig. 8 illustrates a diagram of an example of an implementation of an attenuation enable unit of a gain control circuit, in accordance with various embodiments. The attenuation enabling unit 230 may be implemented as shown in fig. 8. In this case, the example of the implementation of fig. 8 does not limit the present disclosure, and the attenuation enabling unit 230 may be implemented differently.

Referring to fig. 8, the attenuation enabling unit 230 may have a structure in which a first portion 230a and a second portion 230b are connected in parallel. The first portion 230a includes transistors 801a, 802a, and 803a connected in a stacked configuration, and the second portion 230b includes transistors 801b, 802b, and 803b connected in a stacked configuration. If the gain control circuit 110 does not perform attenuation, i.e. if the through path 310 is turned on, at least one or all of the transistors 801a, 802a and 803a comprised in the first part 230a are turned off and at least one or all of the transistors 801b, 802b and 803b comprised in the second part 230b are turned off. Conversely, if the gain control circuit 110 performs attenuation, i.e., if one of the attenuation paths 320-1 to 320-N is turned on, the transistors 801a, 802a, and 803a included in the first section 230a are turned on, and the transistors 801b, 802b, and 803b included in the second section 230b are turned on.

Fig. 9A is a diagram illustrating a configuration of a shunt unit of a gain control circuit according to various embodiments. Referring to fig. 9A, the shunt unit 240 includes a plurality of shunt paths 910-1 to 910-N.

One end of the plurality of shunt paths 910-1 to 910-N is grounded via a capacitor 920. The multiple shunt paths 910-1 to 910-N may form different impedance values. In each of the plurality of shunt paths 910-1 to 910-N, an impedance value may be formed using an on-resistance of a transistor. An example of an implementation of the multiple shunt paths 910-1 to 910-N may be as shown in fig. 9B.

Fig. 9B illustrates a diagram of an example of an implementation of a shunting unit of a gain control circuit, in accordance with various embodiments. The shunt unit 240 may be implemented as shown in fig. 9B. In this case, the example of implementation of fig. 9B does not limit the present disclosure, and the shunt unit 240 may be implemented differently. Fig. 9B shows a case where four shunt paths are implemented.

Referring to fig. 9B, first shunt path 910-1 forms an impedance value greater than impedance values of second shunt path 910-2, third shunt path 910-3, and fourth shunt path 910-4. The first shunt path 910-1 may include a transistor 911 and a transistor 912 connected in a stack structure. The sum of the on-resistance values of transistor 911 and transistor 912 may be greater than the on-resistance values of the other paths 910-2, 910-3, and 910-4.

Second shunt path 910-2 may form an impedance value that is less than the impedance value of first shunt path 910-1 and greater than the impedance values of third shunt path 910-3 and fourth shunt path 910-4. The second shunt path 910-2 may include a transistor 913 and a transistor 914 connected in a stacked configuration. The sum of the on-resistance values of the transistor 913 and the transistor 914 can be smaller than the on-resistance values of the transistor 911 and the transistor 912.

Third shunt path 910-3 may form an impedance value that is less than the impedance values of first shunt path 910-1 and second shunt path 910-2 and greater than the impedance value of fourth shunt path 910-4. Third shunt path 910-3 may include a transistor 915. The on-resistance value of the transistor 915 is smaller than the sum of the on-resistance values of the transistor 913 and the transistor 914.

Fourth shunt path 910-4 may form an impedance value that is less than the impedance values of first shunt path 910-1, second shunt path 910-2, and third shunt path 910-3. The fourth shunt path 910-4 may include a transistor 916. The on-resistance value of the transistor 916 may be smaller than the on-resistance value of the transistor 915.

In the structure shown in fig. 9B, transistors included in the same path can be controlled to be equivalently turned on/off. For example, to impose minimal gain variation, i.e., in the case of pass-through mode, at least one or all of transistors 911 and 912 in first shunt path 910-1 are turned off, at least one or all of transistors 913 and 914 in second shunt path 910-2 are turned off, transistor 915 in third shunt path 910-3 is turned off, and transistor 916 in fourth shunt path 910-4 is turned off. As another example, in the case of the attenuation mode, at least one of the first shunt path 910-1, the second shunt path 910-2, the third shunt path 910-3, and the fourth shunt path 910-4 is controlled to be in a conductive state.

As described in various embodiments, the on-resistance of the transistor may be used to form an impedance for attenuating the signal gain. In this case, a plurality of transistors connected in a stacked structure may be used. If a plurality of transistors are connected in a stack structure, an impedance corresponding to the sum of on-resistances of the plurality of transistors can be formed. If a single transistor having a constant on-resistance is used, a voltage difference may be generated between the source terminal and the drain terminal due to a decrease in gain. Therefore, the corresponding transistor may operate abnormally, and linearity may be deteriorated. Therefore, as described in the embodiment, if a plurality of transistors are connected in a stack structure and the transistors are turned on, a voltage difference between a source terminal and a drain terminal of each transistor is relatively low, and thus linearity may be improved.

Similarly, if the transistor is turned off, a reverse bias is applied by the bias providing unit 250, and linearity when the transistor is turned off can be improved. An example of applying a reverse bias may be as shown in fig. 10A and 10B.

Fig. 10A shows a diagram illustrating a reverse bias state of a transistor caused by a bias providing unit in a gain control circuit according to various embodiments; and fig. 10B shows a diagram illustrating a reverse bias state of a transistor caused by a bias providing unit in a gain control circuit according to various embodiments. Fig. 10A shows the transistor in an off state, and fig. 10B shows the transistor in an on state.

Referring to FIG. 10A, if V is to be_off(e.g., 0V) is applied to the gate terminal of transistor 1001, then transistor 1001 is turned off. Referring to FIG. 10B, if V is to be_on(e.g., 1.8V) is applied to the gate terminal of transistor 1001, and transistor 1001 is turned on. In this case, V is supplied through the bias supply unit 250_bias(e.g., 0.9V) is applied to the source and drain terminals. Due to V_biasV of transistor 1001_GSis-V_biasAnd transistor 1001 operates in a reverse bias state. Thus, when it is in contact with V_biasWhen compared with the case of 0, V_onNeeds to be increased by V_bias. For example, if the gate voltage required to turn on transistor 1001 (not reverse biased) is 0.9V, then transistor 1001 is turned on (reverse biased V)_bias) The required gate voltage is increased to 0.9+ V_bias。

Fig. 11 illustrates a diagram of an example of an implementation of a gain control circuit, in accordance with various embodiments. Fig. 11 is an example of an implementation of the gain control circuit 110, and shows an example of a circuit in which the path unit 210, the attenuation enabling unit 230, and the shunt unit 240 are combined, implemented as shown in fig. 3B, 8, and 9B. Referring to fig. 11, a plurality of control signals C are provided₀To C₉Each of which controls the switching operation of at least one transistor. Control signal C of gain mode defined according to attenuation₀To C₉The set values of (b) are shown in table 1 below.

[ Table 1]

Gain mode	Code	C0	C1	C2	C3	C4	C5	C6	C7	C8	C9
												-2	000	1	0	0	0	0	0	0	0	0	0
-5	001	0	1	0	0	0	1	1	0	0	0
												-8	010	0	0	1	0	0	1	0	1	0	0
-11	011	0	0	0	1	0	1	0	0	1	0
												-14	100	0	0	0	0	1	1	0	0	0	1

According to Table 1, in the mode corresponding to code 100, C₆、C₇And C₈Is set to 0. According to another embodiment, in the mode corresponding to code 100, C₆、C₇And C₈May be set to 1.

FIG. 12A shows a graph of performance of a gain control circuit in accordance with various embodiments; and fig. 12B is a graph of performance of a gain control circuit according to various embodiments. Fig. 12A and 12B show the input third-order intercept point (IIP3) of the variation of electric power according to the signal input to the gain control circuit 110.

Fig. 12A compares a case in which at least one of the path unit 210, the attenuation enabling unit 230, and the shunt unit 240 is configured with transistors connected in a stack structure with a case in which at least one of the path unit 210, the attenuation enabling unit 230, and the shunt unit 240 is configured with a single transistor that does not use a stack structure. Referring to fig. 12A, when a stack structure is used, it is recognized that the IIP3 is relatively high. For example, if the electrical power of the input signal is-30 dBm, the IIP3 may be increased by approximately 4 dB.

Fig. 12B compares the case where the reverse bias is used with the case where the reverse bias is not used. Referring to FIG. 12B, when reverse bias is used, the IIP3 is identified as being relatively high. For example, if the electrical power of the input signal is-40 dBm, the IIP3 may be increased by approximately 11 dB.

The method according to the embodiments described in the claims and/or the description of the present disclosure may be implemented in hardware, software, or a combination of hardware and software.

When the method is implemented by software, a computer-readable storage medium for storing one or more programs (software modules) may be provided. One or more programs stored in the computer-readable storage medium may be configured to be executed by one or more processors within the electronic device. The at least one program may include instructions for causing the electronic device to perform methods in accordance with various embodiments of the present disclosure as defined by the appended claims and/or disclosed herein.

The programs (software modules or software) may be stored in non-volatile memory including random access memory and flash memory, Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), magnetic disk storage devices, compact disk-ROM (CD-ROM), Digital Versatile Disks (DVD), or other types of optical storage devices or magnetic tape. Alternatively, any combination of some or all of them may form a memory storing a program. Furthermore, a plurality of such memories may be included in the electronic device.

In addition, the programs may be stored on AN attachable storage device accessible via a communication network, such as the Internet, AN intranet, a local area network (L AN), a Wide Area Network (WAN) and a Storage Area Network (SAN) or a combination thereof.

In the above detailed embodiments of the present disclosure, components included in the present disclosure are expressed in the singular or plural according to the presented detailed embodiments. However, for ease of description, the singular or plural forms are selected to be appropriate for the situation presented, and the various embodiments of the disclosure are not limited to a single element or a plurality of elements thereof. Further, a plurality of elements expressed in the description may be configured as a single element, or a single element in the description may be configured as a plurality of elements.

While the disclosure has been shown and described with reference to certain embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the disclosure. Therefore, the scope of the present disclosure should not be defined as limited to the embodiments, but should be defined by the appended claims and equivalents thereof.

While the present disclosure has been described with various embodiments, various changes and modifications may be suggested to one skilled in the art. The present disclosure is intended to embrace such alterations and modifications as fall within the scope of the appended claims.