阅读说明：本技术 形成半导体器件的方法 (Method of forming semiconductor device ) 是由 市川淳启 猪饲啓太 于 2020-01-07 设计创作，主要内容包括：本发明题为“形成半导体器件的方法”。在一个实施方案中,一种用于高侧驱动器的控制电路形成交替信号以控制存储模式和保持模式。该控制电路的实施方案存储大于输入电压的电压,这导致对于所述周期中的一个周期的至少一部分存储大量电荷。该电荷用对于所述周期中的另一周期的至少一部分向该驱动器供应操作电压。(The invention provides a method for forming a semiconductor device. In one embodiment, a control circuit for a high-side driver forms an alternating signal to control a storage mode and a hold mode. Embodiments of the control circuit store a voltage greater than the input voltage, which results in a large amount of charge being stored for at least a portion of one of the cycles. The charge supplies an operating voltage to the driver for at least a portion of another of the cycles.)

1. A control circuit for a high-side driver, comprising:

a control circuit configured to form a first signal to control a high-side transistor and to form a second signal to control a low-side transistor to form an output voltage from a high voltage;

a first input for receiving said high voltage;

a second input for receiving an input voltage less than the high voltage;

a first capacitor;

a second capacitor;

a first driver coupled to receive the first signal and configured to enable the high-side transistor in response to an asserted state of the first signal;

a second driver coupled to receive the second signal and configured to enable the low-side transistor in response to an assertion state of the second signal;

a voltage generation circuit configured to form a plurality of storage periods for at least a portion of the asserted state of the second signal, a first storage period of the plurality of storage periods comprising alternately storing substantially the input voltage on the first capacitor for a first portion of the first storage period to store a first charge on the first capacitor, and subsequently coupling the first capacitor in series with the input voltage for a second portion of the first storage period to form a second charge and a second voltage on the second capacitor; and is

The voltage generation circuit is configured to form a plurality of hold cycles for at least a portion of the assertion state of the first signal, a first hold cycle of the plurality of hold cycles comprising coupling the first capacitor in series between the second capacitor and the high voltage for a first portion of the first hold cycle, and then substantially storing the input voltage on the first capacitor to store the first charge on the first capacitor for a second portion of the first hold cycle.

2. The voltage generation circuit of claim 1, wherein the control circuit is configured to: continuing to form the storage period in response to asserting the second signal for at least a portion of an interval during which the first signal remains inactive.

3. The voltage generation circuit of claim 1 wherein the voltage generation circuit comprises a first transistor coupled to a first terminal of the first capacitor, and wherein the control circuit enables the first transistor to couple the first capacitor in series between the input voltage and a common reference voltage to store the first charge on the first capacitor.

4. The voltage generation circuit of claim 3 wherein the voltage generation circuit includes a second transistor coupled to the first terminal of the first capacitor and further coupled to receive the high voltage, wherein the control circuit enables the second transistor to couple the first capacitor in series between the second capacitor and the high voltage for the first portion of the first retention period.

5. A method of forming a control circuit for a high-side driver, comprising:

configuring the control circuit to control the first driver to operate the first switch and to control the second driver to operate the second switch to form the output voltage from the first voltage;

configuring the control circuit to receive an input voltage and form an operating voltage for the second driver from the input voltage;

configuring the control circuit to store a temporary voltage on a first capacitor, the temporary voltage being no less than substantially twice the input voltage, wherein the control circuit is configured to store the temporary voltage on the first capacitor for at least a portion of a first time interval in which the second switch is enabled;

configuring the control circuit to couple the first capacitor to supply current and voltage to operate the first driver in response to controlling the first driver to enable the first switch, wherein the first capacitor is substantially referenced to the output voltage; and

configuring the control circuit to: coupling a second capacitor in series between the first voltage and the first capacitor to supply current and voltage to the first driver for a second time interval in which the first driver is controlled to enable the first switch, and then charging a second capacitor from the input voltage for a third time interval in which the first driver is controlled to enable the first switch.

6. The method of claim 5, wherein configuring the control circuit to store the temporary voltage on the first capacitor for a sequence comprises configuring the control circuit to: coupling the second capacitor to be charged substantially to the input voltage for a first portion of the first time interval and then coupling between the input voltage and the second capacitor to store the temporary voltage on the first capacitor for a second portion of the first time interval.

7. The method of claim 6, further comprising configuring the control circuit to repeat the sequence continuously for the first time interval.

8. A method of forming a semiconductor device, comprising:

configuring the control circuit to control the first driver to operate the first switch and to control the second driver to operate the second switch to form the output voltage from the first voltage;

configuring an input of the control circuit to receive an input voltage;

configuring the control circuit to form a temporary voltage greater than the input voltage, including forming the temporary voltage for at least a portion of a first time interval in which the second switch is enabled, wherein the temporary voltage is formed by the input voltage; and

configuring the control circuit to couple the first driver to substantially receive the temporary voltage to supply current and voltage to operate the first driver in response to controlling the first driver to enable the first switch.

9. The method of claim 8, further comprising:

configuring the control circuit to: forming a second voltage that is substantially the input voltage for at least a first portion of a second time interval during which the first driver is controlled to enable the first switch, and then coupling the second voltage in series between the first voltage and a power input of the first driver to supply voltage and current to the first driver for a second portion of the second time interval.

10. The method of claim 8, wherein configuring the control circuit to form the temporary voltage comprises configuring the control circuit to form a sequence to charge a first capacitor substantially to the input voltage and then to couple the first capacitor in series between the input voltage and a second capacitor to store the temporary voltage on the second capacitor,

wherein the control circuit repeats the sequence continuously for the first time interval.

Background

The present invention relates generally to electronic devices and, more particularly, to semiconductors, semiconductor structures, and methods of forming semiconductor devices.

In the past, the semiconductor industry utilized various circuits and methods to control switches or transistors configured in an H-bridge or half-H-bridge configuration. These types of configurations are commonly used in a variety of applications, including power supply controllers, boost mode power supply controllers, motor drivers, and other circuits. The control circuit typically requires a high voltage to enable one or more high-side transistors of an H-bridge or half-H-bridge configuration. For example, N-channel transistors typically require higher voltages.

Some control circuits utilize a bootstrap circuit to provide the high voltage. Some other circuits utilize charge pump circuits to generate the high voltage. Both of these configurations typically require an external capacitor because the capacitor must have a large value in order to supply sufficient current to drive the transistor. In some embodiments, capacitors are integrated onto semiconductor devices, which occupy a large area on the semiconductor device and add additional cost to the semiconductor device.

Furthermore, bootstrap circuit configurations often fail to enable the high-side transistor at a substantially 100% duty cycle.

It is therefore desirable to have a circuit and method that generates the high voltage required to enable the transistor, that can be provided at a substantially 100% duty cycle, that can use a smaller value capacitor, that occupies less area of the semiconductor device, and/or that reduces noise generated by electromagnetic interference.

Disclosure of Invention

According to an aspect of the present disclosure, there is provided a control circuit for a high-side driver, including:

a control circuit configured to form a first signal to control a high-side transistor and to form a second signal to control a low-side transistor to form an output voltage from a high voltage;

a first input for receiving said high voltage;

a second input for receiving an input voltage less than the high voltage;

a first capacitor;

a second capacitor;

a first driver coupled to receive the first signal and configured to enable the high-side transistor in response to an asserted state of the first signal;

a second driver coupled to receive the second signal and configured to enable the low-side transistor in response to an assertion state of the second signal;

a voltage generation circuit configured to form a plurality of storage periods for at least a portion of the asserted state of the second signal, a first storage period of the plurality of storage periods comprising alternately storing substantially the input voltage on the first capacitor for a first portion of the first storage period to store a first charge on the first capacitor, and subsequently coupling the first capacitor in series with the input voltage for a second portion of the first storage period to form a second charge and a second voltage on the second capacitor; and is

The voltage generation circuit is configured to form a plurality of hold cycles for at least a portion of the assertion state of the first signal, a first hold cycle of the plurality of hold cycles comprising coupling the first capacitor in series between the second capacitor and the high voltage for a first portion of the first hold cycle, and then substantially storing the input voltage on the first capacitor to store the first charge on the first capacitor for a second portion of the first hold cycle.

In some embodiments, the control circuitry is configured to: continuing to form the storage period in response to asserting the second signal for at least a portion of an interval during which the first signal remains inactive.

In some embodiments, the voltage generation circuit includes a first transistor coupled to a first terminal of the first capacitor, and wherein the control circuit enables the first transistor to couple the first capacitor in series between the input voltage and a common reference voltage to store the first charge on the first capacitor.

In some embodiments, the voltage generation circuit includes a second transistor coupled to the first terminal of the first capacitor and further coupled to receive the high voltage, wherein the control circuit enables the second transistor to couple the first capacitor in series between the second capacitor and the high voltage for the first portion of the first retention period.

According to an aspect of the present disclosure, there is provided a method of forming a control circuit for a high-side driver, comprising:

configuring the control circuit to control the first driver to operate the first switch and to control the second driver to operate the second switch to form the output voltage from the first voltage;

configuring the control circuit to receive an input voltage and form an operating voltage for the second driver from the input voltage;

configuring the control circuit to store a temporary voltage on a first capacitor, the temporary voltage being no less than substantially twice the input voltage, wherein the control circuit is configured to store the temporary voltage on the first capacitor for at least a portion of a first time interval in which the second switch is enabled;

configuring the control circuit to couple the first capacitor to supply current and voltage to operate the first driver in response to controlling the first driver to enable the first switch, wherein the first capacitor is substantially referenced to the output voltage; and

configuring the control circuit to: coupling a second capacitor in series between the first voltage and the first capacitor to supply current and voltage to the first driver for a second time interval in which the first driver is controlled to enable the first switch, and then charging a second capacitor from the input voltage for a third time interval in which the first driver is controlled to enable the first switch.

In some embodiments, configuring the control circuitry to store the temporary voltage on the first capacitor for a sequence comprises configuring the control circuitry to: coupling the second capacitor to be charged substantially to the input voltage for a first portion of the first time interval and then coupling between the input voltage and the second capacitor to store the temporary voltage on the first capacitor for a second portion of the first time interval.

In some embodiments, the method further comprises configuring the control circuit to repeat the sequence continuously for the first time interval.

According to an aspect of the present disclosure, there is provided a method of forming a semiconductor device, including:

configuring the control circuit to control the first driver to operate the first switch and to control the second driver to operate the second switch to form the output voltage from the first voltage;

configuring an input of the control circuit to receive an input voltage;

configuring the control circuit to form a temporary voltage greater than the input voltage, including forming the temporary voltage for at least a portion of a first time interval in which the second switch is enabled, wherein the temporary voltage is formed by the input voltage; and

configuring the control circuit to couple the first driver to substantially receive the temporary voltage to supply current and voltage to operate the first driver in response to controlling the first driver to enable the first switch.

In some embodiments, the method further comprises:

configuring the control circuit to: forming a second voltage that is substantially the input voltage for at least a first portion of a second time interval during which the first driver is controlled to enable the first switch, and then coupling the second voltage in series between the first voltage and a power input of the first driver to supply voltage and current to the first driver for a second portion of the second time interval.

In some embodiments, configuring the control circuit to form the temporary voltage includes configuring the control circuit to form a sequence to charge a first capacitor substantially to the input voltage and then to couple the first capacitor in series between the input voltage and a second capacitor to store the temporary voltage on the second capacitor,

wherein the control circuit repeats the sequence continuously for the first time interval.

Drawings

Fig. 1 schematically illustrates an example of a portion of an embodiment of a half H-bridge circuit including a control circuit according to the present invention;

FIG. 2 is a diagram having graphs showing some of the signals that may be generated during operation of an embodiment of the circuit of FIG. 1 in accordance with the present invention;

FIG. 3 shows a flow chart with steps illustrating some of the modes of the circuit of FIG. 1 in accordance with the present invention; and is

Fig. 4 shows an enlarged plan view of a semiconductor device including the circuit of fig. 1 according to the present invention.

Elements in the figures are not necessarily to scale, some elements may be exaggerated for illustrative purposes and, unless otherwise specified, like reference numerals in different figures denote like elements. Moreover, descriptions and details of well-known steps and elements may be omitted for simplicity of the description. As used herein, current carrying element or current carrying electrode means an element of a device that carries current through the device, such as a source or drain of an MOS transistor or an emitter or collector of a bipolar transistor or a cathode or anode of a diode, while a control element or control electrode means an element of a device that controls current through the device, such as a gate of an MOS transistor or a base of a bipolar transistor. In addition, one current carrying member may carry current through the device in one direction, such as carrying current into the device, while a second current carrying member may carry current through the device in the opposite direction, such as carrying current out of the device. Although the devices may be described herein as certain N-channel or P-channel devices or certain N-type or P-type doped regions, one of ordinary skill in the art will appreciate that complementary devices according to the present invention are also possible. It is understood by those of ordinary skill in the art that conductivity type refers to the mechanism by which conduction occurs, such as through holes or electrons, and thus, conductivity type does not refer to the doping concentration but to the doping type, such as P-type or N-type. It will be understood by those skilled in the art that the terms "during … …", "at … … simultaneously", and "when … …" as used herein in relation to circuit operation do not mean exactly that an action is said to occur immediately after the action is initiated, but that there may be some minor but reasonable delay, such as various propagation delays, between the reactions initiated by the initial action. Additionally, the term "simultaneously at … …" means that some action occurs at least for a period of time during the duration of the trigger action. Use of the word "approximately" or "substantially" means that the value of an element has a parameter that is expected to be close to the stated value or position. However, as is well known in the art, there are always minor differences that prevent a value or position from being exactly the stated value or position. It is recognized in the art that deviations of up to at least ten percent (10%) (and up to twenty percent (20%) for some components including semiconductor dopant concentrations) are reasonable deviations from the ideal target exactly as described. When used with respect to signal states, the term "active" means an active state of a signal, and the term "inactive" means an inactive state of a signal. The actual voltage value or logic state of a signal (such as a "1" or "0") depends on whether positive or negative logic is used. Thus, if positive logic is used, high voltage or high logic may be in effect, and if negative logic is used, low voltage or low logic may be in effect; whereas a low voltage or low state may fail if positive logic is used, and a high voltage or high logic may fail if negative logic is used. In this context, a positive logic convention is used, but those skilled in the art will appreciate that a negative logic convention may also be used. The terms "first," "second," "third," and the like in the claims and/or in the detailed description, as used in portions of the names of elements, are used for distinguishing between similar elements and not necessarily for describing a sequential or chronological order, spatial order, hierarchical order, or any other order. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments described herein are capable of operation in other sequences than described or illustrated herein. Reference to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrase "in one embodiment" appearing in various places throughout the specification are not necessarily all referring to the same embodiment, but in some instances may. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments, as would be apparent to one of ordinary skill in the art.

The embodiments illustrated and described as appropriate below may lack any elements not specifically disclosed herein and/or may be practiced in the absence of any element not specifically disclosed herein.

Detailed Description

Fig. 1 schematically shows an example of a portion of an embodiment of a half H-bridge circuit 10 including a control circuit 19. Circuit 19 is configured to alternately drive a high-side switch (such as, for example, transistor 11) and a low-side switch (such as, for example, transistor 12) to form an output Voltage (VO) on output 16. These switches (such as, for example, transistor 11 and transistor 12) may be connected in a half H-bridge configuration, such as connected together in series in a stacked configuration. One embodiment may include: switches (such as, for example, transistor 11 and transistor 12) are connected together at a bridge node 13. In some embodiments, output 16 may be connected to node 13. In some embodiments, transistors 11-12 and node 13 may be included as part of circuit 19 or may be included within the circuit. Circuit 10 receives an operating voltage or input voltage (Vin) between a voltage input 14 and a common return 15. In some embodiments, return 15 may be connected to receive a common reference voltage. In one embodiment, the common reference voltage may be a ground reference voltage. The input voltage received on input 14 is typically a value for operating circuitry 19 and some of its elements. In some embodiments, the input voltage may be about five volts (5V), in other embodiments about three volts (3V), or less.

Circuit 10 also receives a High Voltage (HV) on High Voltage (HV) input 18 that is received through transistor 11. This High Voltage (HV) is typically much greater than the voltage received on input 14. In one embodiment, the input voltage may be substantially no greater than the high voltage or about equal to the high voltage. One embodiment may include: the high voltage may be less than the input voltage. One embodiment may include: this high voltage may be twice the voltage on input 14, and may be greater in other embodiments. In one embodiment, the high voltage may be about twelve volts (12V) or about twenty four volts (24V), or greater.

Circuit 19 includes a high-side driver circuit or driver 21 coupled to drive a high-side switch, such as, for example, transistor 11, and a low-side driver circuit or driver 20 configured to drive a low-side switch, such as, for example, transistor 12. Because driver 20 is driving transistor 12, and in one embodiment, is referenced to a common reference voltage, driver 20 is able to be operated from a lower operating voltage than driver 21. Driver 20 may have an embodiment that receives the operating voltage received from input 14 as the operating voltage of driver 20. However, the driver 21 requires a higher operating voltage to generate a higher drive voltage to enable the transistor 11. For example, embodiments of transistor 11 may be referenced to output 16 or node 13. Driver 21 receives the higher operating voltage from node 23. In some embodiments, this higher operating voltage may be referred to as a bootstrap voltage.

The circuit 19 includes a voltage generation circuit 30 configured to form a bootstrap voltage for operating the driver 21. As will be seen further below, either circuit 19 or circuit 30 is configured to operate alternately in a storage mode and a retention mode. In the storage mode, circuitry 19 is configured to store charge that will supply current to driver 21 and contribute to forming a bootstrap voltage. In the hold mode, the circuit 19 is configured to supply a bootstrap voltage and supply a hold current to the driver 21. The circuit 19 also includes a capacitor 26 that may assist in supplying the bootstrap voltage to the driver 21. Embodiments of circuit 30 may also include a diode 27 to help form the bootstrap voltage.

Circuit 30 includes a charging circuit 40 and a storage circuit 32. Circuit 30 also includes a pass circuit that includes pass transistor 51, transistor 53, and resistors 54-55. Charging circuit 40 includes transistor 45, transistors 46 and 47, and flying capacitor 43. In some implementations, transistor 47 has a high breakdown voltage, such as a high drain-to-source breakdown voltage. For example, the breakdown voltage of transistor 47 may be higher than the voltage received from input 18. Exemplary embodiments may include: transistor 47 may have a drain-to-source breakdown voltage of at least forty volts (40V). One embodiment may include: transistor 45 and transistor 46 may also have a high breakdown voltage. In one embodiment, transistor 47 may have a higher breakdown voltage than transistors 45-46. Circuit 40 may also include a blocking diode 41, a blocking diode 48, and a blocking diode 49. The storage circuit 32 may have a storage capacitor 33 and may have an optional diode 35 and a diode 36. Circuit 30 may have an embodiment in which the capacitance of capacitor 33 is greater than the capacitance of capacitor 43. In one embodiment, diodes 35 and 36 may help protect capacitor 33 from excessive voltages. One embodiment may include: the diode 35 and the diode 36 may be zener diodes.

A controller or control circuit 68 of circuit 19 generates control signals to control transistors 11-12 and also control circuit 40. For example, transistors 45-47 are controlled.

Fig. 2 is a diagram with graphs showing some of the signals that may be generated during operation of an embodiment of circuit 19, the abscissa shows time, the ordinate shows an increasing value of the shown signals, graph 61 shows a high side control (H) signal for enabling transistor 11, and graph 62 shows a low side control (L) signal for enabling transistor 12.

Graph 63 shows the P1 control signal for enabling transistor 45, graph 64 shows the P2 control signal for enabling transistor 46, and graph 65 shows the P3 control signal for enabling transistor 47. For simplicity of explanation, signals P1-P3 are shown as having an active state illustrated as a high or positive level. However, in one embodiment, transistors 45 and 47 are P-channel transistors that are enabled when the corresponding control signals are at a lower level, and therefore, inverter 66 and inverter 67 are employed to invert signals P1 and P3 in order to enable transistors 45 and 47. Those skilled in the art will recognize that in some embodiments, the P1 control signal and the P3 control signal may be inverted and inverters 66 and 67 may be omitted, or these transistors may be other types of transistors. This description makes reference to fig. 1 to 2.

To facilitate operation, circuit 68 is configured to operate transistors 45-47 at a frequency higher than the frequency at which transistors 11 and 12 are operated. In one exemplary embodiment, transistors 45-47 may be enabled at frequencies greater than one (1) MHz. In other embodiments, the frequency may be at least six (6) MHz. In one embodiment, transistors 11-12 may be operated at frequencies below approximately one hundred (100) KHz. One embodiment may include: transistors 11-12 may be operated at a frequency of approximately twenty (20) KHz.

In the storage mode, circuit 19 is configured to operate circuit 40 to form a temporary charge on capacitor 33. For at least a portion of the time interval during which the low-side transistor 12 is enabled and the high-side transistor 11 is disabled, the control circuit 68 operates the transistors 45-47 to cause the circuit 40 to operate in the storage mode to store charge on the capacitor 33 as temporary charge. For example, circuit 68 may form a plurality of storage periods such that each storage period alternately enables transistor 45 and transistor 46 to store charge while transistor 12 is enabled and transistor 11 is disabled. During a memory cycle, transistors 45 and 46 may be alternately enabled mutually exclusively, wherein both transistors 45 and 46 are not enabled at the same time. This situation may also be referred to as being enabled out of phase with each other.

For example, assume at time T0 that the L signal is a high signal, causing transistor 12 to be enabled, and the H signal is a low signal, causing transistor 11 to be disabled at time T0, deactivating signal P1 and signal P3 and asserting signal P2, thus transistor 45 and transistor 47 are disabled and transistor 46 is enabled, enabling transistor 46 causes current to flow from input 14 through diode 48 to capacitor 43 and through transistor 46, thereby charging capacitor 43, the voltage stored on capacitor 43 is substantially the input voltage or the input voltage minus a voltage drop of diode 48, in one embodiment, the input voltage may be about five volts (5V), and the voltage stored on capacitor 43 may be about four and one-half volts (4.5V), storing the voltage on capacitor 43 results in storing charge on capacitor 43, at time T1, circuit 30 transistor 46 and enabling transistor 45, for example, circuit 68 may then deactivate signal P2, and cause the signal P68 to be stored on capacitor 33, thus, and thus, be configured to be stored across the temporarily enabled for a period of one time T33, thus, the temporarily storing the voltage on capacitor 33, resulting in a period of the temporarily enabled, stored voltage, which is about one voltage stored on capacitor 33.9, thus, and the temporarily stored on the temporarily capacitor 33, thus, resulting in the temporarily enabling transistor 33, and the temporarily storing the voltage stored on the temporarily capacitor 33, which is caused by the temporarily stored on the temporarily capacitor 33, thus, which is caused by the temporarily storing the temporarily capacitor 33, which is caused by the temporarily storing the temporarily capacitor 33, which is caused by the temporarily storing the temporarily enabling transistor 33, which is caused by the temporarily storing the temporarily capacitor 33, which is caused by the voltage of the temporarily storing the voltage of one of the voltage of the temporarily storing the voltage of the.

Next at time T2, circuit 30 begins another storage cycle and capacitor 43 is charged again by disabling transistor 45 and then enabling transistor 46. Circuit 30 next enables transistor 45 to again store the temporary voltage and charge on capacitor 33. The storage period of charging of capacitor 43 followed by storage of charge on capacitor 33 is repeated as transistor 45 and transistor 46 are alternately enabled during the time interval that transistor 12 is enabled and transistor 11 is disabled. Those skilled in the art will appreciate that the capacitor 33 may not be fully charged to the temporary charge or voltage during the first storage period in which the transistor 45 is enabled, but rather the voltage or charge stored on the capacitor 33 steadily increases to the temporary charge or voltage over several storage periods.

Since the H signal is deactivated, transistor 53 is disabled, which results in transistor 51 being disabled. Thus, during the storage mode, the charge on capacitor 33 is not coupled to capacitor 26.

Subsequently at time T3, circuit 19 disables transistor 12 while transistor 11 is disabled. In one embodiment, circuit 30 also ceases to operate in the storage mode, thereby ceasing to alternately switch transistor 45 and transistor 46, as illustrated by deactivating signal P1 and asserting signal P2 at time T3.

During the storage mode, the capacitor 33 is charged to a voltage value that is substantially twice the input voltage on the input 14, which results in a temporary charge being stored on the capacitor. In one embodiment, the voltage at node 34 also increases. Since the capacitor 33 is charged to a voltage substantially twice the input voltage, the charge stored on the capacitor 33 corresponds to the charge stored on the capacitor having twice the capacitance of the capacitor 33 and charged to the input voltage. This sequence of charging the capacitor 33 to a voltage greater than the input voltage therefore stores a large amount of charge on the capacitor 33 and facilitates the use of a smaller capacitance value to obtain the amount of charge required to subsequently supply current to the driver 21. Using a smaller capacitance value reduces the cost of the semiconductor device on which the circuit 19 is formed.

At time T4, circuit 19 controls driver 21 to enable transistor 11, for example, circuit 68 may assert the H signal to enable transistor 11 and may also hold L signal inactive to keep transistor 12 disabled Note that there is a non-overlapping time interval (from time T3 to time T4) between transistor 12 being disabled and transistor 11 being enabled to minimize shoot-through current and avoid damaging transistor 11 and transistor 12. during this non-overlapping time interval, transistor 45 and transistor 47 are disabled, transistor 46 is enabled, and both the storage mode and the retention mode are disabled.

For at least a portion of the time interval during which transistor 11 is enabled and transistor 12 is disabled, circuit 19 is configured to operate in a hold mode to supply a bootstrap voltage and a hold current to driver 21. For example, circuitry 19 may be configured to begin operating in hold mode at time T4 or just after T4. In one embodiment, controlling driver 21 to enable transistor 11 results in the temporary charge or voltage stored on capacitor 33 being coupled as a bootstrap voltage to driver 21 and supplying current for operating driver 21 during the enabling of transistor 11. In one embodiment, asserting the H signal to enable transistor 11 may also enable transistor 53, which pulls the gate of transistor 51 low to enable transistor 51, coupling node 23 to both node 34 and capacitor 33. Thus, circuit 30 connects capacitor 33 to supply temporary charge and voltage to driver 21 to help enable transistor 11. Since the capacitor 33 is referenced to the output section 16, the voltage from the capacitor 33 is added to the output voltage (Vo) on the output section 16, thereby becoming a bootstrap voltage at the node 23 for operating the driver 21. Those skilled in the art will recognize that because transistor 11 is enabled, the output voltage (Vo) is substantially the High Voltage (HV) from input 18, and thus capacitor 33 is substantially referenced to the High Voltage (HV). In addition, some of the temporary charge from the capacitor 33 is transferred to the capacitor 26, so that the capacitor 26 can contribute to supply a holding current to the driver 21.

During the hold mode, circuit 68 may be configured to control transistors 45-47 to continue supplying the bootstrap voltage and hold current to driver 21. For at least a portion of the time interval during which transistor 11 is enabled and transistor 12 is disabled, circuit 68 forms a plurality of hold periods such that each hold period alternately enables transistor 46 and transistor 47 to store charge on capacitor 43 and supply a bootstrap voltage and hold current to driver 21. In the holding period, the transistors 46 and 47 may be alternately enabled mutually exclusively, wherein both the transistors 46 and 47 are not enabled at the same time, so as to be out of phase with each other.

At time T4 or just after T4, circuit 19 may be configured to enable transistor 47. Enable transistor 47 couples the High Voltage (HV) from input 18 in series with capacitor 43 and applies a bootstrap voltage to node 23 that is substantially the High Voltage (HV) plus the voltage stored on capacitor 43. Because transistor 11 is enabled and a High Voltage (HV) is being applied to output 16, driver 21 is referenced to the High Voltage (HV) on output 16. Since the voltage from the capacitor 43 is also coupled to the HV, the capacitor 43 is also referenced to the HV, so the voltage on the capacitor 43 becomes the bootstrap voltage for operating the driver 21, and the capacitor 43 also supplies the holding current. For example, a terminal of the capacitor 43 is connected to the HV through the transistor 47, and a second terminal of the capacitor 43 is connected to the capacitor 33 through the diode 41, and is also connected to the power input terminal of the driver 21 through the transistor 51. In one embodiment, diode 48 blocks the input voltage and allows coupling capacitor 43 to the HV. Since capacitor 33 and capacitor 26 are also coupled to HV on output 16, some of the charge from capacitor 43 may also be transferred to capacitor 33 and capacitor 26.

At time T5, circuit 19 disables transistor 47 and enables transistor 46, thereby again substantially charging capacitor 43 to the voltage from input 14. For this portion of the hold period, the capacitor 33 and the capacitor 26 supply a hold current and a bootstrap voltage to operate the driver 21 during this portion of the hold period. This hold period of storing charge on capacitor 43 and then referencing capacitor 43 to this HV to supply the bootstrap voltage and hold current to driver 21 is continuously repeated during at least a portion of the interval that transistor 11 is enabled and transistor 12 is disabled.

At time T6, circuit 68 controls driver 21 to disable transistor 11. For example, circuit 68 may disable the H signal to begin disabling transistor 11 at least while transistor 12 is disabled. The storage mode remains disabled because transistor 11 and transistor 12 are disabled, circuit 19 also stops the hold mode and no longer alternately charges capacitor 43 and supplies hold current.

At time T7, circuit 68 controls driver 20 to enable transistor 12. for example, circuit 68 may again assert the L signal to enable transistor 12 while transistor 11 is disabled it is noted that there is a time interval between disabling transistor 11 and enabling transistor 12 during which transistors 45-47 are not alternately switched.

One skilled in the art will recognize that embodiments may include: circuit 19 or circuit 30 may be configured to continue forming a storage cycle (and thus, operate in a storage mode) after controlling driver 20 to disable transistor 12 and before controlling driver 21 to enable transistor 11.

Those skilled in the art will also recognize that the respective diodes 41 and 48 may be replaced by transistors that are controlled to be enabled for a portion of the time interval during which transistors 45 and 46 are respectively enabled.

FIG. 3 shows a flowchart 110 with steps illustrating some of the modes of circuitry 19 (FIG. 1). At step 111, circuit 19 controls driver 20 to enable transistor 12 after transistor 11 is disabled, or circuit 30 operates in a storage mode to form a plurality of storage cycles. The hold mode is disabled. At step 112, circuit 19 controls driver 20 to disable transistor 12 and transistor 11 remains disabled, and circuit 19 disables operation of both the storage mode and the retention mode. Alternative embodiments may include: circuitry 19 continues to operate in the storage mode for step 112. At step 113, circuit 19 controls driver 21 to enable transistor 11 and transistor 12 remains disabled, and either circuit 19 or circuit 30 operates in a hold mode to form a plurality of hold periods. But the storage mode remains disabled. At step 114, circuit 19 controls driver 21 to disable transistor 11 and transistor 12 remains disabled, and either circuit 19 or circuit 30 disables operation in the retention mode and continues to disable operation in the storage mode.

To facilitate the operations and functions described above, input 18 is connected to the source of transistor 47 and the drain of transistor 11. input 14 is commonly connected to the anode of diode 27, the anode of diode 48, and the source of transistor 45. the cathode of diode 48 is commonly connected to the first terminal of capacitor 43 and the anode of diode 41. the cathode of diode 41 is commonly connected to the cathode of diode 35, node 34, the first terminal of capacitor 33, the first terminal of resistor 54, and the source of transistor 51. the drain of transistor 51 is commonly connected to the first terminal of capacitor 26, node 23, the cathode of diode 27, the power input of driver 21, and the cathode of diode 24. the power return terminal of driver 21 is commonly connected to output 16, the anode of diode 24, the second terminal of capacitor 26, the source of transistor 53, the second terminal of capacitor 33, and the anode of diode 36. the cathode of diode 36 is connected to the anode of diode 35. the second terminal of transistor 55 is commonly connected to the gate of transistor 54 and the gate of the transistor 35. the gate of the transistor 35 is connected to the gate of the input circuit of the transistor 35. the transistor 35, the gate of the transistor 35 is connected to the gate of the input circuit of the transistor 35, the transistor 35 is connected to the gate of the transistor 35, the gate of the transistor 23 is connected to the gate of the transistor 35, and the gate of the transistor 23 is connected to the gate of the transistor 35 is connected to the transistor 35, the gate of the transistor 35 is connected to the gate of the transistor 35, and the transistor connected to the gate of the transistor connected to the transistor 35, and the gate of the transistor connected to the transistor 35, and the transistor connected to the gate of the transistor 35, and the gate of the transistor connected to the gate of the transistor connected to the transistor 35, and the transistor connected to the gate of the transistor connected to the transistor 35, and the gate of the transistor.

Fig. 4 shows an enlarged plan view of a portion of an embodiment of a semiconductor device or integrated circuit 116 formed on a semiconductor die 117. In one embodiment, circuit 19 or circuit 30 may be formed on die 117. Die 117 may also include other circuitry not shown in fig. 4 to simplify the drawing. Circuitry or integrated circuit 19 may be formed on die 117 by semiconductor fabrication techniques known to those skilled in the art.

From all of the foregoing, those skilled in the art will recognize that examples of implementations of control circuits for high-side drivers may include:

a control circuit (such as, for example, circuit 19) configured to form a first signal (such as, for example, an H signal) to control a high-side transistor (such as, for example, transistor 11) and to form a second signal (such as, for example, an L signal) to control a low-side transistor (such as, for example, transistor 12) to form an output voltage (such as, for example, on output 16) from a high voltage (such as, for example, HV on input 18);

a first input (such as, for example, input 18) for receiving the high voltage;

a second input (such as, for example, input 14) for receiving an input voltage (such as, for example, a Vin voltage) that is less than the high voltage;

a first capacitor (such as, for example, capacitor 43);

a second capacitor (such as, for example, capacitor 33);

a first driver (such as, for example, driver 21) coupled to receive the first signal and configured to enable the high-side transistor in response to an asserted state of the first signal;

a second driver (such as, for example, driver 20) coupled to receive the second signal and configured to enable the low-side transistor in response to an assertion state of the second signal;

a voltage generation circuit (such as, for example, circuit 30) configured to form a plurality of storage periods for at least a portion of the asserted state of the second signal, a first storage period of the plurality of storage periods comprising alternately substantially storing the input voltage on the first capacitor to store a first charge on the first capacitor for a first portion of the first storage period, and subsequently coupling the first capacitor in series with the input voltage to form a second charge on the second capacitor and a second voltage for a second portion of the first storage period; and is

The voltage generation circuit is configured to form a plurality of hold periods for at least a portion of the asserted state of the first signal, a first hold period of the plurality of hold periods including coupling the first capacitor in series between the second capacitor and the high voltage for a first portion of the first hold period, and then substantially storing an input voltage on the first capacitor to store the first charge on the first capacitor for a second portion of the first hold period.

One embodiment may include: the voltage generation circuit may be configured to couple the second capacitor to the first driver in response to asserting the first signal.

In one embodiment, the voltage generation circuit may include a second capacitor to which at least a portion of the first charge is transferred for a second portion of the first storage period.

In one embodiment, the control circuit may be configured to inhibit the formation of both the storage period and the retention period in response to disabling both the first signal and the second signal.

One embodiment may include: the control circuit may be configured to continue to form the memory cycle for at least a portion of the interval that the first signal remains inactive in response to asserting the second signal.

The voltage generation circuit may have an embodiment wherein the control circuit includes a first transistor (such as, for example, transistor 47) coupled to a first terminal of a first capacitor and also coupled to receive the high voltage, wherein the control circuit enables the first transistor to couple the first capacitor in series between a second capacitor and the high voltage for a first portion of a first retention period.

One embodiment may include a first transistor (such as, for example, transistor 46) coupled to a first terminal of a first capacitor, and wherein the control circuit enables the first transistor to couple the first capacitor in series between the input voltage and a common reference voltage to store a first charge on the first capacitor.

In one embodiment, a second transistor (such as, for example, transistor 47) may be coupled to the first terminal of the first capacitor and also coupled to receive the high voltage, wherein the control circuit enables the second transistor to couple the first capacitor in series between the second capacitor and the high voltage for a first portion of a first retention period.

Another embodiment may include a second transistor (such as, for example, transistor 51) coupled to a first terminal of a second capacitor and also coupled to a power input of the first driver, wherein the voltage generation circuit enables the second transistor to couple the second capacitor to supply current to the first driver in response to asserting the first signal.

One skilled in the art will recognize that an example of a method of forming a control circuit for a high-side driver may include:

configuring the control circuit (such as, for example, circuit 19) to control a first driver (such as, for example, driver 21) to operate a first switch (such as, for example, 11) and to control a second driver (such as, for example, driver 20) to operate a second switch (such as, for example, a switch of transistor 12) to form an output voltage (such as, for example, a voltage on output 16) from a first voltage (such as, for example, HV);

the control circuit is configured to receive an input voltage (such as, for example, a voltage on input 14) and form therefrom an operating voltage for the second driver;

configuring the control circuit to store a temporary voltage on a first capacitor (such as, for example, capacitor 33), the temporary voltage being no less than substantially twice the input voltage, wherein the control circuit is configured to store the temporary voltage on the first capacitor for at least a portion of a first time interval during which a second switch is enabled;

configuring the control circuit to couple the first capacitor to supply a current and a voltage to operate the first driver in response to controlling the first driver to enable the first switch, wherein the first capacitor is substantially referenced to the output voltage; and is

The control circuit is configured to couple a second capacitor (such as, for example, capacitor 43) in series between the first voltage and the first capacitor to supply current and voltage to the first driver for a second time interval in which the first driver is controlled to enable the first switch, and then charge the second capacitor (such as, for example, capacitor 43) by the input voltage for a third time interval in which the first driver is controlled to enable the first switch.

The method may have an embodiment further comprising configuring the control circuit to initiate the second time interval in response to controlling the first driver to enable the first switch.

One embodiment may include: configuring the control circuit to implement the sequence to store the temporary voltage on the first capacitor includes configuring the control circuit to couple the second capacitor to be charged substantially to the input voltage for a first portion of the first time interval and then to be coupled between the input voltage and the second capacitor to store the temporary voltage on the first capacitor for a second portion of the first time interval.

Another embodiment may include configuring the control circuit to continuously repeat the sequence for the first time interval.

One embodiment of the method may comprise: configuring the control circuit to couple the second capacitor in series between the first voltage and the first capacitor includes referencing the second capacitor to the output voltage.

One embodiment may include: configuring the control circuit to couple the second capacitor in series between the first voltage and the first capacitor includes coupling a first transistor (such as, for example, transistor 47) to receive the first voltage and coupling the first voltage to a first terminal of the second capacitor, wherein a second terminal of the second capacitor is coupled to the first capacitor.

One skilled in the art will also recognize that an example of a method of forming a semiconductor device may include:

configuring a control circuit (such as, for example, circuit 19) to control a first driver (such as, for example, driver 21) to operate a first switch (such as, for example, the switch of transistor 11) and to control a second driver (such as, for example, driver 20) to operate a second switch (such as, for example, the switch of transistor 12) to form an output voltage (such as, for example, the voltage on output 16) from a first voltage (such as, for example, HV);

configuring an input (such as, for example, input 14) of the control circuit to receive an input voltage (such as, for example, Vin);

configuring the control circuit to form a temporary voltage (such as, for example, a voltage on capacitor 33) greater than the input voltage comprises forming the temporary voltage for at least a portion of a first time interval that the second switch is enabled, wherein the temporary voltage is formed by the input voltage; and is

The control circuit is configured to couple the first driver to substantially receive the temporary voltage to supply current and voltage to operate the first driver in response to controlling the first driver to enable the first switch.

The method may have an embodiment that may include configuring the control circuit to form a second voltage that is substantially the input voltage (such as, for example, the voltage on capacitor 43) for at least a first portion of a second time interval during which the first driver is controlled to enable the first switch, and then coupling the second voltage in series between the first voltage and a power input of the first driver to supply voltage and current to the first driver for a second portion of the second time interval.

One embodiment may include: configuring the control circuit to form the temporary voltage includes configuring the control circuit to form a sequence to charge a first capacitor (such as capacitor 43) substantially to the input voltage and then serially coupling the first capacitor between the input voltage and a second capacitor (such as, for example, capacitor 33) to store the temporary voltage on the second capacitor, wherein the control circuit repeats the sequence continuously for a first time interval.

One embodiment may include forming the temporary voltage on a capacitor (such as, for example, capacitor 43) referenced to the output voltage.

The method may have an embodiment that may further include configuring the control circuit to couple a first capacitor (such as, for example, capacitor 43) in series between a first voltage and a power input of the first driver to supply voltage and current to the first driver for a first portion of a second time interval during which the first driver is controlled to activate the first switch, and then to couple the first capacitor to be substantially charged to the input voltage to form the second voltage for at least a second portion of the second time interval.

While the subject matter of the present specification has been described in terms of certain preferred and exemplary embodiments, the foregoing drawings and description of the present specification depict only typical and non-limiting examples of embodiments of the subject matter and are not therefore to be considered to limit its scope, as numerous alternatives and modifications will be apparent to those skilled in the art. As the following claims reflect, inventive aspects may lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims set forth below are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention. Furthermore, although some embodiments described herein include some but not other features included in other embodiments, those skilled in the art will appreciate that combinations of features of different embodiments are intended to be within the scope of the invention and are intended to form different embodiments.