阅读说明：本技术 光源驱动电路和驱动方法 (Light source driving circuit and driving method ) 是由 蔡文彬 于 2019-12-27 设计创作，主要内容包括：本发明提供一种包含多个子驱动电路、多个锁存电路以及多个第一开关电路的光源驱动电路。子驱动电路配置成供应多个驱动电流以驱动第一组光源发光从而在显示媒体上形成为第一像素。子驱动电路的数量对应于第一像素的像素数据的第一数据分辨率。锁存电路中的每一个配置成存储第一像素的像素数据的不同位。第一开关电路分别耦合到子驱动电路且配置成根据像素数据来控制将驱动电流供应到第一组光源的多个子驱动电路。(The invention provides a light source driving circuit comprising a plurality of sub-driving circuits, a plurality of latch circuits and a plurality of first switch circuits. The sub-driving circuit is configured to supply a plurality of driving currents to drive the first group of light sources to emit light to form a first pixel on the display medium. The number of sub-driving circuits corresponds to a first data resolution of the pixel data of the first pixel. Each of the latch circuits is configured to store a different bit of pixel data of the first pixel. The first switching circuits are respectively coupled to the sub-driving circuits and configured to control a plurality of sub-driving circuits supplying driving currents to the first group of light sources according to the pixel data.)

1. A light source driving circuit comprising:

a plurality of sub-driving circuits configured to supply a plurality of driving currents to drive a first group of light sources to emit light to form as first pixels on a display medium, wherein the number of the sub-driving circuits corresponds to a first data resolution of pixel data of the first pixels;

a plurality of latch circuits, wherein each of the latch circuits is configured to store a different bit of the pixel data of the first pixel; and

a plurality of first switching circuits respectively coupled to the plurality of sub-driving circuits and configured to control the supply of the driving current to the plurality of sub-driving circuits of the first group of light sources according to the pixel data.

2. The light source driving circuit of claim 1, wherein each of the latch circuits is configured to store at least two bit values relative to a same bit position of at least two pixels on the display medium.

3. The light source driving circuit according to claim 2, further comprising:

a plurality of multiplexers, wherein each of the multiplexers is coupled to one of the latch circuits and one of the first switch circuits and configured to time-divisionally output the at least two bit values stored in the one of the latch circuits to control the one of the first switch circuits.

4. The light source driving circuit according to claim 1, wherein each of the sub-driving circuits comprises:

a bias current generating circuit configured to generate a reference current whose value is configured according to a bit order of the pixel data; and

a plurality of output current mirrors configured to generate a plurality of output currents to drive a second group of light sources, respectively, wherein one of the output currents is a first drive current of the drive currents of light sources to be driven of the first group of light sources.

5. The light source driving circuit according to claim 4, further comprising:

at least one additional sub-drive circuit configured to supply at least one additional drive current; and

a current summing circuit coupled to the at least one additional sub-drive circuit and at least one light source of the first set of light sources, configured to transmit the at least one additional drive current to the at least one light source,

wherein a total number of the sub-driving circuits and the at least one additional sub-driving circuit corresponds to a second data resolution that is greater than the first data resolution.

6. The light source driving circuit according to claim 5, wherein the current summing circuit comprises:

at least one first switch coupled between the at least one additional sub-drive circuit and the at least one light source of the first set of light sources, configured to transmit the at least one additional drive current to the at least one light source.

7. The light source driving circuit according to claim 6, further comprising:

a controller coupled to the at least one first switch and configured to generate a control signal to control a switching operation of the at least one first switch.

8. The light source driving circuit according to claim 1, further comprising:

a current transfer circuit coupled to a first number of the plurality of latch circuits and to a first number of the plurality of sub-drive circuits and configured to transfer a first number of the drive currents among the drive currents output from corresponding first numbers of sub-drive circuits to the first set of light sources.

9. The light source driving circuit according to claim 8, wherein the current transfer circuit includes a plurality of switches controlled according to some of the bits of the pixel data stored in the corresponding latch circuits.

10. The light source driving circuit according to claim 4, wherein

The bias current generating circuit in each of the sub-drive circuits corresponds to one of the latch circuits,

the bias current generating circuit is configured to generate a first reference current applied in a first display frame, and a corresponding one of the latch circuits is configured to store a bit value of a first bit position of the pixel data in the first display frame; and

the bias current generating circuit is configured to generate a second reference current applied in a second display frame, and the corresponding one of the latch circuits is configured to store a bit value of a second bit position of the pixel data in the second display frame.

11. The light source driving circuit of claim 1, wherein the sub-driving circuit drives the first set of light sources to emit light in a time-multiplexed manner to form a first pixel on a display medium by visual persistence.

12. A driving method applied to a driving circuit including a plurality of sub driving circuits, a plurality of latch circuits, and a plurality of first switch circuits, the driving method comprising:

supplying a plurality of driving currents to drive a first group of light sources to emit light through the plurality of sub-driving circuits to form first pixels on a display medium, wherein the number of the sub-driving circuits corresponds to a first data resolution of pixel data of the first pixels;

storing, by each of the plurality of latch circuits, a different bit of the pixel data of the first pixel in a plurality of latch circuits of the drive circuit; and

controlling the plurality of sub driving circuits through the plurality of first switching circuits to supply the driving current to the first group of light sources according to the pixel data.

13. The driving method of claim 12, wherein storing the different bits of the pixel data of the first pixel in the plurality of latch circuits of the driving circuit comprises:

storing at least two bit values relative to a same bit position of at least two pixels on the display medium.

14. The driving method according to claim 13, further comprising:

outputting, by a plurality of multiplexers of the drive circuit, the at least two bit values stored in the latch circuit to control the first switch circuit.

15. The driving method according to claim 12, further comprising:

generating a reference current according to a bit sequence of the pixel data; and

generating a plurality of output currents to drive a second group of light sources, respectively, wherein one of the output currents is a first drive current of the drive currents of the light sources of the first group of light sources to be driven.

16. The driving method according to claim 12, further comprising:

supplying, by at least one additional sub-drive circuit of the drive circuit, at least one additional drive current; and

transmitting, by a current summing circuit of the drive circuit, the at least one additional drive current to at least one light source, wherein a total number of the sub-drive circuits and the at least one additional sub-drive circuit corresponds to a second data resolution that is greater than the first data resolution.

17. The driving method according to claim 12, further comprising:

transmitting, by a current transmitting circuit of the driving circuit, a first number of driving currents among the driving currents output from corresponding first portions of sub-driving circuits to the first group of light sources,

wherein the current transfer circuit is coupled to a first portion of the plurality of latch circuits and to a first portion of the plurality of sub-drive circuits.

18. The driving method according to claim 17, further comprising:

a plurality of switches of the current transfer circuit are controlled according to some of the bits of the pixel data stored in the corresponding latch circuit.

19. The driving method according to claim 12, further comprising:

scrolling the bit position of the pixel data stored in each of the latch circuits and scrolling the reference current generated by the bias current generating circuit of each of the sub-drive circuits in each display frame, wherein

A first reference current applied in a first display frame is generated by the bias current generating current source circuit and a bit value of a first bit position of the pixel data is stored in the first display frame through a corresponding one of the latch circuits, and a second reference current applied in a second display frame is generated by the bias current generating circuit and a bit value of a second bit position of the pixel data is stored in the second display frame through the corresponding one of the latch circuits.

Technical Field

The present disclosure relates generally to light source driving, and more particularly, to a driving circuit capable of improving display quality at a high refresh rate (refresh rate) and a method thereof.

Background

In led display systems, pulse-width modulation (PWM) is used in many applications to drive multiple light sources to display multiple bits of display data on a display medium. The display system may control a duty cycle (e.g., a percentage of an "ON" period within each cycle) to drive the light source according to a data resolution of the multi-bit display data. For example, a cycle may be divided into 256 cells to display 8 bits of display data, which represents gray levels from 0 to 255. The length of the cycle is inversely proportional to the refresh rate of the display system. In other words, as the refresh rate of the display system increases, the length of the cycle decreases. When the length of the cycle is too short compared with the response time of the light source, the display quality of the multi-bit display data is degraded because the length of each cycle is not long enough to display the full range of gray scales.

As the demand for display applications with fast refresh rates has increased recently, there is a need for innovative techniques to improve display quality at high refresh rates for led display systems.

Disclosure of Invention

A light source driving circuit and a driving method capable of improving display quality at a high refresh rate are provided.

In some embodiments, the light source driving circuit includes a plurality of sub-driving circuits, a plurality of latch circuits, and a plurality of first switching circuits. The plurality of sub-driving circuits are configured to supply a plurality of driving currents to drive the first group of light sources to emit light to form first pixels on the display medium. The number of sub-driving circuits corresponds to a first data resolution of the pixel data of the first pixel. Each of the latch circuits is configured to store a different bit of the pixel data of the first pixel, and a number of the plurality of latch circuits corresponds to a data resolution of the pixel data of the first pixel. The first switching circuits are respectively coupled to the sub-driving circuits and configured to control a plurality of sub-driving circuits supplying driving currents to the first group of light sources according to the pixel data.

In some embodiments, the driving method comprises the steps of: supplying a plurality of driving currents to drive a first group of light sources to emit light through a plurality of sub driving circuits to form first pixels on a display medium, wherein the number of the sub driving circuits corresponds to a first data resolution of pixel data of the first pixels; storing, by a plurality of latch circuits, different bits of pixel data of the first pixel in a plurality of latch circuits of a drive circuit, wherein a number of the plurality of latch circuits corresponds to a data resolution of the pixel data of the first pixel; and controlling the plurality of sub driving circuits through the plurality of first switching circuits to supply driving currents to the first group of light sources according to the pixel data.

In order that the disclosure may be better understood, several embodiments are described in detail below with reference to the accompanying drawings.

Drawings

The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated into and constitute a part of this specification. The drawings illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

FIG. 1 is a schematic diagram of a display system according to some embodiments.

Fig. 2A is a schematic diagram of a driving circuit for driving a plurality of light sources according to some embodiments.

Fig. 2B is a schematic diagram of a driving circuit for driving a plurality of light sources according to some embodiments.

Fig. 2C-2D are timing diagrams illustrating driving operations of a driving circuit, according to some embodiments.

Fig. 3A is a schematic diagram of a drive circuit having a current summing circuit, according to some embodiments.

Fig. 3B is a timing diagram illustrating a driving operation of a driving circuit according to some embodiments.

Fig. 4A is a schematic diagram of a driver circuit having a current delivery circuit according to some embodiments.

Fig. 4B is a timing diagram illustrating a driving operation of a driving circuit according to some embodiments.

Fig. 5A-5B are timing diagrams illustrating a scrolling function of a drive circuit, according to some embodiments.

Fig. 6A is a schematic diagram of a driving circuit capable of compensating for a defective light source according to some embodiments.

Fig. 6B is a timing diagram illustrating a driving operation of a driving circuit for compensating a defective light source according to some embodiments.

Fig. 7A is a schematic diagram of a driving circuit capable of compensating for a defective light source according to some embodiments.

Fig. 7B is a timing diagram illustrating a driving operation of a driving circuit for compensating a defective light source according to some embodiments.

Fig. 8 is a flow diagram illustrating a driving method suitable for use in a driving circuit, in accordance with some embodiments.

Description of the reference numerals

100: a display system;

110. 210, 310, 410, 610, 710: a drive circuit;

120. l ED _11, L ED _1M, L ED _21, L ED _22, L ED _2M, L ED _31, L ED _61, L ED _71, L ED _81, L ED _8M light source;

130: displaying the media;

140: a controller;

210_1, 210_2, 210_ 8: a sub-driving circuit;

210_01, 210_ 02: an additional sub-driving circuit;

CO L _1, CO L _ M columns;

DATA: displaying the data;

i01, I02: a bias source;

i1: a current source;

IR 1: reference current/bias current;

IR 2: a bias current;

IR 8: a reference current;

l11, L1M, L21, L71, L81, L8M latch circuit;

l11 _1, L11 _ N, L81 _1, L81 _ N latch;

m01_2, M02_2, M11_2, M1M _2, M21_2, M61_2, M71_2, M81_2, M8M _ 2: an output current mirror;

MS11, MP11, MP1M, MS1M, MS81, MP81, MP8M, MS 8M: a switching circuit;

m1, M2: a transistor;

MUX _11, MUX _81, MUX _ 8M: a multiplexer;

OPAM: an operational amplifier;

p1, P2, P20: a pixel;

ROW _1, ROW _2, ROW _3, ROW _4, ROW _7, ROW _ 8: a row;

s810, S820 and S830: a step of;

and (3) Scrl: a control signal;

sop: an optical signal;

SW01, SW02, SW11, SW71, SW73, SW7M, SW81, SW8M, TS11, TS81, TS 8M: a switch;

t1, T3, T5, T8, T15, T20: and (6) circulating.

Detailed Description

It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present disclosure. Also, it is to be understood that the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting.

FIG. 1 illustrates a display system 100 according to some embodiments. The display system 100 may include a driving circuit 110, a plurality of light sources 120, a display medium 130, and a controller 140. Drive circuit 110 is coupled to light source 120 and is configured to drive light source 120 to emit light or optical signals Sop to display medium 130 in order to form pixels of a display frame on display medium 130. The driving circuit 110 may drive the light source 120 according to the display DATA. In some embodiments, the driving circuit 110 may include at least one bias current generating circuit (not shown) configured to generate reference currents having different current levels. The driving circuit 110 may drive the light source 120 according to the reference current and the display DATA (or pixel DATA) DATA to form a display frame on the display medium 130. In some embodiments, the display medium 130 may be a projection screen and the light from the light source 120 is projected onto the projection screen to form the surface of the pixels of the display frame. In another embodiment, the display medium 130 may be the retina of a human eye and the light from the light source 120 is projected onto the retina. The light may be projected onto the display medium 130 using optical components such as prisms, lenses, or mirrors. In another embodiment, the display medium 130 may be a display panel configured with the light source 120. The controller 140 is coupled to the driving circuit 110 and configured to control the operation of the driving circuit 110 according to the control signal Scrl. In some embodiments, the controller 140 includes logic circuitry configured to generate the control signal Scrl to control the driving circuit 110. In some embodiments, the light sources 120 may be configured as a light emitting array of the same color, such as red, blue, green, or white, or other colors, such as cyan (cyan), magenta (magenta), yellow (yellow), for example, without limitation. In some embodiments, the display system 100 may include multiple arrays of light sources 120 to emit different colors of light, such as red, blue, green, and the different colors of light may be projected to form full-color (full-color) pixels on the display medium 130. In some embodiments, the display system 100 may include multiple arrays of light sources 120 emitting white light, and through the color filter assembly, the white light may be projected to form full color pixels on the display medium 130.

Fig. 2A illustrates a schematic diagram of a driving circuit 210 for driving a plurality of light sources L ED _11 to L ED _8M, where M is a positive integer, light sources L ED _11 to L ED _8M may be arranged in an array of N × M (array), N8, including ROWs ROW _1 to ROW _8 and columns CO L _1 to CO L _ M, the light sources in the same columns are referred to as a first group of light sources, and the light sources in the same ROWs are referred to as a second group of light sources, for example, the first group of light sources may be light source columns CO L _1 including light sources L ED _11 to L ED _81, and the second group of light sources may be light source ROWs w _1 including light sources L ED _11 to L ED _1M, light sources L ED _11 to L ED _8M may be light emitting elements (light emitting elements), light sources 398936 ED _11 to light sources 4637 ED _8M, light sources may be light emitting micro light sources L, or any other suitable micro light sources capable of emitting light, e L.

The driving circuit 210 may include a plurality of sub-driving circuits 210_1 to 210_8, a plurality of latch circuits L to L M, a plurality of multiplexers MUX _11 to 8M, and a plurality of switch circuits MS11 to switch circuits MS 8m. from the aspect of the light source ROW, the sub-driving circuits 210_1 to 210_8 are configured to provide driving currents to M light sources of a corresponding light source ROW (i.e., the second set of light sources) in the ROW _1 to ROW _8, from the aspect of the light source column, the sub-driving circuits 210_1 to 210_8 are configured to provide driving currents to 8 light sources of a corresponding light source column (i.e., the first set of light sources) in the columns CO L _1 to CO L _8, in order to drive the light source column CO L _1 to form a first pixel of the display medium 130, associated portions of the driving circuit 210 are sub-driving circuits 210 to 210, a sub-driving circuit 210, a set of light sources CO L to emit light to form a first pixel of the display medium 130, if the display medium is displayed in a display frame with a display data format such as a display data by a visual display medium such as a sub-drive circuit including a sub-drive circuit 210, a display medium such as a display data, a display medium such as a display medium, a display medium such as a display medium with a display data, a display frame, a display medium such as a sub-8, a display medium such as a display medium with a display medium, a display medium with a display data, a sub-8, a display data, a sub-8.

Fig. 2B is a schematic diagram of a driving circuit for driving a plurality of light sources according to some embodiments. Based on the example of fig. 2B, multiplexer MUX _11 through multiplexer MUX _81 are not required.

In some embodiments, each of the sub-driver circuits 210_1 through 210_8 includes a bias current generating circuit and a current mirror circuit, for example, the sub-driver circuit 210_1 includes a bias current generating circuit formed by a current source generating a reference current I1 (hereinafter also referred to as a current source I1) and a current mirror circuit CM1 including an input current transistor M1 and output current transistors MP11 through MP 1M. the transistors are illustrated as PMOS, but not limited thereto. the current mirror circuit CM1 generates a plurality of output currents as driving currents for the light sources L ED _11 through L ED _1M, respectively, wherein each output current has the same current value as the reference current I1. each of the sub-driver circuits 210_2 through 210_8 includes a circuit structure (i.e., a bias current generating circuit and a current mirror circuit) similar to the sub-driver circuit 210_1, which is repeatedly described herein. the output currents generated by the current mirror circuit CM1 are provided to the light source ROW W8 at the same time in embodiments, the light source AM transistors are configured to include a plurality of symmetrical current generating transistors AM transistors M2, which are provided to the current mirror circuits included in the present embodiment, and AM transistors included in order to provide a greater amount of the light source AM transistors M2, which are included in the present embodiment, which are configured to provide a more of the symmetrical current amplifier circuit, which is included in order to provide the light source AM transistors included in the light source circuits including the same as the light source circuits including the input current amplifier circuit AM transistors.

Regarding the pixels of the display frame, for example, the first pixel corresponding to the light source row CO L _1, the sub-driving circuits 210_1 to 210_8 generate eight different driving currents for the light sources L ED _11 to L ED _81 of the light source row CO L _1, respectively, and the eight different driving currents are time-divisionally supplied to the light sources L ED _11 to L ED _81 under the control of the plurality of switching circuits MS11 to MS81, the values of the reference currents I1 to I8 generated by the bias current generating circuits of the sub-driving circuits 210_1 to 210_8 are configured according to different bit orders of the pixel data stored in the circuit latches, the reference current I1 is corresponding to bit 0 of the display data and is configured as 20I, the reference current I2 is corresponding to bit 1 and is configured as 2 of the display data, and the 8-bit display data is configured as an example¹I; taking 8-bit display data as an example, the reference current I3 is corresponding to bit 2 of the display data and is configured as 2²I, etc., and so on, where I is a predetermined current. Therefore, the reference currents I1 to I8 are 1 × I, 2 × I, 4 × I, 8 × I, 16 × I, 32 × I, 64 × I, and 128 × I, respectively.

In some embodiments, the values of the reference currents I1 to I8 may be periodically changed (e.g., according to a display frame) such as current values rolling, which can prevent the light sources of each row from being always driven by the same current value, thereby eliminating the effect of current component mismatch caused by the manufacturing process. For example, the scrolling function is shown in table 1, and the reference currents I1 to I8 are 1 × I, 2 × I, 4 × I, 8 × I, 16 × I, 32 × I, 64 × I, and 128 × I, respectively, with respect to driving the light source to display the display frame 1 (e.g., emitting light for projection onto the projection screen); regarding the display frame 2 in which the driving light source is displayed to be continuous to the display frame 1, the reference currents I1 to I8 are 128 × I, 1 × I, 2 × I, 4 × I, 8 × I, 16 × I, 32 × I, and 64 × I, respectively; regarding the display frame 3 in which the driving light source is displayed to be continuous to the display frame 2, the reference currents I1 to I8 are 64 × I, 128 × I, 1 × I, 2 × I, 4 × I, 8 × I, 16 × I, and 32 × I, respectively. When the scrolling function is applied to the setting of the reference current, the bit sequence of the bits of the pixel data stored in the latch circuit can be changed corresponding to the display frame, which is described in detail later.

TABLE 1

	Display frame 1	Display frame 2	Display frame 3
				I1	1*I	128*I	128*I
I2	2*I	1*I	128*I
				I3	4*I	2*I	1*I
I4	8*I	4*I	2*I
				I5	16*I	8*I	4*I
I6	32*I	16*I	8*I
				I7	64*I	32*I	16*I
I8	128*I	64*I	32*I

A display frame including a row of pixels P11 to P1 4, which are 8 bits of pixel data, as an illustration to be described below based on this example, pixel P11 is displayed by eight light sources L ED _11 to L ED _81 that are time-divisionally illuminated, and latch circuits L to L are arranged to store different bits of pixel data of pixel P11 similarly, pixel P1M is displayed by eight light sources L ED _1M to L ED _8M that are time-divisionally illuminated, and latch circuits L M to L M are arranged to store different bits of pixel data of pixel P1M.

For example, latch circuit L11 may store bit 0 of pixel P11, designated B [0] (e.g., the least significant bit), latch circuit L21 may store bit 1 of pixel P11, designated B [1], and latch circuit L81 may store bit 7 of pixel P11, designated B [8] (e.g., the most significant bit). in some embodiments, the number of latch circuits to store pixel data for a pixel corresponds to the data resolution of the pixel data.

For example, the switch circuits MS11 to MS81 are coupled to the sub-driver circuits 210_1 to 210_8, respectively, and are configured to control the sub-driver circuits 210_1 to 210_8 according to bits of pixel data of the pixel P11 (stored in the latch circuits L to L, respectively) to time-divisionally supply different driving currents to the light sources L ED _11 to L ED _81 (i.e., the first set of light sources) of the light source column CO L _1, similarly, the switch circuits MS1M to MS8 638 are coupled to the sub-driver circuits 210_1 to 210_8, respectively, and are configured to control the sub-driver circuits 210_1 to 210_8 according to bits of pixel data of the pixel P1M (stored in the latch circuits L M to L M, respectively) to time-divisionally supply different driving currents to the sub-driver circuits 210_8, to latch the light sources of the light source column CO 29, i.e., the switch circuits MS 468 to generate the set of light sources 468 signals (stored in the latch circuits MS 4642 to MS 468) based on the bits of the switch circuits MS 4624, 468, and the switch circuits MS 468, and the switch circuits 468, respectively.

In some embodiments, each of latch circuits L through L M is configured to store at least two bits relative to a same bit position of at least two pixels on the display medium. each of multiplexer MUX _11 through multiplexer MUX _8M is coupled between one of latch circuits L through L M and one of switch circuits MS11 through MS8M and is configured to time-divisionally output at least two control signals based on at least two bits relative to a same bit position of at least two pixels stored in latch circuits L through 468M to control switch circuits MS11 through MS 8M. for example, multiplexer MUX _11 is coupled between latch circuit L11 and switch circuit MS11 and is configured to output a first control signal corresponding to a first bit stored in latch circuit L11 to control switch circuit MS 463 during a first time division and to output a second control signal corresponding to second bit stored in latch circuit MS L during a second time division to control switch circuit MS 73784.

FIG. 2C is a block diagram for a pixel array based on 8-bit pixel data B [0]]To display data B [7]]To drive a light source to form a pixel P on a display medium_1,1To P_N,MIn the exemplary timing diagram of the present disclosure, Pn is indicated as a row of pixels, including pixel P, where N, M is an integer and N-20_n,1To P_n,M. T1-T20 are denoted unit periods. In this example, the ratio of the light source to the pixel pitch on the display medium is 1:1, meaning that light emitted by the light source can be projected to the target pixel location. The light source lines ROW _1 to ROW _8 emit light according to different bits of 8-bit display data, respectively. Thus, in each unit period, each light source row is driven according to the bit of the 8-bit display data, and eight unit periods (considered as cycles) are required to display the 8-bit display data of the pixels on the display medium. Referring to fig. 2A and 2C, in the unit period T1, the driving circuit is configured to be in accordance with the pixel P_1,1To P_1,MA plurality of bits B [0] of pixel data (which may be briefly labeled as pixel row P1)]To control the light sources L ED _11 through L ED _1M in the ROW ROW _1 to emit light in a unit period T2, the driving circuit is configured to emit light according to the pixels P_1,1To P_1,MA plurality of bits B [1] of pixel data of]To control the light sources L ED _21 through L ED _2M (not shown) in the ROW ROW _2 to emit light similarly, in the subsequent unit periods T3 through T8, the driving circuit is configured to drive the display device according to the pixels P of the display medium_1,1To P_1,MBit B [2] of pixel data of]To B < 7 >]To control the light sources in the light source ROWs ROW _3 to ROW _8 to emit light in time division. Other pixel rows P2 through P20 may be formed in the display medium in a similar manner, and thus detailed description is omitted below. On the display medium can be calculated according to equation (1)Luminance L of pixel row P1_P1Where I is the predetermined current.

L_P1＝1*I*P1_B[0]+2*I*P1_B[1]+4*I*P1_B[2]+8*I*P1_B[3]+

16*I*P1_B[4]+32*I*P1_B[5]+64*I*P1_B[6]+128*I*P1_B[7](1)

FIG. 2D illustrates a timing diagram for driving light sources to form pixels (e.g., pixel row P1 through pixel row P20) in accordance with 8-bit display data B [0] through display data B [7], where the ratio of light sources to pixel spacing on the display medium is 2: 1. The difference between the timing diagram shown in FIG. 2B and the diagram shown in FIG. 2C is that the bit values of pixel data P1 (e.g., P1_ B [0] through P1_ B [8]) are not displayed in consecutive cycles. In practice, position P1_ B [1] is shown in cycle T3, position P1_ B [2] is shown in cycle T5, and position P1_ B [7] is shown in cycle T15. As such, after 15 cycles, the drive circuit may drive the light source to display 8-bit display data (e.g., B [0] to B [7]) on pixel P1 of the display medium. The luminance of the pixel P1 may be determined according to equation (1).

Fig. 3A illustrates a schematic diagram of a driving circuit 310 for driving a plurality of light sources L ED _11 to L ED _8M according to some embodiments, in which the light sources L ED _11 to L ED _8M are arranged as a light source array (array) of N × M, N-8, the same components of the driving circuits in fig. 3A and 2A are indicated by the same reference numerals, the difference between fig. 3A and 2A is that the driving circuit 310 in fig. 3A further includes an additional sub-driving circuit 210_01 and an additional sub-driving circuit 210_02 and a current summation (current summation) circuit, which in this case may be implemented by switching SW0_11, SW0_21, SW 38 _12, SW0_22 to SW0_1M and SW 0M, each of the additional sub-driving circuit 210_01 and the additional sub-driving circuit 210_02 may be implemented by a pre-current generation circuit 210 and an additional sub-driving circuit 210 current generation circuit 210, which may be implemented by switching an additional sub-current generation circuit 210, such as a pre-current generation circuit 210, a pre-driving circuit 210, a pre-current generation circuit 210 and an additional sub-current generation circuit 210, which may be represented by a pre-current generation circuit 2I-2 c, which may be represented by a pre-data-c circuit 2c, and an additional sub-c circuit 2c, which may be respectively, which may be represented by a resolution data-c, and may be represented by a resolution data-c, which may be respectively, and an additional sub-c circuit 2c, which may be represented by a resolution-c, and an additional sub-c circuit 2c, which is shown as additional sub-c circuit 210, which may be respectively, and an additional sub-c circuit 2c, which may be respectively, which is shown in which may be included in which is shown as a resolution-c 2c, and may be included in a resolution data-c 2c, and may be included in a resolution data-c 2c, which is included in a resolution-c, which is shown as a resolution circuit 210, which is included in a resolution circuit 210, which is shown as an additional sub-c, which is a resolution circuit 210 c, and.

The current summing circuit is used to deliver the driving current provided by the sub-driving circuit 210_01 and other driving currents provided by the sub-driving circuit 210_01 to any one of the light source ROWs ROW _1 to ROW _8, for example, to the light source ROW _1 according to the control of the switches in the current summing circuit in this example. In the current summing circuit, the switches SW0_11 to SW0_1M may be coupled between a plurality of output current mirror transistors (e.g., M01_2) of the additional sub-driving circuit 210_01 and a plurality of output current mirror transistors (e.g., M02_2) of the additional sub-driving circuit 210_02, respectively. The switches SW0_21 to SW0_2M may be coupled between a plurality of output current mirror transistors (e.g., M02_2) of the additional sub-driving circuit 210_02 and a plurality of output current mirror transistors MP11 to MP1M of the additional sub-driving circuit 210_01, respectively (refer to fig. 2A).

For example, when the switch SW0_11 and the switch SW0_21 are turned on to form an electrical connection among the output current mirror transistors M01_2, M02_2, MP1, the driving current supplied to the light source L ED _11 may be summed to equal 1/4I + 1/2I + 1I, where I is a predetermined current.

FIG. 3B is a block diagram for a 10-bit pixel data B [0] according to some embodiments]To display data B [9 ]]To drive a light source to form a pixel P on a display medium_1,1To P_N,MTiming diagram of pixels (e.g., pixel P1-pixel P20) of the pixel array of N × M, where N, M is an integer and N is 20 for illustrative purposes referring to fig. 3A and 3B, when switches SW0_11 to SW0_1M and SW0_21 to SW0_2M of the current summing circuit are turned on, bit data B [0] of pixels corresponding to pixel row R1 is added]And bit data B [1]]To bit data B [2] of the pixel corresponding to pixel row R1 (generated by the additional sub-drive circuit)]Thus summarizing the drive circuit driving the light sources L ED _11 through L ED _1M the light sources in the light source ROW ROW _2 through ROW _8 are used to display bits B [3] of pixel data for the pixels of the pixel ROW R1]In place B [9]To form pixels in the display medium. In this manner, the driving circuit 310 can control the light source according to the 10-bit display data to form the pixel in the display medium. In the example shown in FIG. 3B, the ratio of the light source to the pixel spacing on the display medium is 2:1, so the cycle of displaying a row of pixels completely on the display medium is equal to 15 cell periods (e.g., from T1 to T15). Pixel P of pixel line P1 on display medium_i,jMay be positively correlated with the result of summing the drive currents, the luminance of which may be calculated according to equation (2):

I_P1,j＝{I01*P_1,j_B[0]+I02*P_1,j_B[1]+I1*P_1,j_B[2]}+I2*P_1,j_B[3]+I3*P_1,j_B[4]+I4*P_1,j_B[5]+I5*P_1,j_B[6]+I6*P_1,j_B[7]+I7*P_1,j_B[8]+I8*P_1,j_B[9]＝{1/4*I*P_1,j_B[0]+1/2*I*P_1,j_B[1]+1*I*P_1,j_B[2]}+2*I*P_1,j_B[3]+4*I*P_1,j_B[4]+8*I*P_1,j_B[5]+16*I*P_1,j_B[6]+32*I*P_1,j_B[7]+64*I*P_1,j_B[8]+128*I*P_1,j_B[9](2)

fig. 4A illustrates a schematic diagram of a driving circuit 410 for driving light source 4 ROWs according to some embodiments, which includes a first light source ROW _1 including light sources L ED _11 to L ED _1M, a second light source ROW _2 including light sources L ED _21 to L ED _2M (not shown), a third light source ROW _3 including light sources L ED _31 to L ED _3M (not shown), a fourth light source ROW _4 including light sources L ED _41 to L ED _4M, which are also arranged in columns CO L _1 to CO L _ M.

The difference between the driving circuit 410 shown in fig. 4A and the driving circuit 210 shown in fig. 2A is that two sub-driving circuits drive each light source ROW (second group of light sources) in fig. 4A, and one sub-driving circuit drives each of the second group of light sources in fig. 2A, for example, in fig. 4A, the second group of light sources L ED _22 to L ED _2M in the ROW _1 correspond to a pair of sub-driving circuits 210_1 and 210_2, and in case that the number of light source ROWs for displaying pixel data is reduced to four light source ROWs, the driving circuit 410 is used to maintain 8-bit data resolution.

Another difference between the driver circuit 410 depicted in FIG. 4A and the driver circuit 210 depicted in FIG. 2A is that the driver circuit 410 further includes a current transfer circuit formed by switches TS11 through TS 4M. Each of switches TS11 through TS4M is coupled between the outputs of the two output current mirror transistors of the sub-driver circuit pair, more specifically, switches TS11 through TS4M are coupled between the outputs of the output current mirror transistors MP11 through MP1M of the sub-driver circuit 210_1 and between the outputs of the output current mirror transistors MP21 through MP2M of the sub-driver circuit 210_2, respectively. M9 through TS4 are similarly coupled between the outputs of the output current mirror transistors MP71 through MP7M of the sub-driver circuit 210_1 and between the outputs of the output current mirror transistors MP81 through MP8 of the sub-driver circuit 210_2, respectively, and the output current mirror transistors MP81 through MP8 of the sub-driver circuit MP2, respectively, the pixel pitch ratio between the light source and the display medium is other than 1: the pixel pitch ratio, the pixel pitch is latched by the multiplexer TS 3511, the multiplexer is controlled to receive the data stored in the time division multiplexer circuit receiving the MUX 11.

For example, based on bit B [0] of pixel data of a pixel row (stored in a latch circuit), switches TS 11-TS 1M may be controlled to transfer drive currents from the outputs of output current mirror transistors MP 11-MP 1M of sub-drive circuit 210_1 to the outputs of output current mirror transistors MP 21-MP 2M of sub-drive circuit 210_2, respectively, or not. In this manner, the driving circuit 410 having eight sub-driving circuits can be used to drive the four light source rows of the group using 8-bit display data when the switches TS11 to TS4M of the current transfer circuit are controlled to be turned on or off according to the storage bits in the latch circuit. In the example of switches TS11 through TS4M set to turn off the current transfer circuit, a driver circuit 410 having eight sub-driver circuits may be used to drive the group of eight light source rows using 8-bit display data (e.g., fig. 2A). In this way, the flexibility of the driving circuit 410 is improved.

FIG. 4B is a block diagram for a pixel based on 8-bit pixel data B [0] according to some embodiments]To display data B [7]]To drive the light source to form a timing diagram of the pixels on the display medium. Referring to FIGS. 4A and 4B, in the unit period T1, the switches TS11 through TS1M of the current transmitting circuit can respectively transmit the bit B [0] of the pixel data corresponding to the pixel column P1]Is transmitted to the output terminals of the output current mirror transistors M21 through M2M, thus corresponding to the bit B [0] of the pixel data of the pixel column P1]And bit B [1] of pixel data corresponding to pixel column P1]May be separately summed. Thus, in the unit period T1, according to the respective summed bits B [0] of the pixel data corresponding to the pixel column P1]And B1]Similarly, in the unit period T2, according to the respectively summed bits B [0] 0 of the pixel data corresponding to the pixel ROW P2]And B1]Driving the light source ROW _ 1; in unit period T3, bits B [0] according to the respective summed pixel data corresponding to pixel column P3]And B1]Driving the light source ROW _ 1; in unit period T4, bits B [0] according to the respective summed pixel data corresponding to pixel column P4]And B1]The light source ROW _1 is driven by the driving current of (1). In the unit periods T1 to T4, the light source ROWs other than the light source ROW _1 are not driven (OFF). In unit period T5, bits B [2] of pixel data corresponding to pixel column P1 are summed according to respective sums]And B3]Driving the light source ROW _ 2; in the unit period T9, the pixels corresponding to the pixel row P1 according to the respective summationsBit B [4] of data]And B [5]]Driving the light source ROW _ 3; in unit period T13, bits B [6] of pixel data corresponding to pixel column P1 are summed according to respective sums]And B [7]]The light source ROW _4 is driven by the driving current of (1). After 13 cycles, drive circuit 410 may drive the light sources to display 8-bit display data (e.g., B [0] on pixel row P1 of the display medium]To B < 7 >]). Pixel P of pixel line P1 on display medium_i,jMay be positively correlated with the result of summing the drive currents, the luminance of which may be calculated according to equation (3):

I_P1,j＝{I1*P_1,j_B[0]+I2*P_1,j_B[1]}+{I3*P_1,j_B[2]+I4*P_1,j_B[3]}+

{I5*P_1,j_B[4]+I6*P_1,j_B[5]}+{I7*P_1,j_B[6]+I8*P_1,j_B[7]}＝1*I*P_1,j_B[0]+2*I*P_1,j_B[1]+4*I*P_1,j_B[2]+8*I*P_1,j_B[3]+16*I*P_1,j_B[4]+32*I*P_1,j_B[5]+64*I*P_1,j_B[6]+128*I*P_1,j_B[7](3)

fig. 5A is a timing diagram illustrating a scrolling function of a drive circuit (e.g., drive circuit 210 in fig. 2A, drive circuit 310 in fig. 3A) according to some embodiments. The display quality of the light source is not uniform within the light source of the display system due to variations occurring during the manufacturing process of the light source and the electrical connections among the light source. For example, different light sources may produce different illumination values even if driven by the same drive current. The driving circuit may drive the light source using a scrolling function to improve the display quality of the display system.

Referring to FIGS. 2A and 5A, latch circuits L11-L81 may store bits B [0] to B [7] of pixel data for a pixel, respectively, for driving light source L0 ED _ 11-L1 ED _81, light source L ED _ 11-L ED _81 is driven according to bits stored in latch circuits L11-L81, light source L ED _11 is driven according to bits stored in latch circuits L11, and light source L ED _81 is driven according to bits stored in latch circuits L81.

Referring to fig. 2A and 5A, latch circuits L-L M of sub-driver circuit 210_1 driving light source ROW 1 may store a plurality of bits B [0] of pixel data in display frame 1. reference current I1 may be configured according to the bit order of bits B [0], e.g., 1I.

In display frame 2, latch circuits L11 through L1M of sub-driver circuit 210_1 corresponding to ROW ROW _1 may store a plurality of bits B [7] of pixel data in display frame 1, and reference current I1 may be configured according to the bit order of bits B [7], e.g., 128I, so light source ROW ROW _1 may be driven to display bits B [7] of pixel data in frame 2. similarly, sub-driver circuits 210_2 through 210_8 may drive light sources of ROWs ROW _2 through ROW _8 according to different bit values in different display frames.

FIG. 5B is a timing diagram illustrating a scrolling function of a drive circuit (e.g., drive circuit 410 in FIG. 4A.) referring to FIGS. 4A and 5B, latch circuits L11-L81 may store bits B [0] through B [7] of pixel data of a pixel, respectively, for driving light source L0 ED _ 11-L1 ED _ 41. each of light source L ED _ 11-L ED _41 is driven according to bit values stored in the latch circuits of the two sub-drive circuits, for example, light source L ED _11 is driven according to bit values stored in latch circuit L11 and latch circuit L21, and light source L ED _41 is driven according to bit values stored in latch circuit L71 and latch circuit L81, according to some embodiments.

In some embodiments, the drive circuit 410 may scroll bit values stored in latch circuits and change current values of the current sources I1 through I8 to enable a scrolling function referring to FIGS. 4A and 5B, latch circuits L11 through L1M may store bit values B [0] of pixel data in frame 1 and latch circuits L21 through L2M may store bit values B [1] of pixel data in frame 1 to drive a light source ROW ROW _1 the reference currents I1 and I2 may be configured according to a bit order of the bit values B [0] and B [1], respectively, so the drive circuit 410 may drive the light sources L ED _11 through L ED _1M according to the bit values B [0] and B [1] of pixel data in display frame 1.

In display frame 2, latch circuits L11 through L1M may store bit values B [6] of pixel data in frame 2 and latch circuits L21 through L2M may store bit values B [7] of pixel data in frame 2 to drive light source ROW ROW _ 1. reference currents I1 and I2 may be configured according to the bit order of bit values B [6] and B [7], respectively. As such, drive circuit 410 may drive light sources L ED _11 through L ED _1M of light source ROW ROW _1 according to bit values B [6] and B [7] of pixel data in display frame 2. similarly, drive circuit 410 may drive each of light source ROW ROW _2 through light source ROW ROW _4 according to different bit values of pixel data in each display frame.

Fig. 6A is a schematic diagram of a driving circuit 610 capable of compensating for light emission of a defective light source according to some embodiments. The difference between the driving circuit 610 shown in fig. 6A and the driving circuit 210 shown in fig. 2A is that the driving circuit 610 further includes a current summing circuit including a plurality of switches SW11 through SW 7M. Each of the switches SW11 through SW71 of the current summing circuit is coupled between an output terminal of an output current mirror transistor of one sub-driving circuit driving the light source ROW _ i and an output terminal of an output current mirror transistor of the other sub-driving circuit driving the light source ROW _ (i + 1). For example, switch SW11 is coupled between output current mirror transistor MP11 and output current mirror transistor MP 21; and switch SW71 is coupled between output current mirror transistor MP71 and output current mirror transistor MP 81. The switches SW 11-SW 7M of the current summing circuit may be controlled by a controller (e.g., controller 140 in fig. 1).

When a defective light source, such as light source L ED _71, is present, drive circuit 610 may deactivate defective light source L ED _71 (i.e., not output drive current to the defective light source). In addition, switch SW71 of the current summing circuit is turned on to electrically couple the output of output current mirror transistor MP71 to the output of output current mirror transistor MP81, so the drive current of defective light source L ED _71 may be added to the drive current of light source L ED _81, when switches SW11 through SW6 are in the OFF state. thus, light source L ED _81 may replace the function of defective light source L ED _71, meaning that light source L ED 81 not only emits light corresponding to bit B [7] of the pixel data, but also emits light corresponding to bit B [6] of the pixel data.

FIG. 6B is a timing diagram illustrating the driving of the driving circuit 610 when the light sources (e.g., L ED _31 and L ED _71) are defective light sources, in the example of FIG. 6B, the ratio of the light sources to the pixel pitch on the display medium is 2: 1. referring to FIGS. 6A and 6B, when the light source L ED _31 in the light source ROW ROW _3 is a defective light source, the driving circuit 610 deactivates the light source L ED _31, and the control switch 31 is turned on to add the driving current to the light source L ED _31 to the driving current to the light source 7 _41 in the light source ROW ROW _ 4. in this way, the light source L _41 is driven by the total driving current in unit period T7, the total driving current is the sum of the driving current corresponding to bit B [2] of the pixel data and the driving current corresponding to bit B [3] of the pixel data, similarly, when the light source L _7 in the light source ROW ROW _7 is a unit period T _7, the light source SW _7 is activated by the total driving current to sum of the driving current to the light source 467, the light source SW _7 is added to the light source SW _7, the total driving current is added to the driving current to the driving circuit 58 in a unit SW7 _7, the pixel data, the light source is added to the light source SW7 _7, the total driving current is added to the pixel data, the total driving current is added to the pixel data, the total driving current added to the pixel data, the driving current for the pixel data, the total driving circuit 58 is added to the pixel data 7, the pixel data 7 is added to the.

Fig. 7A illustrates a driving circuit 710 capable of compensating for light emission of a defective light source according to some embodiments the driving circuit 710 includes a current transfer circuit including switches TS11 through TS4M and operable to drive four light source ROWs including light sources L ED _11 through L ED _4M, similar to the driving circuit 410 of fig. 4A the difference between the driving circuit 710 in fig. 7A and the driving circuit 410 in fig. 4A is that the driving circuit 710 further includes a current summing circuit including a plurality of switches SW11 through SW3M as light source compensation functions and having a similar circuit structure as the current summing circuit of the driving circuit 610 of fig. 6A each of the switches SW11 through SW3M of the current summing circuit is coupled between an output terminal of an output current mirror transistor of one sub-driving circuit driving the light source ROW rowi and an output terminal of another sub-driving circuit of the light source ROW (i +1) the output current mirror circuit of the switch SW11 is controllable by a switch SW7M, e.g. a controller M.

When a defective light source, such as the light source L ED _31 of the light source ROW ROW _3, is present, the driving circuit 610 may deactivate the defective light source L ED _31 and control the switch SW31 to be turned on to electrically couple the output terminal of the output current mirror transistor MP61 to the output terminal of the output current mirror transistor MP81, accordingly, the driving current of the light source L ED _41 in the next light source ROW (e.g., ROW _4) may be adjusted to compensate for the emission of the defective light source.

FIG. 7B is a timing diagram illustrating the driving of the driving circuit 710 when the light source L ED _61 is a defective light source referring to FIGS. 7A and 7B, when the light source L ED _31 in the light source ROW ROW _3 is defective, the driving circuit 710 deactivates the light source L ED _31 and controls the switch 31 to be turned on to add the driving current to the light source L ED _31 to the driving current to the light source L ED _41 in the light source ROW ROW _ 4. in this way, the light source L ED _41 is driven by the total driving current in the unit period T13, the total driving current being the total of the driving currents of the bits B [4], B [5], B [6], B [7] of the corresponding pixel data, the driving circuit 710 can adjust the display data replaced by the light source in the next ROW to compensate for the light emission of the defective light source by controlling the switch SW11 to the switch SW3M of the current summing circuit.

Fig. 8 illustrates a flow diagram of a driving method suitable for use in a driving circuit, in accordance with some embodiments. In step S810, a plurality of driving currents are supplied through a plurality of sub driving circuits to drive the first group of light sources to emit light to form first pixels on the display medium, wherein the number of sub driving circuits corresponds to a first data resolution of pixel data of the first pixels. In step S820, different bits of the pixel data of the first pixel are stored in the plurality of latch circuits of the driving circuit by the plurality of latch circuits. In step S830, the plurality of sub driving circuits are controlled by the plurality of first switching circuits to supply driving currents to the first group of light sources according to the pixel data.

According to an embodiment of the present disclosure, a plurality of sub-driving circuits of a driving circuit are used to drive a set of light sources according to pixel data having a particular resolution to form pixels on a display medium. According to an embodiment of the present disclosure, the sub-driving circuit drives the light sources not based on the duty ratio of the pulse width modulation but in a time-divisional manner, and in each unit period of a cycle of a complete display pixel, the driving currents given to different bits of the pixel data are supplied to the corresponding light sources for the same length of time (within the unit period) regardless of the gray-scale value of the data, thus preventing the degradation of display quality at a high operating frequency. Furthermore, the additional sub-drive circuits and current summing circuits may be configured to allow the drive circuits to drive the light sources according to a higher resolution (e.g., 10-bit pixel data). The switch included in the current summing circuit may also allow the drive circuit to drive the light source according to different resolutions, thereby improving the flexibility of the drive circuit. The drive circuit may have a scrolling function to reduce negative effects caused by imperfect manufacturing of the light source. Further, a repair mechanism may also be implemented in the drive circuit using a current summing circuit to turn off the defective light source and compensate for the light emission of the defective light source using the light source in the next row.

It will be apparent to those skilled in the art that various modifications and variations can be made in the structure of the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of this disclosure provided they come within the scope of the appended claims and their equivalents.