阅读说明：本技术 用于生成pwm信号的方法和用于生成pwm信号的电路 (Method for generating PWM signal and circuit for generating PWM signal ) 是由 克里斯多夫·索爱尔 马库斯·克斯勒尔 延斯·里希特 于 2020-04-27 设计创作，主要内容包括：一种生成PWM信号(501)的电路(1),其包括：-移位寄存器(10),其具有多个时钟控制的寄存器单元(10i),该多个时钟控制的寄存器单元分别具有输入端(11i)和输出端(12i),-写入单元(20),其设计用于将寄存器单元(10i)的输出端分别设置为预定的逻辑值,以及-时钟发生器(30),其设计用于以共同的时钟信号(500)操作寄存器单元(10i),-其中寄存器单元(10i)串联连接,移位寄存器(10)设计用于在输出触点(12)处输出PWM信号(501),其中PWM信号(501)是在寄存器单元(10i)中设置的逻辑值的时间序列,并且PWM信号(501)随时钟信号(500)的一个时钟(5)的持续时间采用逻辑值中的每一个,其中时钟信号(500)是周期的,连续时钟(5)的持续时间在一个周期(50)期间变化,并且每个周期(50)的时钟信号是相同的。(A circuit (1) for generating a PWM signal (501), comprising: -a shift register (10) having a plurality of clocked register cells (10i) each having an input (11i) and an output (12i), -a write unit (20) which is designed to set the outputs of the register cells (10i) to predetermined logic values, respectively, and-a clock generator (30) which is designed to operate the register cells (10i) with a common clock signal (500), -wherein the register cells (10i) are connected in series, the shift register (10) being designed to output PWM signals (501) at output contacts (12), wherein the PWM signals (501) are a time sequence of the logic values set in the register cells (10i) and the PWM signals (501) adopt each of the logic values over the duration of one clock (5) of the clock signal (500), wherein the clock signal (500) is periodic, the duration of successive clocks (5) varies during one period (50), and the clock signal of each period (50) is the same.)