阅读说明：本技术 一种Posit浮点数处理器 (Posit floating point number processor ) 是由 梁峰 赵科芃 吴斌 张国和 孙齐伟 于 2020-04-27 设计创作，主要内容包括：本申请提供了一种Posit浮点数处理器,涉及计算机技术领域。为用户提供了满足Posit标准的浮点数处理器。所述Posit浮点数处理器包括：解码电路、运算电路以及编码电路；所述解码电路用于根据CPU的计算指令,获取参与运算的多个目标Posit浮点数,并将所述多个目标Posit浮点数转换为各自对应的补码形式的中间数据；所述中间数据包括多个字段：符号字段、真实指数字段、第一尾数字段以及保护位字段；所述运算电路,用于根据所述计算指令,对接收的所述解码电路输出的多个中间数据进行运算,得到以补码形式的中间数据表示的运算结果；所述编码电路,用于根据所述计算指令中的指定格式,将所述运算结果转换为所述指定格式的Posit浮点数。(The application provides a Posit floating point number processor, and relates to the technical field of computers. A floating-point number processor that meets the Posit standard is provided for the user. The Posit floating point number processor includes: a decoding circuit, an arithmetic circuit, and an encoding circuit; the decoding circuit is used for acquiring a plurality of target Posit floating point numbers participating in operation according to a calculation instruction of the CPU, and converting the plurality of target Posit floating point numbers into intermediate data in a complementary code form corresponding to each target Posit floating point number; the intermediate data includes a plurality of fields: a sign field, a true exponent field, a first mantissa field, and a protection bit field; the arithmetic circuit is used for carrying out arithmetic on a plurality of received intermediate data output by the decoding circuit according to the calculation instruction to obtain an arithmetic result represented by the intermediate data in a complementary code form; and the coding circuit is used for converting the operation result into a Posit floating point number in a specified format according to the specified format in the calculation instruction.)

1. A Posit floating point number processor, comprising: a decoding circuit, an arithmetic circuit, and an encoding circuit;

the decoding circuit is used for acquiring a plurality of target Posit floating point numbers participating in operation according to a calculation instruction of the CPU, and converting the plurality of target Posit floating point numbers into intermediate data in a complementary code form corresponding to each target Posit floating point number; the intermediate data includes a plurality of fields: a sign field, a true exponent field, a first mantissa field, and a protection bit field;

the arithmetic circuit is used for carrying out arithmetic on a plurality of received intermediate data output by the decoding circuit according to the calculation instruction to obtain an arithmetic result represented by the intermediate data in a complementary code form;

and the coding circuit is used for converting the operation result into a Posit floating point number in a specified format according to the specified format in the calculation instruction.

2. The Posit floating point number processor of claim 1, wherein the decoding circuit comprises: a first exclusive-or device, a second exclusive-or device, an inverted leading zero detection circuit device, a first shift circuit device, a first splicing circuit device, a first extraction circuit device, and the following modules:

the register real symbol determining module is used for carrying out XOR operation on the highest bit of the target Posit floating point number and the second highest bit of the target Posit floating point number through the first XOR device to obtain a real symbol of a register field of the target Posit floating point number;

the region field unifying module is used for removing the highest bit and the second highest bit of the target Posite floating point number for the first time, removing the highest bit and the second lowest bit of the target Posite floating point number for the second time, and then performing XOR operation on the result of the first removal and the result of the second removal through the second XOR device to obtain a region unifying field;

the reverse leading zero detection circuit device is used for detecting the reverse leading zero value of the region field;

the extraction module is used for shifting out the highest three bits of the target Posit floating point number through the first shift circuit device and shifting left assigned numbers of the residual fields of the target Posit floating point number after the highest three bits are shifted out; the specified bit number is obtained according to the output of the reverse leading zero detection circuit device;

the extraction module is further configured to extract an exponent field and a second mantissa field of the target Posit floating point number from the left-shifted target Posit floating point number according to the bit width of the exponent field of the target Posit floating point number;

the real exponent determining module is used for negating the exponent field when the target Posit floating point number is a negative number, and splicing the exponent field or the negated exponent field with the value field of the register field through the first splicing circuit device to obtain and output a real exponent field in intermediate data corresponding to the target Posit floating point number;

a first mantissa field determining module, configured to perform zero padding on a low bit of the second mantissa field according to a maximum bit width of the first mantissa field to obtain a first mantissa field, and output the first mantissa field; the maximum bit width of the first mantissa field is obtained by subtracting the bit width of the sign bit of the target Posite floating point number from the total bit width of the target Posite floating point number, the bit width of the exponent field, and the minimum bit width of the register field;

a protection bit output module, configured to use a field with a value of 0 for each bit as the protection bit field, and output the protection bit field; the bit width of the protection bit field is 3.

3. The Posit floating point number processor of claim 1, wherein the intermediate data further comprises an infinity field and a zero value field; the decoding circuit further includes: an infinite number determining module and a zero value judging module;

the infinity determination module is configured to set an infinity number segment of intermediate data corresponding to the target Posit floating point number to true when the target Posit floating point number is an infinity number;

and the zero value judging module is used for setting a zero value field of intermediate data corresponding to the target Posit floating point number to be true when the target Posit floating point number is zero.

4. The Posit floating point number processor of claim 3, wherein the intermediate data further comprises a sign field; the decoding circuit further includes: a symbol judgment module;

and the symbol judgment module is used for determining the symbol of the target Posit floating point number according to the highest bit of the target Posit floating point number, taking the symbol of the target Posit floating point number as the symbol of the intermediate data corresponding to the target Posit floating point number, and outputting the symbol field of the intermediate data corresponding to the target Posit floating point number as the symbol of the intermediate data.

5. The Posit floating point number processor of claim 1, wherein the encoding circuit comprises: a second extraction circuit device, a second shift circuit device, a second stitching circuit device, and the following modules:

an exponent field encoding module, configured to extract, by the second extraction circuit device, a field with a bit width that is the same as a bit width of an exponent encoding field from a lowest bit to a highest bit in a true exponent field of the operation result, obtain the exponent encoding field according to the field with the bit width that is the same as the bit width of the exponent encoding field, and extract the true exponent field after the field with the bit width that is the same as the bit width of the exponent encoding field as a numerical value corresponding to the regime encoding field;

the region format determining module is used for determining the filling format of the region coding field according to the symbol field of the operation result and the symbol of the region coding field;

the region field coding module is used for sequentially splicing the filling format, the exponent coding field, the first mantissa field of the operation result and the protection bit field of the operation result by using the second splicing circuit device to obtain a spliced field, and arithmetically right-shifting the spliced field by using the second shifting circuit device according to a numerical value corresponding to the region coding field to obtain the region coding field;

and the floating point number result determining module is used for rounding the spliced field after right shifting by using the protection bit field, and adding the sign field of the operation result to the highest bit of the spliced field after rounding to obtain the Posite floating point number in the specified format.

6. The Posit floating point number processor of claim 5, wherein the encoding circuit further comprises an output module:

the output module is used for directly outputting the Posite floating point number in the specified format as an infinite number encoding field representing an infinite number when the infinite number field of the intermediate data is true;

the output module is further configured to directly output the Posite floating point number in the specified format as an infinity encoded field representing a zero value when the zero value field of the intermediate data is true.

7. The Posit floating point number processor of claim 2, wherein the inverted leading zero detection circuit device comprises an OR device, a first inverting device, a second inverting device;

the reverse leading zero detection circuit device is used for respectively carrying out negation operation on the 0 th bits of a plurality of input fields with the bit width of 2 by using the first negation device, and then respectively carrying out OR operation on a plurality of negation results and the 1 st bits of the plurality of input fields with the bit width of 2 by using the OR device to obtain the 0 th bits of a plurality of output fields; the input field with the bit width of 2 is obtained after the region unified field is processed by a binary circuit;

the reverse leading zero detection circuit device is further configured to perform an or operation on the 0 th bits of the input fields with the bit width of 2 and the 1 st bits of the input fields with the bit width of 2 by using the or device, respectively, to obtain the 1 st bits of the output fields;

the reverse leading zero detection circuit device is also used for splicing the output fields to obtain the inverted code of the value of the region uniform field.

8. The Posit floating point number processor of claim 7, wherein the regime value calculation module comprises:

the region value calculation submodule is used for negating the inverse code output by the reverse leading zero detection circuit device when the real symbol of the region field is positive, and then adding the real symbol of the region field to the highest bit of the inverse code output by the reversed reverse leading zero detection circuit device to obtain the value field of the region field;

and the region value calculation sub-module is further used for adding the real symbol of the region field to the highest bit of the inverse code output by the reverse leading zero detection circuit device when the real symbol of the region field is negative, so as to obtain the value field of the region field.

9. The Posit floating point number processor of claim 5, wherein the floating point number result determination module comprises:

a protection bit sub-module, configured to add 1 to the lowest bit of the right-shifted concatenation field when each bit of the right-shifted concatenation field is 0, and keep the right-shifted concatenation field unchanged when all values of the right-shifted concatenation field are 1;

the protection bit submodule is further configured to, when values of any two bits in the concatenation field after right shift are different and the value of the protection bit is greater than 4, add 1 to the lowest bit of the concatenation field after right shift, or when any two bits in the concatenation field after right shift are different, and when the value of the protection bit is equal to 4 and the lowest bit of the concatenation field after right shift is 1, add 1 to the lowest bit of the concatenation field after right shift.

10. The Posit floating point number processor of claim 5, wherein the exponent field encoding module is further configured to, when the sign field of the intermediate data represents a negative number, invert the field having the same bit width as the exponent encoded field to obtain the exponent encoded field;

and when the sign field of the intermediate data represents a positive number, taking the field with the bit width being the same as that of the exponent encoding field as the exponent encoding field.