阅读说明：本技术 标准单元库的耐低压超低功率边沿触发触发器 (Low-voltage-resistant ultra-low power edge trigger of standard cell library ) 是由 S.米塔尔 J.S.巴蒂亚 R.德什潘德 帕文德.库马尔.拉纳 尼克希拉.C.M. 阿布舍 于 2019-07-08 设计创作，主要内容包括：一种用于设计低功率集成电路(IC)的方法和触发器。该方法包括接收时钟信号、数据信号和互补数据信号中的至少一个。互补数据信号由存在于触发器中的输入数据反相器产生。此外,该方法包括当时钟信号处于低逻辑电平时,基于接收到的时钟信号、数据信号和互补数据信号中的至少一个来生成至少一个主内部信号。此外,该方法包括当时钟信号处于高逻辑电平时,基于接收到的时钟信号和生成的至少一个主内部信号中的至少一个来生成至少一个从内部信号。此外,该方法包括基于生成的至少一个从内部信号来生成输出信号。(A method and flip-flop for designing a low power Integrated Circuit (IC). The method includes receiving at least one of a clock signal, a data signal, and a complementary data signal. The complementary data signals are generated by an input data inverter present in the flip-flop. Further, the method includes generating at least one primary internal signal based on at least one of the received clock signal, the data signal, and the complementary data signal when the clock signal is at a low logic level. Further, the method includes generating at least one slave internal signal based on at least one of the received clock signal and the generated at least one master internal signal when the clock signal is at a high logic level. Further, the method includes generating an output signal based on the generated at least one secondary internal signal.)

1. A method of configuring a low power Integrated Circuit (IC) using flip-flops, the method comprising:

receiving, by a master latch, at least one of a clock signal, a data signal, and a complementary data signal generated by an input data inverter of a flip-flop; and

when the clock signal is at a low logic level, at least one main internal signal is generated by the main latch based on at least one of the received clock signal, the data signal, and the complementary data signal.

2. The method of claim 1, further comprising:

generating, by the slave latch, at least one slave internal signal based on at least one of the received clock signal and the generated at least one master internal signal when the clock signal is at a high logic level; and

an output signal is generated by an output inverter driver in response to receiving the generated at least one slave internal signal.

3. The method of claim 1, wherein the master latch is predominantly p-type metal oxide semiconductor (PMOS).

4. The method of claim 2, wherein the slave latch is predominantly n-type metal oxide semiconductor (NMOS).

5. A method of configuring a low power Integrated Circuit (IC) using flip-flops, the method comprising:

receiving, by a master latch, at least one of a clock signal, a complement clock signal, a data signal, and a complement data signal, wherein the complement clock signal is generated by a clock inverter of a flip-flop and the complement data signal is generated by a data inverter of the flip-flop; and

when the clock signal is at a low logic level, at least one main internal signal is generated by the main latch based on at least one of the received clock signal, the complementary clock signal, the data signal, and the complementary data signal.

6. The method of claim 5, further comprising:

generating, by the slave latch, at least one slave internal signal based on at least one of the generated at least one master internal signal and the received clock signal when the clock signal is at a high logic level; and

receiving, by an output inverter driver, the at least one slave internal signal and generating an output signal.

7. The method of claim 5, wherein the master latch is predominantly n-type metal oxide semiconductor (NMOS).

8. The method of claim 6, wherein the slave latch is predominantly p-type metal oxide semiconductor (PMOS).

9. A flip-flop for a low power Integrated Circuit (IC), the flip-flop comprising:

an input data inverter; and

a master latch configured to:

receiving at least one of a clock signal, a data signal, and a complementary data signal generated by an input data inverter; and

when the clock signal is at a low logic level, at least one main internal signal is generated based on at least one of the received clock signal, the data signal, and the complementary data signal.

10. The flip-flop of claim 9, further comprising:

a slave latch configured to generate at least one slave internal signal based on at least one of the clock signal and the at least one master internal signal when the clock signal is at a high logic level; and

an output inverter driver configured to generate an output signal in response to receiving the generated at least one slave internal signal.

11. The flip-flop of claim 9, wherein the master latch is predominantly p-type metal oxide semiconductor (PMOS).

12. The flip-flop of claim 10, wherein the slave latch is predominantly n-type metal oxide semiconductor (NMOS).

Technical Field

The present disclosure relates to the field of Integrated Circuits (ICs), and more particularly, to low voltage tolerant ultra-low power edge triggered master-slave flip-flops of standard cell libraries.

Background

The term "flip-flop" or "flip-flop" is commonly used to describe or refer to a clocked electronic circuit having two stable states, which is used to store a value. Flip-flops typically include two latch circuits. Flip-flops have many different applications and are widely used in digital circuits. One important use of a flip-flop is to store bits of an instruction in an instruction pipeline of a Central Processing Unit (CPU) or a Graphics Processing Unit (GPU). In conventional flip-flop electronic circuits, data is stored in cross-coupled inverters. The first latch, or "master" latch, includes a pass gate and cross-coupled inverters. The second latch or "slave" latch similarly includes a transmission gate and cross-coupled inverters. The clock signal controls the operation of the two transmission gates and thus the operation of the flip-flop circuit.

Generally, for low power chip designs, there are many power elements where clock power is critical. Clock power is the main contributor to total block power (total power), so optimizing the clock power of a flip-flop design will reduce the overall block power. However, using conventional stacking techniques can reduce flip-flop performance, which affects overall block frequency and increases overall area.

Fig. 1 is a circuit diagram of a related art flip-flop in which a master latch uses a related art blocking latch (jam latch) which is not robust in nature. In addition, the related art flip-flop circuit uses a large number of single-stack inverters, which results in high power consumption. A data inverter present in the flip-flop receives the data signal D and generates a complementary data signal DN. In addition, when the Clock (CLK) signal is at low logic, nodes N1 and N2 are set (cut) and go to the slave latch according to the D and DN signals. When CLK goes to high logic, the master latch closes and the previous value is retained by the block latch. From nodes N1 and N2, signals Q and QN are generated and are retained by the blocking latch when CLK goes to low logic.

In view of the above, there is a need to provide a flip-flop design that has extremely low clock power with minimal impact on cell area and performance.

The above-mentioned shortcomings, disadvantages and problems are addressed herein and will be understood by reading and studying the following specification.

The above information is presented as background information only to aid in understanding the present disclosure. No determination is made as to whether any of the above can be applied as prior art with respect to the present disclosure, nor is an assertion made.

Disclosure of Invention

According to an aspect of the present disclosure, a method and flip-flop for designing a low power Integrated Circuit (IC) are provided. The method includes receiving at least one of a clock signal, a data signal, and a complementary data signal. The complementary data signals are generated by an input data inverter present in the flip-flop. Further, the method includes generating at least one primary internal signal based on at least one of the received clock signal, the data signal, and the complementary data signal when the clock signal is at a low logic level. Further, the method includes generating at least one slave internal signal based on at least one of the received clock signal and the generated at least one master internal signal when the clock signal is at a high logic level. Further, the method includes generating an output signal based on the generated at least one secondary internal signal.

According to yet another aspect of the present disclosure, a method and flip-flop for designing a low power Integrated Circuit (IC) are provided. The method includes receiving at least one of a clock signal, a complementary clock signal, a data signal, and a complementary data signal. The complementary clock signals are generated by clock inverters present in the flip-flops. The complementary data signals are generated by a data inverter present in the flip-flop. Further, the method includes generating at least one primary internal signal based on at least one of the received clock signal, the complementary clock signal, the data signal, and the complementary data signal when the clock is at a low logic level. Further, the method includes generating at least one slave internal signal based on at least one of the generated at least one master internal signal and the received clock signal when the clock signal is at a high logic level. Further, the method includes receiving at least one slave internal signal and generating an output signal.

According to an embodiment of the present disclosure, a method for designing a low power Integrated Circuit (IC) using a flip-flop is provided. The method includes receiving at least one of a clock signal, a data signal, and a complementary data signal. The complementary data signals are generated by an input data inverter present in the flip-flop. Further, the method includes generating at least one primary internal signal based on at least one of the received clock signal, the data signal, and the complementary data signal when the clock signal is at a low logic level. Further, the method includes generating at least one slave internal signal based on at least one of the received clock signal and the generated at least one master internal signal when the clock signal is at a high logic level. Further, the method includes generating an output signal based on the generated at least one secondary internal signal.

According to an embodiment of the present disclosure, a method for designing a low power Integrated Circuit (IC) using a flip-flop is provided. The method includes receiving at least one of a clock signal, a complementary clock signal, a data signal, and a complementary data signal. The complementary clock signals are generated by clock inverters present in the flip-flops. The complementary data signals are generated by a data inverter present in the flip-flop. Further, the method includes generating at least one master internal signal based on at least one of the received clock signal, the complementary clock signal, the data signal, and the complementary data signal when the clock is at a low logic level. Further, the method includes generating at least one slave internal signal based on at least one of the generated at least one master internal signal and the received clock signal when the clock signal is at a high logic level. Further, the method includes receiving at least one slave internal signal and generating an output signal.

According to an embodiment of the present disclosure, a flip-flop for designing a low power Integrated Circuit (IC) is provided. The flip-flop includes a master latch configured to receive at least one of a clock signal, a data signal, and a complementary data signal. The complementary data signals are generated by an input data inverter present in the flip-flop. Further, the master latch is configured to generate at least one master internal signal based on at least one of the received clock signal, the data signal, and the complementary data signal when the clock signal is at a low logic level. Further, the flip-flop includes a slave latch configured to generate at least one slave internal signal based on at least one of the clock signal and the at least one master internal signal when the clock signal is at a high logic level. Further, the flip-flop includes an output inverter driver configured to generate an output signal from the internal signal based on the generated at least one.

In an embodiment of the present disclosure, the master latch is predominantly a P-type Metal oxide Semiconductor (PMOS), and the slave latch is predominantly an N-type Metal oxide Semiconductor (NMOS).

According to an embodiment of the present disclosure, a flip-flop for designing a low power Integrated Circuit (IC) is provided. The flip-flop includes a master latch configured to receive at least one of a clock signal, a complement clock signal, a data signal, and a complement data signal. The complementary clock signals are generated by clock inverters present in the flip-flops. The complementary data signals are generated by a data inverter present in the flip-flop. Further, the master latch is configured to generate at least one master internal signal based on at least one of the received clock signal, the complementary clock signal, the data signal, and the complementary data signal when the clock signal is at a low logic level. Further, the flip-flop includes a slave latch configured to generate at least one slave internal signal based on at least one of the received at least one master internal signal and the clock signal when the clock signal is at a high logic level. Further, the flip-flop includes an output inverter driver configured to receive the at least one slave internal signal and generate an output signal.

In embodiments of the present disclosure, the master latch is dominated by n-type metal oxide semiconductor (NMOS) and the slave latch is dominated by p-type metal oxide semiconductor (PMOS).

The above and other aspects, features and advantages of certain embodiments of the present disclosure will be more apparent and readily appreciated when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following description, while indicating exemplary embodiments and numerous specific details thereof, is given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the exemplary embodiments herein without departing from the spirit thereof, and the exemplary embodiments herein include all such modifications.

Drawings

Various embodiments are illustrated in the drawings, wherein like reference numerals represent corresponding parts throughout the different views. Various embodiments herein will be better understood from the following description with reference to the accompanying drawings, in which:

fig. 1 is a circuit diagram of a related art flip-flop;

FIG. 2 is a block diagram illustrating a flip-flop circuit design for optimizing clock power for low power Integrated Circuits (ICs), according to an embodiment; and

FIG. 3 is a block diagram illustrating a flip-flop circuit design with clocked inverters for optimizing clock power for a low power Integrated Circuit (IC) according to an embodiment.

Detailed Description

In the following description, certain exemplary embodiments, various features and advantageous details thereof are explained more fully with reference to the accompanying drawings only. Descriptions of well-known components and processing techniques are omitted so as to not unnecessarily obscure the illustrative embodiments. The description herein is merely for the purpose of facilitating understanding of ways in which the exemplary embodiments herein may be practiced and further enabling those of skill in the art to practice the exemplary embodiments herein. Accordingly, the present disclosure should not be construed as limiting the scope of the exemplary embodiments.

Example embodiments herein implement methods and flip-flop circuit designs for low power Integrated Circuits (ICs). The flip-flop includes a master latch configured to receive at least one of a clock signal, a data signal, and a complement data signal, wherein the complement data signal is generated by an input data inverter present in the flip-flop. Further, the master latch is configured to generate at least one master internal signal based on at least one of the received clock signal, the data signal, and the complementary data signal when the clock signal is at a low logic level. Further, the flip-flop includes a slave latch configured to generate at least one slave internal signal based on at least one of the received clock signal and the generated at least one master internal signal when the clock signal is at a high logic level. Further, the flip-flop includes an output inverter driver configured to generate an output signal from the internal signal based on the generated at least one. Referring now to the drawings, and more particularly to fig. 2-3, wherein like reference numerals represent corresponding features consistently throughout the several views, there is shown an exemplary embodiment.

FIG. 2 is a flip-flop 200 circuit design for optimizing clock power for a low power Integrated Circuit (IC), according to an example embodiment.

The exemplary embodiments herein provide a flip-flop 200 circuit design for low power Integrated Circuits (ICs). The flip-flop 200 includes a master latch 202, the master latch 202 configured to receive at least one of a clock signal, a data signal, and a complement data signal, wherein the complement data signal is generated by an input data inverter 204 present in the flip-flop 200. The master latch 202 is predominantly p-type metal oxide semiconductor (PMOS). Further, the master latch 202 is configured to generate at least one master internal signal based on at least one of the received clock signal, data signal, and complementary data signal when the clock signal is at a low logic level. Further, the flip-flop 200 circuit design includes a slave latch 206, the slave latch 206 configured to generate at least one slave internal signal based on at least one of the received clock signal and the generated at least one master internal signal when the clock signal is at a high logic level. The slave latch 206 is predominantly n-type metal oxide semiconductor (NMOS). Further, the flip-flop 200 circuit design includes an output inverter driver 208, the output inverter driver 208 configured to generate an output signal from the internal signal based on the generated at least one.

For example, the input data inverter 204 present in the flip-flop 200 generates the complementary data signal Db from the data signal D. Db is an inverted data signal, so the Db and D signals are complementary to each other. Further, the master latch 202 may be configured to generate at least one master internal signal based on at least one of the received clock signal, the data signal D, and the complementary data signal Db when the clock signal is at a low logic level. Due to the generation of at least one main internal signal, the node nn4 or nn3 will pull up. In addition, nodes nn3 and nn4 go to slave latch 206. These nodes are complementary to each other, which means that if nn3 is 1, then nn4 should be 0. Furthermore, when the clock signal goes to high logic, nodes nn3 and nn4 will short circuit and result in a direct power supply. Slave latch 206 may signal and maintain nodes nn3 and nn4, which facilitates the generation of an output using output inverter driver 208 present in slave latch 206. Based on the node nn3 or nn4, the node nn1 or nn2 can be discharged and charged, respectively. Further, the output inverter driver 208 may use the node nn1 to generate the output Q. When CLK usage goes from latch 206 to low logic, node nn1 or nn2 may be maintained and the same cycle repeated when new data arrives at CLK-0. FIG. 3 is a flip-flop 400 circuit design with a clocked inverter 404 for optimizing clock power for a low power Integrated Circuit (IC) according to an example embodiment.

The exemplary embodiments herein provide a method of designing a low power IC using flip-flop 400. The method includes receiving at least one of a clock signal, a complementary clock signal, a data signal, and a complementary data signal, wherein the complementary clock signal is generated by a clock inverter 404 present in the flip-flop 400. The complementary data signal is generated by a data inverter 406 present in the flip-flop 400. Further, the method includes generating at least one primary internal signal based on at least one of the received clock signal, the complementary clock signal, the data signal, and the complementary data signal when the clock is at a low logic level. Further, the method includes generating at least one slave internal signal based on at least one of the generated at least one master internal signal and the received clock signal when the clock signal is at a high logic level. Further, the method includes receiving at least one slave internal signal and generating an output signal.

The exemplary embodiments herein provide a flip-flop 400 for designing low power ICs. The flip-flop 400 includes a master latch 402, the master latch 402 configured to receive at least one of a clock signal, a complementary clock signal, a data signal, and a complementary data signal. The complementary clock signals are generated by a clock inverter 404 present in the flip-flop 400. The complementary data signal is generated by a data inverter 406 present in the flip-flop 400. Further, the master latch 402 is configured to generate at least one master internal signal based on at least one of the received clock signal, complementary clock signal, data signal, and complementary data signal when the clock is at a low logic level. Further, flip-flop 400 includes a slave latch 408, slave latch 408 configured to generate at least one slave internal signal based on at least one of the received at least one master internal signal and the clock signal when the clock signal is at a high logic level. Further, the flip-flop 400 includes an output inverter driver 410, the output inverter driver 410 configured to receive at least one slave internal signal and generate an output signal. In an exemplary embodiment, the master latch is dominated by n-type metal oxide semiconductor (NMOS) and the slave latch is dominated by p-type metal oxide semiconductor (PMOS). The flip-flop 400 design is a complementary version of the flip-flop 200, with the master latch being NMOS based and the slave latch being PMOS based in the flip-flop 400 design. The exemplary embodiments disclosed herein may be implemented by at least one software program running on at least one hardware device and performing the functions of the control elements. The elements shown in fig. 2 and 3 may be at least one of a hardware device or a combination of a hardware device and a software module.

The foregoing description illustrates various exemplary embodiments, which may be readily modified and/or adapted by others using current knowledge without departing from the general concept of the disclosure, and therefore such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Thus, while the exemplary embodiments herein have been described, those skilled in the art will recognize that the exemplary embodiments herein can be practiced with modification within the spirit and scope of the specification.