阅读说明：本技术 半导体装置和电源转换装置 (Semiconductor device and power conversion device ) 是由 古川智康 守田俊章 川濑大助 田畑利仁 于 2019-07-09 设计创作，主要内容包括：本发明提供一种半导体装置和电源转换装置,该半导体装置具有包含化学镀Ni层的电极,且化学镀Ni层中裂纹的产生少,可靠性高。半导体装置的特征在于,具备半导体元件和形成于前述半导体元件的第一表面的第一电极,前述第一电极为包含第一化学镀Ni层的层叠结构,前述第一化学镀Ni层含有Ni(镍)和P(磷)作为组成,前述第一化学镀Ni层的P(磷)浓度为2.5wt％以上6wt％以下,且前述第一化学镀Ni层中的Ni<Sub>3</Sub>P的结晶化率为0％以上20％以下。(The invention provides a semiconductor device and a power conversion device, the semiconductor device has an electrode including a chemical plating Ni layer, and the chemical plating Ni layer has less crack generation and high reliability. A semiconductor device is characterized by comprising a semiconductor element and a first electrode formed on a first surface of the semiconductor element, wherein the first electrode has a laminated structure including a first Ni (nickel) -plated layer having a composition containing Ni (nickel) and P (phosphorus), the P (phosphorus) concentration of the first Ni-plated layer is 2.5 wt% or more and 6 wt% or less, and Ni in the first Ni-plated layer 3 The P crystallization rate is 0% to 20%.)

1. A semiconductor device is characterized in that a semiconductor element,

the semiconductor device includes a semiconductor element and a first electrode formed on a first surface of the semiconductor element,

the first electrode is a laminated structure including a first electroless Ni plating layer,

the first electroless Ni plating layer contains Ni that is nickel and P that is phosphorus as a composition,

the first chemical Ni-plating layer has a P concentration of 2.5 wt% or more and 6 wt% or less, and Ni in the first chemical Ni-plating layer₃The P crystallization rate is 0% to 20%.

2. The semiconductor device according to claim 1, wherein a crystallization ratio of Ni in the first electroless Ni plating layer is 70% to 95%.

3. The semiconductor device according to claim 1, wherein the first electroless Ni plating layer is disposed on the first electrode on a side opposite to the first surface, and is bonded to the conductive member through a copper sintered layer.

4. The semiconductor device according to claim 1,

further comprises a second electrode formed on a second surface of the semiconductor element opposite to the first surface,

the second electrode is a laminated structure comprising a second electroless Ni plating layer,

the second electroless Ni plating layer contains Ni and P as a composition,

the P concentration of the second chemical Ni-plating layer is more than 2.5 wt% and less than 6 wt%, and Ni in the second chemical Ni-plating layer₃The P crystallization rate is 0% to 20%.

5. The semiconductor device according to claim 4, wherein a crystallization ratio of Ni in the second electroless Ni-plated layer is 70% or more and 95% or less.

6. The semiconductor device according to claim 4, wherein the second electroless Ni-plated layer is disposed on the second electrode on the opposite side of the second surface, and is bonded to the conductive member via a copper sintered layer.

7. The semiconductor device according to claim 4,

the laminated structure of the first electrode and the laminated structure of the second electrode are symmetrically arranged with the semiconductor element interposed therebetween,

the film thickness of the film constituting the laminated structure of the first electrode is substantially the same as the film thickness of the film constituting the symmetrical laminated structure of the second electrode.

8. The semiconductor device according to claim 4, wherein the second electrode is a pad to which a bonding wire is bonded.

9. A power conversion device is characterized by comprising:

a pair of DC terminals,

an alternating current terminal equal in number to the number of phases of the alternating current output,

a switch lead wire connected between the pair of DC terminals and connecting two parallel circuits composed of a switching element and a diode of reverse polarity in series and having the same number of phases as the AC output, and

a gate circuit that controls the switching element;

the switching element is the semiconductor device according to any one of claims 1 to 8.

Technical Field

The present invention relates to a structure of a semiconductor device and a method for manufacturing the same, and more particularly to a technique effective for downsizing and improving reliability of a power conversion device on which the semiconductor device is mounted.

Background

Semiconductor devices are used in a wide range of fields such as system LSIs (Large Scale Integration), power conversion devices, and control devices for hybrid vehicles. In the semiconductor device, for example, electrical connection between an electrode terminal of an electronic component and an electrode terminal of a circuit pattern on a circuit board is mainly performed by "solder" or "solder alloy" containing lead.

On the other hand, the use of lead is strictly restricted from the viewpoint of global environmental protection, and the use of lead has been restricted, and bonding of electrodes and the like with a material not containing lead has been developed. In particular, as for "high-temperature solder", no material effective as a substitute thereof has been found yet. In the technique for mounting a semiconductor device, it is necessary to use "lead-free multilevel solder (the frame フリー, the frame は/だ)", and therefore, the advent of a material replacing this "high-temperature solder" is expected.

In addition, a power module, which is a main component of a power converter such as an inverter, needs to be reduced in cost and size. Similarly, the power device chip in the power supply module also needs to be reduced in cost and size, and a new technology for realizing a high output current density of the power device chip is required. If the output current density is high, the loss of the power device per unit chip area increases, and the chip temperature rises. Therefore, a highly reliable package mounting technique capable of operating at high temperatures even with increased loss density is required.

Under such a background, a bonding material for bonding electrodes using a composite material of metal particles and an organic compound as a high-temperature and highly reliable material has been proposed instead of "high-temperature solder".

For example, patent document 1 discloses "a semiconductor device in which a bonding material containing copper oxide (CuO) particles and a reducing agent composed of an organic material is used to bond the electrodes in a reducing atmosphere" as a bonding technique capable of obtaining excellent bonding strength to Ni or Cu electrodes.

In the semiconductor device described in patent document 1, copper particles of 100nm or less are generated during heating and reduction, and the copper particles are sintered and bonded to each other. The bonding technique using copper oxide (CuO) particles described in patent document 1 can improve the bonding property to Ni and Cu as compared with conventional nanoparticle bonding, and is expected as a bonding material for Ni electrodes and Cu electrodes.

For example, an IGBT (Insulated Gate bipolar transistor) used in an inverter of a power converter, a flywheel diode, and the like can be electrically connected to a connection terminal of a Ni electrode of a power semiconductor chip via a bonding layer formed of a copper sintered layer.

As the Ni electrode of the power semiconductor chip, there is a Ni electrode forming method in which a Ni layer is grown on the surface of Al metal by an electroless plating method, for example.

Patent document 2 discloses a "semiconductor device having a Ni electrode formed by electroless plating". The semiconductor device described in patent document 2 includes a first Ni plating layer having a low phosphorus concentration and a second Ni plating layer having a high phosphorus concentration on a semiconductor chip, and the phosphorus concentration of the first Ni plating layer is 4 wt% or more and less than 6 wt%. When the phosphorus concentration of the Ni plating layer is low, an alloy of nickel and phosphorus (e.g., Ni) is less likely to occur even if heat treatment is performed₃P) is hard to crack the plating film. Further, it is described that the plated film is entirely crystallized by heat treatment.

Patent document 3 discloses a "semiconductor device having a Ni/Au electrode formed by electroless plating". In the semiconductor device described in patent document 3, the Ni plating layer is made amorphous, so that the crystal structure does not change with changes in temperature and stress, and the plating film does not crack due to grain boundary voids, thereby improving reliability.

Disclosure of Invention

Problems to be solved by the invention

However, the present inventors have conducted studies and found that, as in patent document 2, when the phosphorus concentration is 4 wt% or more and less than 6 wt%, cracks are likely to occur depending on the kind of electroless Ni plating bath and the heat treatment conditions after the formation of the plating film. If cracks are generated in the electroless Ni plating film, the cracks may be enlarged by temperature and stress changes, and the characteristics may be poor.

Further, if there is a crack in the electroless Ni plating electrode of the semiconductor chip, in the case of electrically connecting the connection terminal using the bonding layer formed of the copper sintered layer, there is a problem as follows: copper diffuses from the bonding layer to the power semiconductor chip, thereby increasing leakage current of the device, deteriorating breakdown voltage of the device, and changing characteristics of the device.

Accordingly, an object of the present invention is to provide a semiconductor device having an electrode including an electroless Ni plating layer, in which generation of cracks in the electroless Ni plating layer is small and reliability is high, and a method for manufacturing the semiconductor device.

Means for solving the problems

In order to solve the above problems, the present invention is characterized by comprising a semiconductor element and a first electrode formed on a first surface of the semiconductor element, wherein the first electrode has a laminated structure including a first Ni electroless plating layer, the first Ni electroless plating layer contains Ni (nickel) and P (phosphorus) as a composition, the P (phosphorus) concentration of the first Ni electroless plating layer is 2.5 wt% or more and 6 wt% or less, and Ni in the first Ni electroless plating layer is Ni (phosphorus) in the first Ni electroless plating layer₃The P crystallization rate is 0% to 20%.

Further, the present invention is a power conversion device including: a pair of dc terminals, ac terminals equal in number to the number of phases of the ac output, switching leads connected between the pair of dc terminals and connecting two parallel circuits each including a switching element and a diode of opposite polarity in series and equal in number to the number of phases of the ac output, and a gate circuit for controlling the switching elements; the switching element is a semiconductor device having the above-described characteristics.

Effects of the invention

According to the present invention, a semiconductor device having an electrode including an electroless Ni plating layer in which generation of cracks is small and reliability is high can be realized, and a manufacturing method thereof.

This makes it possible to reduce the size and increase the reliability of the power conversion device on which the semiconductor device is mounted.

Problems, configurations, and effects other than those described above will be apparent from the following description of embodiments.

Drawings

Fig. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention.

Fig. 2 is a sectional view of each step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

Fig. 3 is a sectional view of each step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

Fig. 4 is a view showing a process flow of electroless Ni plating according to the first embodiment of the present invention.

Fig. 5 is a characteristic diagram showing the relationship between the phosphorus concentration and the Ni crystallization ratio in the Ni plating film of the electroless Ni plating according to the first embodiment of the present invention and the occurrence of cracks.

FIG. 6 is a graph fitted with an X-ray diffraction pattern of electroless Ni plating (bath A) according to the first embodiment of the present invention.

FIG. 7 is a graph fitted with an X-ray diffraction pattern of electroless Ni plating (B bath) according to the first embodiment of the present invention.

FIG. 8 is a graph fitted with an X-ray diffraction pattern of electroless Ni plating (C bath) according to the first embodiment of the present invention.

FIG. 9 is a graph fitted with an X-ray diffraction pattern of electroless Ni plating (D bath) according to the first embodiment of the present invention.

FIG. 10 is a graph fitted with an X-ray diffraction pattern of electroless Ni plating (E bath) according to the first embodiment of the present invention.

FIG. 11 is a graph fitted with an X-ray diffraction pattern of electroless Ni plating (F bath) according to a first embodiment of the present invention.

FIG. 12 is a graph fitted with an X-ray diffraction pattern of electroless Ni plating (G bath) according to the first embodiment of the present invention.

FIG. 13 shows the Ni crystallization ratio and Ni content of the electroless Ni plating (F bath) film according to the first embodiment of the present invention₃P crystallization rate, and annealing temperature dependence.

Fig. 14 is a characteristic diagram showing the annealing temperature dependence of the X-ray diffraction pattern of the electroless Ni plating (F bath) film according to the first embodiment of the present invention.

FIG. 15 is a view showing Ni resulting from differences in phosphorus concentration in electroless Ni plating according to the first embodiment of the present invention₃P crystallization rate, and annealing temperature dependence.

Fig. 16A is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention.

Fig. 16B is a cross-sectional view of the semiconductor device of fig. 16A after wire bonding.

Fig. 17 is a sectional view of a semiconductor device according to a third embodiment of the present invention.

Fig. 18 is a circuit diagram showing a schematic configuration of a power converter according to a fourth embodiment of the present invention.

Description of the symbols

90: a Si wafer (Si substrate); 100. 200 and 300: a semiconductor device; 101: a ceramic (insulating) substrate; 102: a conductive member; 103: a copper sintered layer; 104: a Ni layer (electroless Ni plating); 104 a: the surface of the Ni layer; 106 a: a first Al metal layer; 106 b: a second Al metal layer; 107: a Cu diffusion preventing layer; 108: a semiconductor substrate; 108 a: a p-type semiconductor layer; 108 b: n is^－A type-shifting layer; 108 c: n is⁺A type semiconductor layer; 108 d: a first surface (of a semiconductor substrate); 108 e: a second surface (of the semiconductor substrate); 109: an anode electrode (Al metal layer); 110: an insulating oxide film; 111: a passivation film (surface protection film); 112: an electrode structure body (cathode electrode) of the first semiconductor chip; 113: an electrode structure body (anode electrode) of the second semiconductor chip; 150: a semiconductor element; 151: a bonding wire; 301: an electrode structure body (anode electrode) of the third semiconductor chip; 500: a power conversion device; 501-506: a power switching element; 511-516: grid electrodeA circuit; 521-526: a diode; 531: a P terminal; 532: an N terminal; 533: a U terminal; 534: a V terminal; 535: and a W terminal.

Detailed Description

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and detailed description of overlapping portions will be omitted.