阅读说明：本技术 一种新型音频功率放大器 (Novel audio power amplifier ) 是由 樊大伟 于 2019-12-13 设计创作，主要内容包括：本发明公开一种新型音频功率放大器,其将D类功放电路中起到积分作用的电路和AB类功放电路中起到运放作用的电路复用在一折叠式共源共栅电路中,再利用折叠式共源共栅高输出阻抗、高增益、易补偿的特点,使得性能大幅提高的情况下,不仅节约了芯片面积,进而降低芯片成本,又可以减少集成电路版图设计的工作量,进而节约设计时间。(The invention discloses a novel audio power amplifier, which multiplexes a circuit playing a role of integration in a D-type power amplifier circuit and a circuit playing a role of operational amplification in an AB-type power amplifier circuit into a folding cascode circuit, and then utilizes the characteristics of high output impedance, high gain and easy compensation of the folding cascode circuit to greatly improve the performance, thereby not only saving the area of a chip and further reducing the cost of the chip, but also reducing the workload of integrated circuit layout design and further saving the design time.)

1. A novel audio power amplifier, comprising:

a first operational amplifier module;

the multiplexing module is electrically connected with the first operational amplifier module and comprises a multiplexing circuit, a first group of switches and a second group of switches, and the multiplexing circuit is electrically connected with the first group of switches and the second group of switches respectively;

the comparison module is electrically connected with the multiplexing module;

the driving module is electrically connected with the comparison module; and

the load module is electrically connected with the driving module; wherein the content of the first and second substances,

when the first group of switches is closed and the second group of switches is open, the output end of the multiplexing circuit is electrically connected to the comparison module, so that the multiplexing module is switched to be an integration module, and the novel audio power amplifier operates in a class D power amplifier mode;

when the first group of switches is off and the second group of switches is on, the output end of the multiplexing circuit is electrically connected to the load module, so that the multiplexing module is switched to be used as a second operational amplifier module, and the novel audio power amplifier operates in an AB type power amplification mode.

2. The novel audio power amplifier of claim 1, wherein the first operational amplifier module comprises: the circuit comprises a first capacitor, a second capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor and a first operational amplifier; one end of the first capacitor receives the positive input end, and the other end of the first capacitor is electrically connected with one end of the first resistor; one end of the second capacitor receives the negative input end, and the other end of the second capacitor is electrically connected with one end of the second resistor; the other end of the first resistor is electrically connected to one end of the third resistor and the positive input end of the first operational amplifier respectively; the other end of the second resistor is electrically connected to one end of the fourth resistor and the negative input end of the first operational amplifier respectively; the other end of the third resistor is electrically connected to the negative output end of the first operational amplifier, and the other end of the fourth resistor is electrically connected to the positive output end of the first operational amplifier.

3. The novel audio power amplifier of claim 2, wherein the multiplexing circuit comprises: the first resistor, the second resistor, the third resistor, the fourth resistor, the seventh resistor and the eighth resistor are connected in series; one end of the fifth resistor is electrically connected to the other end of the third resistor and the negative output end of the first operational amplifier, and the other end of the fifth resistor is electrically connected to one end of the seventh resistor, one end of the third capacitor, and the positive input end of the multiplexing unit; one end of the sixth resistor is electrically connected to the other end of the fourth resistor and the positive output end of the first operational amplifier, and the other end of the sixth resistor is electrically connected to one end of the eighth resistor, one end of the fourth capacitor and the negative input end of the multiplexing unit; the other end of the third capacitor is electrically connected to a ninth switch in the first group of switches, and the ninth switch is electrically connected to the negative output end of the multiplexing unit; the other end of the fourth capacitor is electrically connected to a tenth switch in the first group of switches, and the tenth switch is electrically connected to the positive output end of the multiplexing unit.

4. The novel audio power amplifier of claim 3, wherein the comparison module comprises: a first comparator and a second comparator; the positive input end of the first comparator is electrically connected to the negative output end of the multiplexing unit, the positive input end of the second comparator is electrically connected to the positive output end of the multiplexing unit, and the negative input end of the first comparator and the negative input end of the second comparator receive a triangular wave signal.

5. The novel audio power amplifier of claim 4, wherein the driver module comprises: the first driver, the second driver, the first output pair of tubes and the second output pair of tubes; the input end of the first driver is electrically connected to the output end of the first comparator, and the input end of the second driver is electrically connected to the output end of the second comparator; the first output pair transistors comprise a thirty-first field effect transistor and a thirty-second field effect transistor; the second output pair transistor comprises a thirty-third field effect transistor and a thirty-fourth field effect transistor; a source electrode of the thirty-first field effect transistor receives a power supply voltage, a grid electrode of the thirty-first field effect transistor is electrically connected to the first output end of the first driver, and a drain electrode of the thirty-first field effect transistor is electrically connected to a drain electrode of the thirty-second field effect transistor; the grid electrode of the thirty-second field effect transistor is electrically connected to the second output end of the first driver, and the source electrode of the thirty-second field effect transistor is grounded; a source electrode of the thirty-third field effect transistor receives a power supply voltage, a grid electrode of the thirty-third field effect transistor is electrically connected to the first output end of the second driver, and a drain electrode of the thirty-third field effect transistor is electrically connected to a drain electrode of the thirty-fourth field effect transistor; the gate of the thirty-fourth field effect transistor is electrically connected to the second output end of the second driver, and the source of the thirty-fourth field effect transistor is grounded.

6. The novel audio power amplifier of claim 5, wherein the load module comprises a load connected to a common node of the thirty-first and thirty-second fets and a common node of the thirty-third and thirty-fourth fets.

7. The novel audio power amplifier of claim 6, wherein the first set of switches comprises a ninth switch and a tenth switch, the ninth switch is electrically connected to the other end of the third capacitor and the negative output terminal of the multiplexing unit, respectively, and the tenth switch is electrically connected to the other end of the fourth capacitor and the positive output terminal of the multiplexing unit, respectively; the second set of switches comprises: an eleventh switch, a twelfth switch, a thirteenth switch, a fourteenth switch, a fifteenth switch, and a sixteenth switch; the eleventh switch is electrically connected to a common node of the multiplexing unit, the ninth switch, the positive input terminal of the first comparator, the thirty-first field effect transistor, and the thirty-second field effect transistor, respectively; the twelfth switch is electrically connected to the multiplexing unit and the grid electrode of the thirty-first field effect transistor respectively; the thirteenth switch is electrically connected to the multiplexing unit and the grid of the thirty-second field effect transistor respectively; the fourteenth switch is electrically connected to the multiplexing unit and the gate of the thirty-third field effect transistor respectively; the fifteenth switch is electrically connected to the multiplexing unit and the grid electrode of the thirty-fourth field effect transistor respectively; the sixteenth switch is electrically connected to the multiplexing unit, the tenth switch, the positive input end of the second comparator, and a common node of the thirty-third and thirty-fourth field effect transistors, respectively.

8. The novel audio power amplifier of claim 3, wherein the multiplexing unit further comprises: the device comprises a first unit, a second unit and a third unit, wherein the second unit is electrically connected to the first unit, and the third unit is electrically connected to the second unit; the first unit includes: the first field effect transistor, the second field effect transistor, the third field effect transistor, the fourth field effect transistor, the fifth field effect transistor, the sixth field effect transistor, the seventh field effect transistor, the eighth field effect transistor, the ninth field effect transistor, the tenth field effect transistor, the eleventh field effect transistor, the twelfth field effect transistor, the thirteenth field effect transistor, the fourteenth field effect transistor, the fifteenth field effect transistor, the sixteenth field effect transistor, the first switch, the second switch, the third switch and the fourth switch; the grid electrode of the first field effect tube is electrically connected to the negative input end of the multiplexing unit, the source electrode of the first field effect tube is electrically connected to the drain electrode of the sixteenth field effect tube and the source electrode of the second field effect tube respectively, and the drain electrode of the first field effect tube is electrically connected to the drain electrode of the thirteenth field effect tube and the source electrode of the eleventh field effect tube respectively; a grid electrode of the second field effect transistor is electrically connected to the positive input end of the multiplexing unit, a source electrode of the second field effect transistor is electrically connected to a drain electrode of the sixteenth field effect transistor, and drain electrodes of the second field effect transistor are respectively and electrically connected to a drain electrode of the fourteenth field effect transistor and a source electrode of the twelfth field effect transistor; a source electrode of the fifteenth field effect transistor receives a power supply voltage, a grid electrode of the fifteenth field effect transistor is respectively and electrically connected to a grid electrode of the third field effect transistor and a grid electrode of the fourth field effect transistor and receives a first bias voltage, and a drain electrode of the fifteenth field effect transistor is electrically connected to a source electrode of the sixteenth field effect transistor; the grid electrode of the sixteenth field effect transistor is respectively and electrically connected to the grid electrode of the fifth field effect transistor and the grid electrode of the sixth field effect transistor and receives a second bias voltage; the source electrode of the third field effect transistor receives a power supply voltage, the grid electrode of the third field effect transistor is electrically connected to the grid electrode of the fourth field effect transistor, and the drain electrode of the third field effect transistor is electrically connected to the source electrode of the fifth field effect transistor; a grid electrode of the fifth field effect transistor is electrically connected to a grid electrode of the sixth field effect transistor, and a drain electrode of the fifth field effect transistor is respectively and electrically connected with a source electrode of the seventh field effect transistor and a drain electrode of the eighth field effect transistor; a source electrode of the seventh field effect transistor is electrically connected to a drain electrode of the eighth field effect transistor, a gate electrode of the seventh field effect transistor is electrically connected to one end of the third switch and one end of the fourth switch respectively, and a drain electrode of the seventh field effect transistor is electrically connected to a source electrode of the eighth field effect transistor and a drain electrode of the eleventh field effect transistor respectively; a grid electrode of the eighth field effect transistor is electrically connected to one end of the first switch, one end of the second switch and a grid electrode of the ninth field effect transistor respectively, and a source electrode of the eighth field effect transistor is electrically connected to a drain electrode of the eleventh field effect transistor; the grid electrode of the eleventh field effect transistor is electrically connected to the grid electrode of the twelfth field effect transistor and receives a third bias voltage, and the source electrode of the eleventh field effect transistor is electrically connected to the drain electrode of the thirteenth field effect transistor; the grid electrode of the thirteenth field effect transistor is electrically connected to the grid electrode of the fourteenth field effect transistor and receives a fourth bias voltage, and the source electrode of the thirteenth field effect transistor is grounded; a source electrode of the fourth field effect transistor receives a power supply voltage, a grid electrode of the fourth field effect transistor receives a first bias voltage, and a drain electrode of the fourth field effect transistor is electrically connected to a source electrode of the sixth field effect transistor; a grid electrode of the sixth field effect transistor receives a second bias voltage, and a drain electrode of the sixth field effect transistor is electrically connected to a drain electrode of the ninth field effect transistor and a source electrode of the tenth field effect transistor respectively; a drain electrode of the ninth field effect transistor is electrically connected to a source electrode of the tenth field effect transistor, a gate electrode of the ninth field effect transistor is electrically connected to one end of the first switch and one end of the second switch respectively, and a source electrode of the ninth field effect transistor is electrically connected to a drain electrode of the tenth field effect transistor and a drain electrode of the twelfth field effect transistor respectively; a grid electrode of the tenth field effect transistor is electrically connected to one end of the third switch and one end of the fourth switch respectively, and a drain electrode of the tenth field effect transistor is electrically connected to a drain electrode of the twelfth field effect transistor; a grid electrode of the twelfth field effect transistor receives a third bias voltage, and a source electrode of the twelfth field effect transistor is electrically connected to a drain electrode of the fourteenth field effect transistor; a grid electrode of the fourteenth field effect transistor receives a fourth bias voltage, and a source electrode of the fourteenth field effect transistor is grounded; the other end of the first switch receives a power supply voltage, the other end of the second switch receives a fifth bias voltage, the other end of the third switch receives a sixth bias voltage, and the other end of the fourth switch is grounded.

9. The novel audio power amplifier of claim 8, wherein the second unit comprises: a seventeenth field effect transistor, an eighteenth field effect transistor, a nineteenth field effect transistor, a twentieth field effect transistor, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a fifth capacitor and a sixth capacitor; a source electrode of the seventeenth field-effect transistor receives a power supply voltage, a gate electrode of the seventeenth field-effect transistor is electrically connected to one end of the fifth switch and one end of the sixth switch respectively, and a drain electrode of the seventeenth field-effect transistor is electrically connected to one end of the fifth capacitor and a drain electrode of the nineteenth field-effect transistor respectively; the drain electrode of the nineteenth field effect transistor is electrically connected to one end of the fifth capacitor, the gate electrode of the nineteenth field effect transistor is electrically connected to the other end of the fifth capacitor, and the source electrode of the nineteenth field effect transistor is grounded; a source electrode of the eighteenth field effect transistor receives a power supply voltage, a grid electrode of the eighteenth field effect transistor is electrically connected to one end of the seventh switch and one end of the eighth switch respectively, and a drain electrode of the eighteenth field effect transistor is electrically connected to one end of the sixth capacitor and the drain electrode of the twentieth field effect transistor respectively; the drain of the twentieth field effect transistor is electrically connected to one end of the sixth capacitor, the gate of the twentieth field effect transistor is electrically connected to the other end of the sixth capacitor, and the source of the twentieth field effect transistor is grounded; the other end of the fifth switch is electrically connected to the grid electrode of the fourth field effect transistor, the other end of the sixth switch is electrically connected to the drain electrode of the fifth field effect transistor, the other end of the seventh switch is electrically connected to the grid electrode of the fourth field effect transistor, and the other end of the eighth switch is electrically connected to the drain electrode of the sixth field effect transistor; the grid electrode of the nineteenth field effect transistor is electrically connected to the drain electrode of the eleventh field effect transistor, and the grid electrode of the twentieth field effect transistor is electrically connected to the drain electrode of the twelfth field effect transistor.

10. The novel audio power amplifier of claim 8, wherein the third unit comprises: a twenty-first field effect transistor, a twenty-second field effect transistor, a twenty-third field effect transistor, a twenty-fourth field effect transistor, a twenty-fifth field effect transistor, a twenty-sixth field effect transistor, a twenty-seventh field effect transistor, a twenty-eighth field effect transistor, a ninth resistor and a tenth resistor; a source electrode of the twenty-first field effect transistor receives a power supply voltage, a grid electrode of the twenty-first field effect transistor receives a first bias voltage, and a drain electrode of the twenty-first field effect transistor is electrically connected to a source electrode of the twenty-second field effect transistor; a grid electrode of the twenty-second field effect transistor receives a second bias voltage, and a drain electrode of the twenty-second field effect transistor is electrically connected to a source electrode of the twenty-third field effect transistor and a source electrode of the twenty-fourth field effect transistor respectively; a grid electrode of the twenty-third field effect transistor is electrically connected to one end of the ninth resistor and one end of the tenth resistor respectively, and a drain electrode of the twenty-third field effect transistor is electrically connected to a drain electrode of the twenty-fifth field effect transistor and a grid electrode of the twenty-seventh field effect transistor respectively; a grid electrode of the twenty-fifth field effect transistor receives a third bias voltage, and a source electrode of the twenty-fifth field effect transistor is electrically connected to a drain electrode of the twenty-seventh field effect transistor;

a grid electrode of the twenty-seventh field effect transistor receives a fourth bias voltage, and a source electrode of the twenty-seventh field effect transistor is grounded; a source electrode of the twenty-fourth field effect transistor is electrically connected to a source electrode of the twenty-third field effect transistor, a gate electrode of the twenty-fourth field effect transistor receives a reference voltage, and a drain electrode of the twenty-fourth field effect transistor is electrically connected to a drain electrode of the twenty-sixth field effect transistor and a gate electrode of the twenty-eighth field effect transistor respectively; a grid electrode of the twenty-sixth field effect transistor receives a third bias voltage, and a source electrode of the twenty-sixth field effect transistor is electrically connected to a drain electrode of the twenty-eighth field effect transistor; and the source electrode of the twenty-eighth field effect transistor is grounded.

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a novel audio power amplifier.

Background

The class-D power amplifier circuit is a switch-type power amplifier circuit, and the working principle of the switch-type power amplifier circuit is based on a PWM mode, an audio signal is compared with a triangular wave, a PWM waveform with the pulse width in direct proportion to the amplitude of the audio signal is output, then the amplitude of the PWM waveform is amplified, and the amplified PWM waveform is restored into an amplified audio signal after being filtered. Compared with a linear power amplifier circuit, the D-type power amplifier circuit has the characteristics of high efficiency and less heat generation, so that the D-type power amplifier circuit is widely applied to the fields of consumer electronics products such as smart televisions and smart phones.

The AB class power amplifier circuit adopts an AB class amplifier, the efficiency of the AB class power amplifier circuit is higher than that of an A class amplifier, and the distortion of the AB class power amplifier circuit is lower than that of a B class amplifier. Two transistors in the circuit are biased to be conducted when a signal is close to zero; at small signals, the transistors all keep working effectively, similar to a class A amplifier; for large signals, only one transistor remains active, corresponding to each half cycle of the waveform, similar to a class B amplifier.

Researchers have found that, in order to solve the problem of electromagnetic interference (EMI), an AB class power amplifier circuit and a D class power amplifier circuit are usually integrated into one chip in the conventional audio chip. When the chip is in a D-type mode, the chip mainly comprises a front-end operational amplifier, an integrator, a comparator and a driver. When the chip is in the AB mode, the operation of the front-stage operational amplifier and the operational amplifier circuit is mainly included. That is, in the circuit system of the existing audio chip, the class AB power amplifier circuit and the class D power amplifier circuit are implemented by two operational amplifier circuits, respectively. This results in a chip size having both operational amplifier circuits having to be increased, which also increases the chip cost.

In view of the development of miniaturization of chips, how to improve the chip design with these two op-amp circuits becomes an important research project for relevant researchers.

Disclosure of Invention

The invention aims to provide a novel audio power amplifier, which multiplexes a circuit playing an integral role in a D-type power amplifier circuit and a circuit playing an operational amplification role in an AB-type power amplifier circuit into a folding cascode circuit, and then utilizes the characteristics of high output impedance, high gain and easiness in compensation of the folding cascode circuit, so that under the condition of greatly improving the performance, the area of a chip is saved, the cost of the chip is reduced, the workload of the layout design of an integrated circuit can be reduced, and the design time is saved.

According to an aspect of the present invention, there is provided a novel audio power amplifier, comprising: a first operational amplifier module; the multiplexing module is electrically connected with the first operational amplifier module and comprises a multiplexing circuit, a first group of switches and a second group of switches, and the multiplexing circuit is electrically connected with the first group of switches and the second group of switches respectively; the comparison module is electrically connected with the multiplexing module; the driving module is electrically connected with the comparison module; the load module is electrically connected with the driving module; when the first group of switches is closed and the second group of switches is open, the output end of the multiplexing circuit is electrically connected to the comparison module, so that the multiplexing module is switched to be an integration module, and the novel audio power amplifier operates in a class D power amplifier mode; when the first group of switches is off and the second group of switches is on, the output end of the multiplexing circuit is electrically connected to the load module, so that the multiplexing module is switched to be used as a second operational amplifier module, and the novel audio power amplifier operates in an AB type power amplification mode.

On the basis of the above technical solution, the present invention may be improved as follows.

In an embodiment of the present invention, the first operational amplifier module includes: the circuit comprises a first capacitor, a second capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor and a first operational amplifier; one end of the first capacitor receives the positive input end, and the other end of the first capacitor is electrically connected with one end of the first resistor; one end of the second capacitor receives the negative input end, and the other end of the second capacitor is electrically connected with one end of the second resistor; the other end of the first resistor is electrically connected to one end of the third resistor and the positive input end of the first operational amplifier respectively; the other end of the second resistor is electrically connected to one end of the fourth resistor and the negative input end of the first operational amplifier respectively; the other end of the third resistor is electrically connected to the negative output end of the first operational amplifier, and the other end of the fourth resistor is electrically connected to the positive output end of the first operational amplifier.

In an embodiment of the present invention, the multiplexing circuit includes: the first resistor, the second resistor, the third resistor, the fourth resistor, the seventh resistor and the eighth resistor are connected in series; one end of the fifth resistor is electrically connected to the other end of the third resistor and the negative output end of the first operational amplifier, and the other end of the fifth resistor is electrically connected to one end of the seventh resistor, one end of the third capacitor, and the positive input end of the multiplexing unit; one end of the sixth resistor is electrically connected to the other end of the fourth resistor and the positive output end of the first operational amplifier, and the other end of the sixth resistor is electrically connected to one end of the eighth resistor, one end of the fourth capacitor and the negative input end of the multiplexing unit; the other end of the third capacitor is electrically connected to a ninth switch in the first group of switches, and the ninth switch is electrically connected to the negative output end of the multiplexing unit; the other end of the fourth capacitor is electrically connected to a tenth switch in the first group of switches, and the tenth switch is electrically connected to the positive output end of the multiplexing unit.

In an embodiment of the present invention, the comparing module includes: a first comparator and a second comparator; the positive input end of the first comparator is electrically connected to the negative output end of the multiplexing unit, the positive input end of the second comparator is electrically connected to the positive output end of the multiplexing unit, and the negative input end of the first comparator and the negative input end of the second comparator receive a triangular wave signal.

In an embodiment of the present invention, the driving module includes: the first driver, the second driver, the first output pair of tubes and the second output pair of tubes; the input end of the first driver is electrically connected to the output end of the first comparator, and the input end of the second driver is electrically connected to the output end of the second comparator; the first output pair transistors comprise a thirty-first field effect transistor and a thirty-second field effect transistor; the second output pair transistor comprises a thirty-third field effect transistor and a thirty-fourth field effect transistor; a source electrode of the thirty-first field effect transistor receives a power supply voltage, a grid electrode of the thirty-first field effect transistor is electrically connected to the first output end of the first driver, and a drain electrode of the thirty-first field effect transistor is electrically connected to a drain electrode of the thirty-second field effect transistor; the grid electrode of the thirty-second field effect transistor is electrically connected to the second output end of the first driver, and the source electrode of the thirty-second field effect transistor is grounded; a source electrode of the thirty-third field effect transistor receives a power supply voltage, a grid electrode of the thirty-third field effect transistor is electrically connected to the first output end of the second driver, and a drain electrode of the thirty-third field effect transistor is electrically connected to a drain electrode of the thirty-fourth field effect transistor; the gate of the thirty-fourth field effect transistor is electrically connected to the second output end of the second driver, and the source of the thirty-fourth field effect transistor is grounded.

In an embodiment of the invention, the load module comprises a load connected to a common node of the thirty-first and thirty-second fets and a common node of the thirty-third and thirty-fourth fets.

In an embodiment of the invention, the first group of switches includes a ninth switch and a tenth switch, the ninth switch is electrically connected to the other end of the third capacitor and the negative output terminal of the multiplexing unit, respectively, and the tenth switch is electrically connected to the other end of the fourth capacitor and the positive output terminal of the multiplexing unit, respectively; the second set of switches comprises: an eleventh switch, a twelfth switch, a thirteenth switch, a fourteenth switch, a fifteenth switch, and a sixteenth switch; the eleventh switch is electrically connected to the multiplexing unit, the ninth switch, the positive input terminal of the first comparator, and a common node of the twenty-first field effect transistor and the twenty-second field effect transistor, respectively; the twelfth switch is electrically connected to the multiplexing unit and the grid electrode of the twenty-first field effect transistor respectively; the thirteenth switch is electrically connected to the multiplexing unit and the grid electrode of the twenty-second field effect transistor respectively; the fourteenth switch is electrically connected to the multiplexing unit and the grid electrode of the twenty-third field effect transistor respectively; the fifteenth switch is electrically connected to the multiplexing unit and the grid electrode of the twenty-fourth field effect transistor respectively; the sixteenth switch is electrically connected to the multiplexing unit, the tenth switch, the positive input end of the second comparator, and the common node of the twenty-third fet and the twenty-fourth fet, respectively.

In an embodiment of the present invention, the multiplexing unit further includes: the device comprises a first unit, a second unit and a third unit, wherein the second unit is electrically connected to the first unit, and the third unit is electrically connected to the second unit; the first unit includes: the first field effect transistor, the second field effect transistor, the third field effect transistor, the fourth field effect transistor, the fifth field effect transistor, the sixth field effect transistor, the seventh field effect transistor, the eighth field effect transistor, the ninth field effect transistor, the tenth field effect transistor, the eleventh field effect transistor, the twelfth field effect transistor, the thirteenth field effect transistor, the fourteenth field effect transistor, the fifteenth field effect transistor, the sixteenth field effect transistor, the first switch, the second switch, the third switch and the fourth switch; the grid electrode of the first field effect tube is electrically connected to the negative input end of the multiplexing unit, the source electrode of the first field effect tube is electrically connected to the drain electrode of the sixteenth field effect tube and the source electrode of the second field effect tube respectively, and the drain electrode of the first field effect tube is electrically connected to the drain electrode of the thirteenth field effect tube and the source electrode of the eleventh field effect tube respectively; a grid electrode of the second field effect transistor is electrically connected to the positive input end of the multiplexing unit, a source electrode of the second field effect transistor is electrically connected to a drain electrode of the sixteenth field effect transistor, and drain electrodes of the second field effect transistor are respectively and electrically connected to a drain electrode of the fourteenth field effect transistor and a source electrode of the twelfth field effect transistor; a source electrode of the fifteenth field effect transistor receives a power supply voltage, a grid electrode of the fifteenth field effect transistor is respectively and electrically connected to a grid electrode of the third field effect transistor and a grid electrode of the fourth field effect transistor and receives a first bias voltage, and a drain electrode of the fifteenth field effect transistor is electrically connected to a source electrode of the sixteenth field effect transistor; the grid electrode of the sixteenth field effect transistor is respectively and electrically connected to the grid electrode of the fifth field effect transistor and the grid electrode of the sixth field effect transistor and receives a second bias voltage; the source electrode of the third field effect transistor receives a power supply voltage, the grid electrode of the third field effect transistor is electrically connected to the grid electrode of the fourth field effect transistor, and the drain electrode of the third field effect transistor is electrically connected to the source electrode of the fifth field effect transistor; a grid electrode of the fifth field effect transistor is electrically connected to a grid electrode of the sixth field effect transistor, and a drain electrode of the fifth field effect transistor is respectively and electrically connected with a source electrode of the seventh field effect transistor and a drain electrode of the eighth field effect transistor; a source electrode of the seventh field effect transistor is electrically connected to a drain electrode of the eighth field effect transistor, a gate electrode of the seventh field effect transistor is electrically connected to one end of the third switch and one end of the fourth switch respectively, and a drain electrode of the seventh field effect transistor is electrically connected to a source electrode of the eighth field effect transistor and a drain electrode of the eleventh field effect transistor respectively; a grid electrode of the eighth field effect transistor is electrically connected to one end of the first switch, one end of the second switch and a grid electrode of the ninth field effect transistor respectively, and a source electrode of the eighth field effect transistor is electrically connected to a drain electrode of the eleventh field effect transistor; the grid electrode of the eleventh field effect transistor is electrically connected to the grid electrode of the twelfth field effect transistor and receives a third bias voltage, and the source electrode of the eleventh field effect transistor is electrically connected to the drain electrode of the thirteenth field effect transistor; the grid electrode of the thirteenth field effect transistor is electrically connected to the grid electrode of the fourteenth field effect transistor and receives a fourth bias voltage, and the source electrode of the thirteenth field effect transistor is grounded; a source electrode of the fourth field effect transistor receives a power supply voltage, a grid electrode of the fourth field effect transistor receives a first bias voltage, and a drain electrode of the fourth field effect transistor is electrically connected to a source electrode of the sixth field effect transistor; a grid electrode of the sixth field effect transistor receives a second bias voltage, and a drain electrode of the sixth field effect transistor is electrically connected to a drain electrode of the ninth field effect transistor and a source electrode of the tenth field effect transistor respectively; a drain electrode of the ninth field effect transistor is electrically connected to a source electrode of the tenth field effect transistor, a gate electrode of the ninth field effect transistor is electrically connected to one end of the first switch and one end of the second switch respectively, and a source electrode of the ninth field effect transistor is electrically connected to a drain electrode of the tenth field effect transistor and a drain electrode of the twelfth field effect transistor respectively; a grid electrode of the tenth field effect transistor is electrically connected to one end of the third switch and one end of the fourth switch respectively, and a drain electrode of the tenth field effect transistor is electrically connected to a drain electrode of the twelfth field effect transistor; a grid electrode of the twelfth field effect transistor receives a third bias voltage, and a source electrode of the twelfth field effect transistor is electrically connected to a drain electrode of the fourteenth field effect transistor; a grid electrode of the fourteenth field effect transistor receives a fourth bias voltage, and a source electrode of the fourteenth field effect transistor is grounded; the other end of the first switch receives a power supply voltage, the other end of the second switch receives a fifth bias voltage, the other end of the third switch receives a sixth bias voltage, and the other end of the fourth switch is grounded.

In an embodiment of the present invention, the second unit includes: a seventeenth field effect transistor, an eighteenth field effect transistor, a nineteenth field effect transistor, a twentieth field effect transistor, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a fifth capacitor and a sixth capacitor; a source electrode of the seventeenth field-effect transistor receives a power supply voltage, a gate electrode of the seventeenth field-effect transistor is electrically connected to one end of the fifth switch and one end of the sixth switch respectively, and a drain electrode of the seventeenth field-effect transistor is electrically connected to one end of the fifth capacitor and a drain electrode of the nineteenth field-effect transistor respectively; the drain electrode of the nineteenth field effect transistor is electrically connected to one end of the fifth capacitor, the gate electrode of the nineteenth field effect transistor is electrically connected to the other end of the fifth capacitor, and the source electrode of the nineteenth field effect transistor is grounded; a source electrode of the eighteenth field effect transistor receives a power supply voltage, a grid electrode of the eighteenth field effect transistor is electrically connected to one end of the seventh switch and one end of the eighth switch respectively, and a drain electrode of the eighteenth field effect transistor is electrically connected to one end of the sixth capacitor and the drain electrode of the twentieth field effect transistor respectively; the drain of the twentieth field effect transistor is electrically connected to one end of the sixth capacitor, the gate of the twentieth field effect transistor is electrically connected to the other end of the sixth capacitor, and the source of the twentieth field effect transistor is grounded; the other end of the fifth switch is electrically connected to the grid electrode of the fourth field effect transistor, the other end of the sixth switch is electrically connected to the drain electrode of the fifth field effect transistor, the other end of the seventh switch is electrically connected to the grid electrode of the fourth field effect transistor, and the other end of the eighth switch is electrically connected to the drain electrode of the sixth field effect transistor; the grid electrode of the nineteenth field effect transistor is electrically connected to the drain electrode of the eleventh field effect transistor, and the grid electrode of the twentieth field effect transistor is electrically connected to the drain electrode of the twelfth field effect transistor.

In an embodiment of the present invention, the third unit includes: a twenty-first field effect transistor, a twenty-second field effect transistor, a twenty-third field effect transistor, a twenty-fourth field effect transistor, a twenty-fifth field effect transistor, a twenty-sixth field effect transistor, a twenty-seventh field effect transistor, a twenty-eighth field effect transistor, a ninth resistor and a tenth resistor; a source electrode of the twenty-first field effect transistor receives a power supply voltage, a grid electrode of the twenty-first field effect transistor receives a first bias voltage, and a drain electrode of the twenty-first field effect transistor is electrically connected to a source electrode of the twenty-second field effect transistor; a grid electrode of the twenty-second field effect transistor receives a second bias voltage, and a drain electrode of the twenty-second field effect transistor is electrically connected to a source electrode of the twenty-third field effect transistor and a source electrode of the twenty-fourth field effect transistor respectively; a grid electrode of the twenty-third field effect transistor is electrically connected to one end of the ninth resistor and one end of the tenth resistor respectively, and a drain electrode of the twenty-third field effect transistor is electrically connected to a drain electrode of the twenty-fifth field effect transistor and a grid electrode of the twenty-seventh field effect transistor respectively; a grid electrode of the twenty-fifth field effect transistor receives a third bias voltage, and a source electrode of the twenty-fifth field effect transistor is electrically connected to a drain electrode of the twenty-seventh field effect transistor; a grid electrode of the twenty-seventh field effect transistor receives a fourth bias voltage, and a source electrode of the twenty-seventh field effect transistor is grounded; a source electrode of the twenty-fourth field effect transistor is electrically connected to a source electrode of the twenty-third field effect transistor, a gate electrode of the twenty-fourth field effect transistor receives a reference voltage, and a drain electrode of the twenty-fourth field effect transistor is electrically connected to a drain electrode of the twenty-sixth field effect transistor and a gate electrode of the twenty-eighth field effect transistor respectively; a grid electrode of the twenty-sixth field effect transistor receives a third bias voltage, and a source electrode of the twenty-sixth field effect transistor is electrically connected to a drain electrode of the twenty-eighth field effect transistor; and the source electrode of the twenty-eighth field effect transistor is grounded.

The novel audio power amplifier has the advantages that the circuit playing the integrating role in the D-class power amplifier circuit and the circuit playing the operational amplifying role in the AB-class power amplifier circuit are multiplexed in the folding cascode circuit, and the characteristics of high output impedance, high gain and easiness in compensation of the folding cascode are utilized, so that under the condition of greatly improving the performance, the area of a chip is saved, the cost of the chip is reduced, the workload of the layout design of an integrated circuit can be reduced, and the design time is saved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic diagram of a novel audio power amplifier according to an embodiment of the present invention.

Fig. 2 is a schematic circuit connection diagram of the novel audio power amplifier in the embodiment of the invention.

Fig. 3 is a schematic circuit connection diagram of the first unit inside the multiplexing unit shown in fig. 2.

Fig. 4 is a schematic circuit connection diagram of a second unit inside the multiplexing unit shown in fig. 2.

Fig. 5 is a schematic circuit connection diagram of a third unit inside the multiplexing unit shown in fig. 2.

Detailed Description

The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.